DETAILED ACTION
This action is responsive to the amendment and RCE received on 05/15/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/15/2026 has been entered.
Election/Restrictions
Applicant’s election without traverse of Species A (Figure 2) in the reply filed on 09/23/2025 is acknowledged. Claim(s) 4, 5, 7, 9, and 10 is/are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to nonelected species without traverse, there being no allowable generic or linking claim. Reasons for their withdrawal and the respective non-elected species they appear to be drawn to were detailed in the Non-Final Rejection mailed on 11/26/2025.
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in REPUBLIC OF KOREA on 05/30/2022.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 6, 8, 12-16, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0122695 A1; Lee et al.; 05/2018; (“Lee”) in view of US 20190006381 A1; Nakatsuji et al.; 01/2019; (“Nakatsuji”) and US 2022/0375529 A1; Yamazaki et al.; 11/2022; (“Yamazaki”). An annotated version of Figure 7A from Lee is provided below and used in the following rejections.
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Regarding Claim 1. Lee discloses A semiconductor device (Figures 7A and 7B, semiconductor device where Figure 8 is an enlarged view of Figure 7A according to [0033]-[0034]) comprising:
a peripheral circuit region (#PC, Figure 7A annotated) comprising:
a first substrate (#2, Figure 7A, semiconductor substrate);
circuit elements (#PTR1’ and #PTR2’, Figures 7A and 7B, peripheral transistors) disposed on the first substrate (Figures 7A and 7B, #PTR1’/2’ are disposed on #2);
a first interconnection structure (portions of #250a, Figure 8, first interconnection structure) electrically connected to the circuit elements (Figure 8, #250a is electrically connected to #PTR1’);
a first peripheral region insulating layer (#LILD1’, Figure 7A, first lower interlayer insulating layer) covering the circuit elements (Figure 7A, #LILD1’ covers #PTR1’/2’), wherein the circuit elements protrude into the first peripheral region insulating layer (Figures 7A and 8, the gate structures of #PTR1’/2’ protrude into #LILD1’);
a second peripheral region insulating layer (#LILD2’, Figure 7A, second lower interlayer insulating layer) disposed on the first peripheral region insulating layer (Figure 7A, #LILD2’ is on #LILD1’);
a third peripheral region insulating layer (#LILD3’, Figure 7A, third lower interlayer insulating layer) disposed on the second peripheral region insulating layer (Figure 7A, #LILD3’ is on #LILD2’); and
a fourth peripheral region insulating layer (#LILD4’, Figure 7A, fourth lower interlayer insulating layer) disposed on the third peripheral region insulating layer (Figure 7A, #LILD4’ is on #LILD3’); and
a memory cell region (#MC, Figure 7A annotated) comprising:
a second substrate (#MILD and #252, Figure 7A, intermediate interlayer insulating layer and semiconductor pattern) disposed on the peripheral circuit region (Figure 7A annotated, #MILD and #252 are on #PC) and having a first region (#MC1, Figure 7A annotated) and a second region (#MC2, Figure 7A annotated);
gate electrodes (#CGs, Figure 7A, cell gates) stacked on the first region of the second substrate (Figure 7A annotated, #CGs are stacked on #MC1) and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate (Figure 7A, #CGs are spaced apart from each other in a vertical first direction perpendicular to an upper surface of #252), and extending in a stepped shape in a second direction perpendicular to the first direction (Figures 7A and 7B, #CGs extend in a stepped shape in a second horizontal direction perpendicular to the vertical direction), on the second region of the second substrate (Figures 7A annotated and 7B, stepped shape of #CGs is on #MC2);
interlayer insulating layers (#CILDs, Figure 7A, cell interlayer insulating layers) alternately stacked with the gate electrodes (Figure 7A, #CILDs are alternately stacked with #CGs);
a cell region insulating layer (#UILD, Figure 7A, upper interlayer insulating layer) covering the gate electrodes (Figures 7A and 7B, #UILD is covering #CGs);
channel structures (#CV, Figure 7A, [0085], “three-dimensional memory array may include . . . a plurality of cell vertical structures CV”) passing through the gate electrodes and vertically extending from the second substrate (Figure 7A, #CV passes through #CGs and extends from #252), each of the channel structures comprising a channel layer (#62, [0091], “Each of the plurality of cell vertical structures CV may include . . . a cell semiconductor layer 62” which functions as the channel of the memory cell); and
a second interconnection structure (#282a, #283a, #286a, etc. and #280b, #282b, #286b, etc., Figures 7A and 7B, contact and interconnection structures) electrically connected to the gate electrodes and the channel structures (Figures 7A and 7B, the contact and interconnection structures are electrically connected to #CGs (Figure 7B) and #CVs (Figure 7A)),
wherein the peripheral circuit region (#PC, Figure 8) further comprises:
a second lower protective layer (#219, Figure 8, lower capping layer) disposed between the first peripheral region insulating layer and the second peripheral region insulating layer (Figure 8, #219 is between #LILD1’ and #LILD2’);
a third lower protective layer (#227, Figure 8, first intermediate capping layer) disposed between the second peripheral region insulating layer and the third peripheral region insulating layer (Figure 8, #227 is between #LILD2’ and #LILD3’); and
a fourth lower protective layer (#237, Figure 8, second intermediate capping layer) disposed between the third peripheral region insulating layer and the fourth peripheral region insulating layer (Figure 8, #237 is between #LILD3’ and #LILD4’).
Lee does not disclose a first lower protective layer disposed below the first peripheral region insulating layer, wherein a lower surface of the first lower protective layer is located at a same vertical level as an upper surface of the first substrate;
wherein at least one of the first lower protective layer, the second lower protective layer, the third lower protective layer, and the fourth lower protective layer comprises a hydrogen diffusion barrier layer configured to inhibit a hydrogen element in the cell region insulating layer from diffusing to the circuit elements, and
wherein the hydrogen diffusion barrier layer comprises aluminum oxide.
However, Nakatsuji teaches a semiconductor device (Figure 21) comprising a peripheral circuit region (#700, peripheral device region) and a memory cell region (#100, memory array region), wherein the peripheral circuit region comprises a first lower protective layer (#762, dielectric liner) disposed below a first peripheral region insulating layer (#764, dielectric material layer), wherein a lower surface of the first lower protective layer is located at a same vertical level as an upper surface of a first substrate (#9, substrate semiconductor layer which has an upper surface at the same vertical level as a lower surface of #762) and circuit elements (#710, Figure 1, semiconductor devices) protrude into the first peripheral region insulating layer (Figures 1 and 21, the gate structures #750 of #710s protrude into #764).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the first lower protective layer from Nakatsuji between the first peripheral region insulating layer and the substrate and peripheral circuit devices in Lee since it “blocks diffusion of mobile ions and/or apply appropriate stress to underlying structures” according to Nakatsuji (see [0044] of Nakatsuji).
Lee in view of Nakatsuji do not explicitly disclose that at least one of the first lower protective layer, the second lower protective layer, the third lower protective layer, and the fourth lower protective layer comprises a hydrogen diffusion barrier layer configured to inhibit a hydrogen element in the cell region insulating layer from diffusing to the circuit elements, and wherein the hydrogen diffusion barrier layer comprises aluminum oxide.
However, Lee discloses that the first lower protective layer (#219), the second lower protective layer (#227), the third lower protective layer (#237), and the fourth lower protective layer (#249) comprise silicon nitride ([0127], “219, 227, 237, and 249 may be formed with a nitride-based insulating layer (e.g., a silicon nitride layer)”) and Nakatsuji teaches that the silicon nitride dielectric liner (#762) functions to prevent the diffusion of mobile ions ([0044]).
Yamazaki teaches in [0259] that “For the film having a barrier property against hydrogen, silicon nitride formed by a chemical vapor deposition (CVD) method can be used” (i.e. silicon nitride is a known barrier material which may inhibit hydrogen element diffusion) and further teaches a semiconductor memory device (Figure 14, memory device according to [0242]) comprising a memory core (#20) and a peripheral circuit structure (#40), and a plurality of protective layers (#510 and #514, insulators) which may have a barrier property against hydrogen diffusion ([0344], “insulator 510 and the insulator 514 are preferably formed using, for example, a film having a barrier property that prevents diffusion of hydrogen”) wherein the hydrogen diffusion barrier material comprises aluminum oxide ([0346], “For the film having a barrier property against hydrogen used for the insulator 510 and the insulator 514, for example, a metal oxide such as aluminum oxide . . . is preferably used”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming at least one, or any plurality, of the protective layers of Lee in view of Nakatsuji out of the hydrogen barrier material aluminum oxide as taught by Yamazaki as substituting equivalents known for the same purpose (see MPEP 2144.06.II) since “aluminum oxide has a high blocking effect that inhibits the passage of both oxygen and impurities such as hydrogen” (see [0347] of Yamazaki).
Regarding Claim 2. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 1, wherein the first lower protective layer comprises silicon nitride (Nakatsuji, [0044], “dielectric liner 762 such as a silicon nitride”), and
wherein each of the second lower protective layer and the third lower protective layer comprises the hydrogen diffusion barrier layer (Lee, [0127], “219, 227 . . . may be formed with a nitride-based insulating layer (e.g., a silicon nitride layer)” and may be converted to aluminum oxide from Yamazaki as substituting equivalents known for the same purpose (see MPEP 2144.06.II) as described in claim 1).
Regarding Claim 3. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 2, wherein the fourth lower protective layer comprises silicon nitride (Lee, [0127], “237 . . . may be formed with a nitride-based insulating layer (e.g., a silicon nitride layer)”).
Regarding Claim 6. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 2, wherein the first interconnection structure (Lee, portions of #250a, Figure 8, first interconnection structure) comprises a first lower interconnection line (Lee, #218, Figure 8, lower interconnection structure), a second lower interconnection line (Lee, #226, Figure 8, first intermediate interconnection structure), and a third lower interconnection line (Lee, #234, Figure 8, second intermediate interconnection structure) disposed on different levels (Lee, Figure 8, #218, #226, and #234 are disposed on different vertical levels),
wherein the second lower protective layer covers an upper surface of the first lower interconnection line (Lee, Figure 8, #219 covers an upper surface of #218),
wherein the third lower protective layer covers an upper surface of the second lower interconnection line (Lee, Figure 8, #227 covers an upper surface of #226), and
wherein the fourth lower protective layer covers an upper surface of the third lower interconnection line (Lee, Figure 8, #237 covers an upper surface of #234).
Regarding Claim 8. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 3,
Lee in view of Nakatsuji and Yamazaki do not explicitly disclose that each of the first lower protective layer and the fourth lower protective layer has a thickness in a range of 300 Å to 2000 Å, and
wherein each of the second lower protective layer and the third lower protective layer has a thickness in a range of 50 Å to 100 Å.
However, Yamazaki teaches in [0412] that “aluminum oxide has a high barrier property, and even a thin aluminum oxide film having a thickness greater than or equal to 0.5 nm (5 Å) and less than or equal to 3.0 nm (300 Å) can inhibit diffusion of hydrogen and nitrogen”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the second lower protective layer and the third protective layer of Lee in view of Nakatsuji and Yamazaki, formed of aluminum oxide, to have a thickness in the range of 50 Å to 100 Å in view of the range of 0.5 nm (5 Å) and less than or equal to 3.0 nm (300 Å) taught by Yamazaki as sufficient for inhibition of hydrogen diffusion since the two ranges are overlapping (see MPEP 2144.05.I)
Furthermore, Nakatsuji teaches a semiconductor memory device (Figure 21) comprising a hydrogen diffusion blocking layer (#766, Figure 21, silicon nitride layer (e.g., hydrogen diffusion barrier)) vertically separating a lower peripheral circuit structure from an upper memory structure, wherein the silicon nitride hydrogen diffusion barrier has a thickness between 6 nm (60 Å) and 100 nm (1000 Å) ([0049], “the thickness of the silicon nitride layer 766 can be in a range from 6 nm to 100 nm”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the first lower protective layer and the fourth lower protective layer of Lee in view of Nakatsuji and Yamazaki, formed of silicon nitride, to have a thickness in the range of 300 Å to 2000 Å in view of the range of 6 nm (60 Å) and 100 nm (1000 Å) taught by Nakatsuji as sufficient for inhibition of hydrogen diffusion since the two ranges are overlapping (see MPEP 2144.05.I)
Regarding Claim 12. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 3, wherein the memory cell region (Lee, #MC, Figure 7A annotated) further comprises an upper via (Lee, #242, #246, and #280a, Figures 7A annotated and 8, upper contact plug, upper interconnection, and bit line contact structure) connecting the first substrate and the second substrate (Lee, Figures 7A annotated and 8, #242, #246, and #280a at least partially forms the physical and electrical connections of #MILD/#252 and #2),
wherein the upper via extends from the second substrate (Lee, Figure 7A, #242, #246, and #280a extends in both the up and down directions from #MILD), and
wherein the upper via passes through the fourth lower protective layer (Lee, Figures 7A and 8, #242 passes through #237).
Regarding Claim 13. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 2, wherein the first interconnection structure (Lee, portions of #250a, Figure 8, first interconnection structure) comprises:
a first lower interconnection line (Lee, #216L, Figure 8, lower interconnection), a second lower interconnection line (Lee, #224L, Figure 8, first intermediate interconnection line), and a third lower interconnection line (Lee, #232L, Figure 8, second intermediate interconnection); and
a first lower contact plug (Lee, #216C, Figure 8, lower contact plug), a second lower contact plug (Lee, #224C, Figure 8, first intermediate contact plug), and a third lower contact plug (Lee, #232C, Figure 8, second intermediate contact plug),
wherein the first lower interconnection line interfaces with the first lower contact plug (Lee, Figure 8, #216L interfaces with #216C),
wherein the second lower interconnection line interfaces with the second lower contact plug (Lee, Figure 8, #224L interfaces with #224C), and
wherein the third lower interconnection line is integrally connected to the third lower contact plug (Lee, Figure 8, #232L is integrally connected to #232C).
Regarding Claim 14. Lee discloses A semiconductor device (Figures 7A and 7B, semiconductor device where Figure 8 is an enlarged view of Figure 7A according to [0033]-[0034]) comprising:
a first substrate (#2, Figure 7A, semiconductor substrate);
circuit elements (#PTR1’ and #PTR2’, Figures 7A and 7B, peripheral transistors) disposed on the first substrate (Figures 7A and 7B, #PTR1’/2’ are disposed on #2);
a first peripheral region insulating layer (#LILD1’, Figure 7A, first lower interlayer insulating layer), wherein the circuit elements protrude into the first peripheral region insulating layer (Figures 7A and 8, the gate structures of #PTR1’/2’ protrude into #LILD1’);
a first lower interconnection structure (#218, Figure 8, lower interconnection structure) penetrating through the first peripheral region insulating layer (Figure 8, #218 penetrates through #LILD1’) the first lower interconnection structure comprising a first lower contact plug (#216C, Figure 8, lower contact plug) and a first lower interconnection line (#216L, Figure 8, lower interconnection line);
a second lower protective layer (#219, Figure 8, lower capping layer) disposed on the first peripheral region insulating layer (Figure 8, #219 is on #LILD1’);
a second peripheral region insulating layer (#LILD2’, Figure 7A, second lower interlayer insulating layer) disposed on the second lower protective layer (Figure 8, #LILD2’ is on #219);
a second lower interconnection structure (#226, Figure 8, first intermediate interconnection structure) penetrating through the second peripheral region insulating layer (Figure 8, #226 penetrates through #LILD2’), the second lower interconnection structure comprising a second lower contact plug (#224C, Figure 8, first intermediate contact plug) and a second lower interconnection line (#224L, Figure 8, first intermediate interconnection);
a third lower protective layer (#227, Figure 8, first intermediate capping layer) disposed on the second peripheral region insulating layer (Figure 8, #227 is on #LILD2’);
a third peripheral region insulating layer (#LILD3’, Figure 7A, third lower interlayer insulating layer) disposed on the third lower protective layer (Figure 7A, #LILD3’ is on #227);
a third lower interconnection structure (#234, Figure 8, second intermediate interconnection structure) penetrating through the third peripheral region insulating layer (Figure 8, #234 penetrates through #LILD3’), the third lower interconnection structure comprising a third lower contact plug (#232C, Figure 8, second intermediate contact plug) and a third lower interconnection line (#232L, Figure 8, second intermediate interconnection);
a fourth lower protective layer (#237, Figure 8, second intermediate capping layer) disposed on the third peripheral region insulating layer (Figure 8, #237 is on #LILD3’);
a fourth peripheral region insulating layer (#LILD4’, Figure 7A, fourth lower interlayer insulating layer) disposed on the fourth lower protective layer (Figure 7A, #LILD4’ is on #237);
a memory structure (#MC, Figure 7A annotated) disposed on the fourth peripheral region insulating layer (Figure 7A annotated, #MC is on #LILD4’), the memory structure comprising gate electrodes (#CGs, Figure 7A annotated, cell gates) and channel structures (#CV, Figure 7A annotated, [0085], “three-dimensional memory array may include . . . a plurality of cell vertical structures CV”) passing through the gate electrodes (Figure 7A, #CVs pass through #CGs);
a first cell region insulating layer (#UILD1, Figure 20A of the method of making the device and part of #UILD in Figure 7A, first upper interlayer insulating layer) disposed on the fourth peripheral region insulating layer (Figure 20A, #UILD1 is on #LILD4’) and covering the memory structure (Figure 120A, #UILD1 covers the memory structure); and
a first upper protective layer (#UILD2, Figure 20A and part of #UILD in Figure 7A, second upper interlayer insulating layer), a second cell region insulating layer (#UILD3, Figure 20A and part of #UILD in Figure 7A, third upper interlayer insulating layer), a second upper protective layer (#UILD4, Figure 20A and part of #UILD in Figure 7A, fourth upper interlayer insulating layer), and a third cell region insulating layer (#UILD5, Figure 20A and part of #UILD in Figure 7A, fifth upper interlayer insulating layer) sequentially stacked on the first cell region insulating layer (Figure 20A, #UILD2-5 are sequentially stacked on #UILD1),
wherein a thickness of the third lower interconnection line (horizontal width of #232L, Figure 8) is greater than a thickness of each of the first lower interconnection line (horizontal width of #216L, Figure 8) and the second lower interconnection line (horizontal width of #224L, Figure 8) (Figure 8, the horizontal width of #232L is greater than the horizontal width of #224L and #216L),
wherein a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first upper protective layer and the second upper protective layer (Figure 20A, the thickness of #219 and #227 are each less than a thickness of #UILD2 and #UILD4).
Lee does not disclose a first lower protective layer covering the circuit elements, wherein the first peripheral region insulating layer is disposed on the first lower protective layer, and a lower surface of the first lower protective layer is located at a same vertical level as an upper surface of the first substrate,
a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first lower protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a second material different from a first material of the first lower protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a hydrogen diffusion barrier layer configured to inhibit a hydrogen element each of in the first cell region insulating layer, the second cell region insulating layer, and the third cell region insulating layer from diffusing to the circuit elements, and
the hydrogen diffusion barrier layer comprises the second material, and
wherein the second material is aluminum oxide.
However, Nakatsuji teaches a semiconductor device (Figure 21) comprising a peripheral circuit region (#700, peripheral device region) and a memory cell region (#100, memory array region), wherein the peripheral circuit region comprises a first lower protective layer (#762, dielectric liner) disposed below a first peripheral region insulating layer which is on it (#764, dielectric material layer on #762), wherein a lower surface of the first lower protective layer is located at a same vertical level as an upper surface of a first substrate (#9, substrate semiconductor layer which has an upper surface at the same vertical level as a lower surface of #762) and circuit elements (#710, Figure 1, semiconductor devices) protrude into the first peripheral region insulating layer (Figures 1 and 21, the gate structures #750 of #710s protrude into #764).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the first lower protective layer from Nakatsuji between the first peripheral region insulating layer and the substrate and peripheral circuit devices in Lee since it “blocks diffusion of mobile ions and/or apply appropriate stress to underlying structures” according to Nakatsuji (see [0044] of Nakatsuji).
Lee in view of Nakatsuji does not disclose a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first lower protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a second material different from a first material of the first lower protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a hydrogen diffusion barrier layer configured to inhibit a hydrogen element each of in the first cell region insulating layer, the second cell region insulating layer, and the third cell region insulating layer from diffusing to the circuit elements, and
the hydrogen diffusion barrier layer comprises the second material, and
wherein the second material is aluminum oxide.
However, Lee does disclose that the first lower protective layer (#219), the second lower protective layer (#227), the third lower protective layer (#237), and the fourth lower protective layer (#249) comprise silicon nitride ([0127], “219, 227, 237, and 249 may be formed with a nitride-based insulating layer (e.g., a silicon nitride layer)”) and Nakatsuji teaches that the silicon nitride dielectric liner (#762) functions to prevent the diffusion of mobile ions ([0044]).
Yamazaki teaches in [0259] that “For the film having a barrier property against hydrogen, silicon nitride formed by a chemical vapor deposition (CVD) method can be used” (i.e. silicon nitride is a known barrier material which may inhibit hydrogen element diffusion) and further teaches a semiconductor memory device (Figure 14, memory device according to [0242]) comprising a memory core (#20) and a peripheral circuit structure (#40), and a plurality of protective layers (#510 and #514, insulators) which may have a barrier property against hydrogen diffusion ([0344], “insulator 510 and the insulator 514 are preferably formed using, for example, a film having a barrier property that prevents diffusion of hydrogen”) wherein the hydrogen diffusion barrier material comprises aluminum oxide ([0346], “For the film having a barrier property against hydrogen used for the insulator 510 and the insulator 514, for example, a metal oxide such as aluminum oxide . . . is preferably used”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming at least one, or any plurality such as the second and third, of the protective layers of Lee in view of Nakatsuji out of the hydrogen barrier material aluminum oxide, different from the silicon nitride hydrogen diffusion barrier, as taught by Yamazaki as substituting equivalents known for the same purpose of blocking the diffusion of hydrogen (see MPEP 2144.06.II) since “aluminum oxide has a high blocking effect that inhibits the passage of both oxygen and impurities such as hydrogen and moisture which are factors of a change in electrical characteristics of the transistor” (see [0347] of Yamazaki).
Lee in view of Nakatsuji and Yamazaki do not disclose that a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first lower protective layer and the fourth lower protective layer.
However, Yamazaki teaches that each of the second lower protective layer and the third lower protective layers being formed of aluminum oxide should have a thickness greater than or equal to 0.5 nm (5 Å) and less than or equal to 3.0 nm (30 Å) since “even a thin aluminum oxide film having a thickness can inhibit diffusion of hydrogen and nitrogen” (see [0412] of Yamazaki).
Nakatsuji teaches a semiconductor memory device (Figure 21) comprising a hydrogen diffusion blocking layer (#766, Figure 21, silicon nitride layer (e.g., hydrogen diffusion barrier)) vertically separating a lower peripheral circuit structure from an upper memory structure, wherein the silicon nitride hydrogen diffusion barrier has a thickness between 6 nm (60 Å) and 100 nm (1000 Å) ([0049], “the thickness of the silicon nitride layer 766 can be in a range from 6 nm to 100 nm”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the second and third protective layers, formed of aluminum oxide, of Lee in view of Nakatsuji and Yamazaki to have thickness (greater than or equal to 0.5 nm (5 Å) and less than or equal to 3.0 nm (30 Å)) smaller than the thickness of the first and fourth protective layers (between 6 nm (60 Å) and 100 nm (1000 Å)), formed of silicon nitride since “The thickness of the silicon nitride layer 766 is selected such that the silicon nitride layer 766 functions as a sufficiently robust hydrogen diffusion barrier” (see [0049] of Nakatsuji) and “even a thin aluminum oxide film having a thickness can inhibit diffusion of hydrogen and nitrogen” (see [0412] of Yamazaki).
Regarding Claim 15. Lee in view of Nakatsuji, and Yamazaki disclose The semiconductor device of claim 14, wherein each of the first lower protective layer (Nakatsuji, [0044], “dielectric liner 762 such as a silicon nitride”) and the fourth lower protective layer comprises silicon nitride (Lee, [0127], “237 . . . may be formed with a nitride-based insulating layer (e.g., a silicon nitride layer)”).
Regarding Claim 16. Lee in view of Nakatsuji, and Yamazaki disclose The semiconductor device of claim 14.
Lee in view of Nakatsuji, and Yamazaki do not explicitly disclose that each of the first lower protective layer and the fourth lower protective layer has a thickness in a range of 300 Å to 2000 Å, and
wherein each of the second lower protective layer and the third lower protective layer has a thickness in a range of 50 Å to 100 Å.
Yamazaki teaches in [0412] that “aluminum oxide has a high barrier property, and even a thin aluminum oxide film having a thickness greater than or equal to 0.5 nm (5 Å) and less than or equal to 3.0 nm (300 Å) can inhibit diffusion of hydrogen and nitrogen”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the second lower protective layer and the third protective layer of Lee in view of Nakatsuji, and Yamazaki, formed of aluminum oxide, to have a thickness in the range of 50 Å to 100 Å in view of the range of 0.5 nm (5 Å) and less than or equal to 3.0 nm (300 Å) taught by Yamazaki as sufficient for inhibition of hydrogen diffusion since the two ranges are overlapping (see MPEP 2144.05.I)
Lee in view of Nakatsuji, and Yamazaki do not explicitly disclose that each of the first lower protective layer and the fourth lower protective layer has a thickness in a range of 300 Å to 2000 Å.
Nakatsuji teaches a semiconductor memory device (Figure 21) comprising a hydrogen diffusion blocking layer (#766, Figure 21, silicon nitride layer (e.g., hydrogen diffusion barrier)) vertically separating a lower peripheral circuit structure from an upper memory structure, wherein the silicon nitride hydrogen diffusion barrier has a thickness between 6 nm (60 Å) and 100 nm (1000 Å) ([0049], “the thickness of the silicon nitride layer 766 can be in a range from 6 nm to 100 nm”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the first lower protective layer and the fourth lower protective layer of Lee in view of Nakatsuji, and Yamazaki, formed of silicon nitride, to have a thickness in the range of 300 Å to 2000 Å in view of the range of 6 nm (60 Å) and 100 nm (1000 Å) taught by Nakatsuji as sufficient for inhibition of hydrogen diffusion since the two ranges are overlapping (see MPEP 2144.05.I)
Regarding Claim 19. Lee discloses An electronic system (#600, Figure 25, electronic system) comprising:
a semiconductor device ([0246], “memory 612 may include the semiconductor device according to example embodiments of inventive concepts” such as #400, Figure 23, semiconductor module, [0237], “memory device 430 may include one of the above-described semiconductor devices formed according to example embodiments of inventive concepts” such as (Figures 7A and 7B, semiconductor device where Figure 8 is an enlarged view of Figure 7A according to [0033]-[0034])) comprising:
a first substrate (#2, Figure 7A, semiconductor substrate);
circuit elements (#PTR1’ and #PTR2’, Figures 7A and 7B, peripheral transistors) on the first substrate (Figures 7A and 7B, #PTR1’/2’ are disposed on #2);
a first peripheral region insulating layer (#LILD1’, Figure 7A, first lower interlayer insulating layer), wherein the circuit elements protrude into the first peripheral region insulating layer (Figures 7A and 8, the gate structures of #PTR1’/2’ protrude into #LILD1’);
a first lower interconnection structure (#218, Figure 8, lower interconnection structure) penetrating through the first peripheral region insulating layer (Figure 8, #218 penetrates through #LILD1’) the first lower interconnection structure comprising a first lower contact plug (#216C, Figure 8, lower contact plug) and a first lower interconnection line (#216L, Figure 8, lower interconnection line);
a second lower protective layer (#219, Figure 8, lower capping layer) disposed on the first peripheral region insulating layer (Figure 8, #219 is on #LILD1’);
a second peripheral region insulating layer (#LILD2’, Figure 7A, second lower interlayer insulating layer) disposed on the second lower protective layer (Figure 8, #LILD2’ is on #219);
a second lower interconnection structure (#226, Figure 8, first intermediate interconnection structure) penetrating through the second peripheral region insulating layer (Figure 8, #226 penetrates through #LILD2’), the second lower interconnection structure comprising a second lower contact plug (#224C, Figure 8, first intermediate contact plug) and a second lower interconnection line (#224L, Figure 8, first intermediate interconnection);
a third lower protective layer (#227, Figure 8, first intermediate capping layer) disposed on the second peripheral region insulating layer (Figure 8, #227 is on #LILD2’);
a third peripheral region insulating layer (#LILD3’, Figure 7A, third lower interlayer insulating layer) disposed on the third lower protective layer (Figure 7A, #LILD3’ is on #227);
a third lower interconnection structure (#234, Figure 8, second intermediate interconnection structure) penetrating through the third peripheral region insulating layer (Figure 8, #234 penetrates through #LILD3’), the third lower interconnection structure comprising a third lower contact plug (#232C, Figure 8, second intermediate contact plug) and a third lower interconnection line (#232L, Figure 8, second intermediate interconnection);
a fourth lower protective layer (#237, Figure 8, second intermediate capping layer) disposed on the third peripheral region insulating layer (Figure 8, #237 is on #LILD3’);
a fourth peripheral region insulating layer (#LILD4’, Figure 7A, fourth lower interlayer insulating layer) disposed on the fourth lower protective layer (Figure 7A, #LILD4’ is on #237);
a memory structure (#MC, Figure 7A annotated) disposed on the fourth peripheral region insulating layer (Figure 7A annotated, #MC is on #LILD4’), the memory structure comprising gate electrodes (#CGs, Figure 7A annotated, cell gates) and channel structures (#CV, Figure 7A annotated, [0085], “three-dimensional memory array may include . . . a plurality of cell vertical structures CV”) passing through the gate electrodes (Figure 7A, #CVs pass through #CGs);
a first cell region insulating layer (#UILD1, Figure 20A of the method of making the device and part of #UILD in Figure 7A, first upper interlayer insulating layer) disposed on the fourth peripheral region insulating layer (Figure 20A, #UILD1 is on #LILD4’) and covering the memory structure (Figure 120A, #UILD1 covers the memory structure); and
a first upper protective layer (#UILD2, Figure 20A and part of #UILD in Figure 7A, second upper interlayer insulating layer), a second cell region insulating layer (#UILD3, Figure 20A and part of #UILD in Figure 7A, third upper interlayer insulating layer), a second upper protective layer (#UILD4, Figure 20A and part of #UILD in Figure 7A, fourth upper interlayer insulating layer), and a third cell region insulating layer (#UILD5, Figure 20A and part of #UILD in Figure 7A, fifth upper interlayer insulating layer) sequentially stacked on the first cell region insulating layer (Figure 20A, #UILD2-5 are sequentially stacked on #UILD1),
input/output pads (#440, Figure 23, Input/output terminals) electrically connected to the circuit elements (Figure 23, #440s are necessarily electrically connected to the circuit elements as they are electrically connected to the memory device),
wherein a thickness of the third lower interconnection line (horizontal width of #232L, Figure 8) is greater than a thickness of each of the first lower interconnection line (horizontal width of #216L, Figure 8) and the second lower interconnection line (horizontal width of #224L, Figure 8) (Figure 8, the horizontal width of #232L is greater than the horizontal width of #224L and #216L),
wherein a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first upper protective layer and the second upper protective layer (Figure 20A, the thickness of #219 and #227 are each less than a thickness of #UILD2 and #UILD4), and
a controller (#614, Figure 25, microprocessor) electrically connected to the semiconductor device through the input/output pads and configured to control the semiconductor device ([0246], “microprocessor 614 may program and control the electronic system 600”, i.e. the microprocessor is necessarily connected to the semiconductor device through its only input/output pads #440, Figure 23).
Lee does not disclose a first lower protective layer covering the circuit elements, wherein the first peripheral region insulating layer is disposed on the first lower protective layer, and a lower surface of the first lower protective layer is located at a same vertical level as an upper surface of the first substrate,
a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first lower protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a second material different from a first material of the first upper protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a hydrogen diffusion barrier layer comprising the second material and configured to inhibit a hydrogen element in each of the first cell region insulating layer, the second cell region insulating layer, and the third cell region insulating layer from diffusing to the circuit elements.
However, Nakatsuji teaches a semiconductor device (Figure 21) comprising a peripheral circuit region (#700, peripheral device region) and a memory cell region (#100, memory array region), wherein the peripheral circuit region comprises a first lower protective layer (#762, dielectric liner) disposed below a first peripheral region insulating layer which is on it (#764, dielectric material layer on #762), wherein a lower surface of the first lower protective layer is located at a same vertical level as an upper surface of a first substrate (#9, substrate semiconductor layer which has an upper surface at the same vertical level as a lower surface of #762) and circuit elements (#710, Figure 1, semiconductor devices) protrude into the first peripheral region insulating layer (Figures 1 and 21, the gate structures #750 of #710s protrude into #764).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider providing the first lower protective layer from Nakatsuji between the first peripheral region insulating layer and the substrate and peripheral circuit devices in Lee since it “blocks diffusion of mobile ions and/or apply appropriate stress to underlying structures” according to Nakatsuji (see [0044] of Nakatsuji).
Lee in view of Nakatsuji does not disclose a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first lower protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a second material different from a first material of the first lower protective layer and the fourth lower protective layer,
wherein each of the second lower protective layer and the third lower protective layer comprises a hydrogen diffusion barrier layer configured to inhibit a hydrogen element each of in the first cell region insulating layer, the second cell region insulating layer, and the third cell region insulating layer from diffusing to the circuit elements.
However, Lee does disclose that the first lower protective layer (#219), the second lower protective layer (#227), the third lower protective layer (#237), and the fourth lower protective layer (#249) comprise silicon nitride ([0127], “219, 227, 237, and 249 may be formed with a nitride-based insulating layer (e.g., a silicon nitride layer)”) and Nakatsuji teaches that the silicon nitride dielectric liner (#762) functions to prevent the diffusion of mobile ions ([0044]).
Yamazaki teaches in [0259] that “For the film having a barrier property against hydrogen, silicon nitride formed by a chemical vapor deposition (CVD) method can be used” (i.e. silicon nitride is a known barrier material which may inhibit hydrogen element diffusion) and further teaches a semiconductor memory device (Figure 14, memory device according to [0242]) comprising a memory core (#20) and a peripheral circuit structure (#40), and a plurality of protective layers (#510 and #514, insulators) which may have a barrier property against hydrogen diffusion ([0344], “insulator 510 and the insulator 514 are preferably formed using, for example, a film having a barrier property that prevents diffusion of hydrogen”) wherein the hydrogen diffusion barrier material comprises aluminum oxide ([0346], “For the film having a barrier property against hydrogen used for the insulator 510 and the insulator 514, for example, a metal oxide such as aluminum oxide . . . is preferably used”).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming at least one, or any plurality such as the second and third, of the protective layers of Lee in view of Nakatsuji out of the hydrogen barrier material aluminum oxide, different from the silicon nitride hydrogen diffusion barrier, as taught by Yamazaki as substituting equivalents known for the same purpose of blocking the diffusion of hydrogen (see MPEP 2144.06.II) since “aluminum oxide has a high blocking effect that inhibits the passage of both oxygen and impurities such as hydrogen and moisture which are factors of a change in electrical characteristics of the transistor” (see [0347] of Yamazaki).
Lee in view of Nakatsuji and Yamazaki do not disclose that a thickness of each of the second lower protective layer and the third lower protective layer is less than a thickness of each of the first lower protective layer and the fourth lower protective layer.
However, Yamazaki teaches that each of the second lower protective layer and the third lower protective layers being formed of aluminum oxide should have a thickness greater than or equal to 0.5 nm (5 Å) and less than or equal to 3.0 nm (30 Å) since “even a thin aluminum oxide film having a thickness can inhibit diffusion of hydrogen and nitrogen” (see [0412] of Yamazaki).
Nakatsuji teaches a semiconductor memory device (Figure 21) comprising a hydrogen diffusion blocking layer (#766, Figure 21, silicon nitride layer (e.g., hydrogen diffusion barrier)) vertically separating a lower peripheral circuit structure from an upper memory structure, wherein the silicon nitride hydrogen diffusion barrier has a thickness between 6 nm (60 Å) and 100 nm (1000 Å) ([0049], “the thickness of the silicon nitride layer 766 can be in a range from 6 nm to 100 nm”.
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the second and third protective layers, formed of aluminum oxide, of Lee in view of Nakatsuji and Yamazaki to have thickness (greater than or equal to 0.5 nm (5 Å) and less than or equal to 3.0 nm (30 Å)) smaller than the thickness of the first and fourth protective layers (between 6 nm (60 Å) and 100 nm (1000 Å)), formed of silicon nitride since “The thickness of the silicon nitride layer 766 is selected such that the silicon nitride layer 766 functions as a sufficiently robust hydrogen diffusion barrier” (see [0049] of Nakatsuji) and “even a thin aluminum oxide film having a thickness can inhibit diffusion of hydrogen and nitrogen” (see [0412] of Yamazaki).
Regarding Claim 20. Lee in view of Nakatsuji, and Yamazaki discloses The electronic system of claim 19, wherein each of the first lower protective layer (Nakatsuji, [0044], “dielectric liner 762 such as a silicon nitride”) and fourth lower protective layer comprises silicon nitride (Lee, [0127], “237 . . . may be formed with a nitride-based insulating layer (e.g., a silicon nitride layer)”).
Claim(s) 11 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0122695 A1; Lee et al.; 05/2018; (“Lee”) in view of US 20190006381 A1; Nakatsuji et al.; 01/2019; (“Nakatsuji”) and US 2022/0375529 A1; Yamazaki et al.; 11/2022; (“Yamazaki”), as applied to claim(s) 3 and 14 above, and further in view of US 2014/0110795 A1; Oh et al.; 04/2014; (“Oh”).
Regarding Claim 11. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 3, wherein the memory cell region (Lee, #MC, Figure 7A annotated) further comprises a through via (Lee, #280a, Figure 7A annotated, first peripheral bit line contact structure) passing through the fourth peripheral region insulating layer (Lee, Figure 7A, #280a passes through #LILD5’) to electrically connect the first interconnection structure and the second interconnection structure (Lee, Figure 7A, #280a electrically connects #248 of the first interconnection structure to #282a of the second interconnection structure), and
wherein the through via passes through the fourth lower protective layer (Lee, Figure 7A, #280a passes through #249).
Lee in view of Nakatsuji and Yamazaki do not disclose that the through via passes through the gate electrodes. Instead the via (#280a) of Lee is formed through the cell region insulating layer (#UILD) adjacent to the gate electrodes (#CGs) in the memory structure.
However, Oh teaches a semiconductor memory structure (Figures 6A and 6B) wherein a via (#GP1, Figure 6B, first contact plug group) is formed through gate electrodes (#241A to #241D, Figure 6B, conductive lines) of a memory structure to connect to transistors in an underlying peripheral circuit structure on a lower substrate (#201).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the via of Lee in view of Nakatsuji and Yamazaki passing through the gate electrodes of the memory structure as in Oh in order to reduce an area required for the peripheral circuit structure and corresponding interconnections and further simplify the device layout (see [0008], [0011], and [0073] of Oh).
Regarding Claim 17. Lee in view of Nakatsuji and Yamazaki discloses The semiconductor device of claim 14, wherein the semiconductor device further comprises a through via (Lee, #280a, Figure 7A annotated, first peripheral bit line contact structure) passing the fourth peripheral region insulating layer (Lee, Figure 7A, #280a passes through #LILD5’), and
wherein the through via passes through the fourth lower protective layer (Lee, Figure 7A, #280a passes through #249).
Lee in view of Nakatsuji and Yamazaki do not disclose that the through via passes through the gate electrodes. Instead the via (#280a) of Lee is formed through the cell region insulating layer (#UILD) adjacent to the gate electrodes (#CGs)in the memory structure.
However, Oh teaches a semiconductor memory structure (Figures 6A and 6B) wherein a via (#GP1, Figure 6B, first contact plug group) is formed through gate electrodes (#241A to #241D, Figure 6B, conductive lines) of a memory structure to connect to transistors in an underlying peripheral circuit structure on a lower substrate (#201).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to consider forming the via of Lee in view of Nakatsuji and Yamazaki passing through the gate electrodes of the memory structure as in Oh in order to reduce an area required for the peripheral circuit structure and corresponding interconnections and further simplify the device layout (see [0008], [0011], and [0073] of Oh).
Regarding Claim 18. Lee in view of Nakatsuji, Yamazaki, and Oh disclose The semiconductor device of claim 17, wherein the semiconductor device further comprises an upper via (Lee, #242, #246, and #280a, Figures 7A annotated and 8, upper contact plug, upper interconnection, and bit line contact structure) penetrating through the fourth peripheral region insulating layer (Lee, Figures 7A and 8, #242 passes through #LILD4’), and
wherein the upper via passes through the fourth lower protective layer (Lee, Figures 7A and 8, #242 passes through #237).
Response to Arguments/Amendments
Applicant’s amendments to claims 1, 14, and 19 and corresponding arguments, see pages 14-16 of the remarks, filed 02/26/2026, with regard to the 35 U.S.C. 103 rejections of claims 1, 14, and 19, and all of their dependent claims have been fully considered. The previous 35 U.S.C. 103 rejections of claims 1, 14, and 19 have been withdrawn as the previously considered prior art does not appear to disclose all of the limitations of the amended claims. However, upon further search and consideration, a reference (US 20190006381 A1; Nakatsuji et al.; 01/2019; (“Nakatsuji”)) was identified which teaches the amended limitation to claims 1, 14, and 19 and provides motivation to combine. Nakatsuji teaches a peripheral region of a three-dimensional memory device (Figure 21) comprising a first lower protective layer (#762, Figure 21, [0044], silicon nitride dielectric liner), wherein a lower surface of the first lower protective layer is located at the same vertical level as an upper surface of the first substrate (Figure 121, a lower surface of #762 is located at the same vertical level as an upper surface of #9) and gate electrodes of the peripheral circuit elements (#750, Figure 21, gate structures) protrude into the overlying first peripheral region insulating layer (#764) by protruding upwards and pushing the first protective layer into the first peripheral region insulating layer in the same manner as shown in Figures 1A and 1B of the instant application. Providing the first lower protective layer from Nakatsuji between the first peripheral region insulating layer and the substrate and peripheral circuit devices in Lee would have been obvious since it “blocks diffusion of mobile ions and/or apply appropriate stress to underlying structures” according to Nakatsuji (see [0044] of Nakatsuji).
Claim(s) 1-3, 6, 8, 12-16, and 19-20 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0122695 A1; Lee et al.; 05/2018; (“Lee”) in view of US 20190006381 A1; Nakatsuji et al.; 01/2019; (“Nakatsuji”) and US 2022/0375529 A1; Yamazaki et al.; 11/2022; (“Yamazaki”).
Claim(s) 11 and 17-18 stand rejected under 35 U.S.C. 103 as being unpatentable over US 2018/0122695 A1; Lee et al.; 05/2018; (“Lee”) in view of US 20190006381 A1; Nakatsuji et al.; 01/2019; (“Nakatsuji”) and US 2022/0375529 A1; Yamazaki et al.; 11/2022; (“Yamazaki”), as applied to claim(s) 3 and 14 above, and further in view of US 2014/0110795 A1; Oh et al.; 04/2014; (“Oh”).
Conclusion
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/TYLER J WIEGAND/Examiner, Art Unit 2812
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