Office Action Predictor
Application No. 18/133,291

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES

Non-Final OA §103
Filed
Apr 11, 2023
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Amkor Technology Singapore Holding Pte. LTD.
OA Round
5 (Non-Final)
86%
Grant Probability
Favorable
5-6
OA Rounds
2y 7m
To Grant
43%
With Interview

Examiner Intelligence

86%
Career Allow Rate
809 granted / 946 resolved
Without
With
+-42.3%
Interview Lift
avg trend
2y 7m
Avg Prosecution
59 pending
1005
Total Applications
career history

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
49.5%
+9.5% vs TC avg
§102
44.7%
+4.7% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/12/25 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2-10 and 12-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liao (US PGPub 2011/0006408, hereinafter referred to as “Liao”) in view of Kuan et al. (US Patent 10,879,192, hereinafter to referred to as “Kuan”). Liao discloses the semiconductor method substantially as claimed. See figures 1A-5 and corresponding text, where Liao teaches, in claim 2, a method of making a semiconductor device, comprising: (figures 1A-1G; [0023-0031]) providing a first component module (10) (left) comprising a first electronic component (120) and a first module encapsulant (130) disposed around the first electronic component (120); providing a second component module (10) (right) comprising a second electronic component (120) and a second module encapsulant (130) disposed around the second electronic component (120); providing a vertical interconnect (108) laterally offset from the first component module (10) (left), wherein the vertical interconnect (108) comprises an electrically conductive material to provide an electrical coupling to an external component; wherein the first component module (10) (left), the second component module (10) (right), and the vertical interconnect (108) are coupled to the main conductive structure (102); wherein the vertical interconnect (108) is external to the first module encapsulant (130) and the second module encapsulant (130). wherein a first portion is between the first component module (10) (left) and the vertical interconnect (108), and the vertical interconnect (108) is between a second portion and the first portion. (figures 1A-1G; [0023-0031]) However, Liao fails to explicitly show, in claim 2, providing a main encapsulant between the first component module and the second component module; and providing a main substrate comprising a main conductive structure; wherein the first component module, the second component module, the vertical interconnect, and the main encapsulant are disposed over a top side of the main substrate; and is surrounded by the main encapsulant; wherein a first portion of the main encapsulant is between the first component module and the vertical interconnect, and the vertical interconnect is between a second portion of the main encapsulant and the first portion of the main encapsulant. Kuan teaches, in claim 2, providing a main encapsulant (110) between the first component module and the second component module; and providing a main substrate (140) comprising a main conductive structure; wherein the first component module, the second component module, and the main encapsulant (DF1, DF2) are disposed over a top side of the main substrate (140), and wherein in the first component module and the second module, are coupled to the main conductive structure; (figure 9; col. 11, lines 40-60; col. 12, lines 1-28) wherein the main encapsulant contacts the top side of the main substrate (140); wherein a first portion of the main encapsulant is between the first component module is between a second portion of the main encapsulant and the first portion of the main encapsulant (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). In addition, Kuan provides the advantages of having a wall structures to isolate the semiconductor devices to protect against electromagnetic interference (col. 7, lines 25-50). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to incorporate providing a main encapsulant between the first component module and the second component module; and providing a main substrate comprising a main conductive structure; wherein the first component module, the second component module, the vertical interconnect, and the main encapsulant are disposed over a top side of the main substrate; and is surrounded by the main encapsulant; wherein a first portion of the main encapsulant is between the first component module and the vertical interconnect, and the vertical interconnect is between a second portion of the main encapsulant and the first portion of the main encapsulant, in the method of Liao, according to the teachings of Kuan, with the motivation of providing isolation of the semiconductor devices to protect against electromagnetic interferences. Liao in view of Kuan shows, in claim 3, comprising: providing a module interconnect coupled to the first component module; and coupling the module interconnect to the main conductive structure; wherein the main encapsulant covers the module interconnect (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 4, wherein: one end of the vertical interconnect is exposed external to the main encapsulant (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 5, wherein: a top side of the first component module is exposed from the main encapsulant (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 6, wherein: the main encapsulant covers a top side of the first component module. Liao in view of Kuan shows, in claim 7, wherein: the main substrate is provided after the main encapsulant is provided; and the main encapsulant extends underneath the first component module between a top side of the main substrate and a bottom side of the of the first component module (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 8, wherein: the main substrate is provided before the main encapsulant is provided (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao shows, in claim 9 a method, comprising: (figures 1A-1G; [0023-0031]) providing a first component module (100 comprising a first electronic component (120) and a first module encapsulant (130) disposed around the first electronic component (120); disposing a shield (140) over the first module encapsulant (10); providing a second component module (10) comprising a second electronic component (120) and a second module encapsulant (130) disposed around the second electronic component (120); and providing a main substrate comprising a main conductive structure; wherein the first component module and the second component module are over a top side of the main substrate and coupled to the main conductive structure; wherein a vertical side of the shield is between the first module encapsulant and the main encapsulant; wherein a top side of the shield is exposed from covered by the main encapsulant, and the vertical side of the shield is covered by the main encapsulant. However, Liao fails to explicitly show, in claim 9, providing a main substrate comprising a main conductive structure; wherein the first component module and the second component module are over a top side of the main substrate and coupled to the main conductive structure; wherein a vertical side of the shield is between the first module encapsulant and the main encapsulant; wherein a top side of the shield is exposed from covered by the main encapsulant, and the vertical side of the shield is covered by the main encapsulant. Kuan teaches, in claim 9, providing a main encapsulant (110) between the first component module and the second component module; and providing a main substrate (140) comprising a main conductive structure; wherein the first component module, the second component module, and the main encapsulant (DF1, DF2) are disposed over a top side of the main substrate (140), and wherein in the first component module and the second module, are coupled to the main conductive structure; (figure 9; col. 11, lines 40-60; col. 12, lines 1-28) wherein the main encapsulant contacts the top side of the main substrate (140); wherein a first portion of the main encapsulant is between the first component module is between a second portion of the main encapsulant and the first portion of the main encapsulant (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). In addition, Kuan provides the advantages of having a wall structures to isolate the semiconductor devices to protect against electromagnetic interference (col. 7, lines 25-50). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to incorporate providing a main substrate comprising a main conductive structure; wherein the first component module and the second component module are over a top side of the main substrate and coupled to the main conductive structure; wherein a vertical side of the shield is between the first module encapsulant and the main encapsulant; wherein a top side of the shield is exposed from covered by the main encapsulant, and the vertical side of the shield is covered by the main encapsulant, in the method of Liao, according to the teachings of Kuan, with the motivation of providing isolation of the semiconductor devices to protect against electromagnetic interferences. Liao in view of Kuan shows, in claim 10, comprising: providing a module interconnect coupled to the first component module; and coupling module interconnect to the main conductive structure; wherein the main encapsulant covers the module interconnect (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 12, wherein: the main encapsulant covers a top side of the first second component module (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 13, wherein: the main substrate is provided after the main encapsulant is provided (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 14, wherein: the main substrate is provided before the main encapsulant is provided. Liao shows, in claim 15, a method, comprising: (figures 1A-1G; [0023-0031]) providing a first component module (10) comprising: a first electronic component (120), a first module encapsulant (130) disposed around the first electronic component (1200, and a shield (140) disposed over the first module encapsulant (130); providing a first component interconnect (106) coupled to the first component module (10); providing a vertical interconnect (108) laterally offset from the first component module (10), wherein the vertical interconnect comprises an electrically conductive material to provide an electrical coupling to an external component; However, Liao fails to explicitly show, in claim 15, disposing a main encapsulant around the first component module and the vertical interconnect; and providing a main substrate comprising a main conductive structure; wherein the first component module, the vertical interconnect, and the main encapsulant are over a top side of the main substrate; and wherein the first component module and the vertical interconnect are coupled to the main conductive structure; wherein the vertical interconnect is external to the first module encapsulant and external to the shield; wherein the shield is between the first module encapsulant and the main encapsulant; and wherein the main encapsulant is external to the shield and extends between a vertical side of the shield and the vertical interconnect. Kuan teaches, in claim 15, providing a main encapsulant (110) between the first component module and the second component module; and providing a main substrate (140) comprising a main conductive structure; wherein the first component module, the second component module, and the main encapsulant (DF1, DF2) are disposed over a top side of the main substrate (140), and wherein in the first component module and the second module, are coupled to the main conductive structure; (figure 9; col. 11, lines 40-60; col. 12, lines 1-28) wherein the main encapsulant contacts the top side of the main substrate (140); wherein a first portion of the main encapsulant is between the first component module is between a second portion of the main encapsulant and the first portion of the main encapsulant (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). In addition, Kuan provides the advantages of having a wall structures to isolate the semiconductor devices to protect against electromagnetic interference (col. 7, lines 25-50). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filling date of the claimed invention, to incorporate disposing a main encapsulant around the first component module and the vertical interconnect; and providing a main substrate comprising a main conductive structure; wherein the first component module, the vertical interconnect, and the main encapsulant are over a top side of the main substrate; and wherein the first component module and the vertical interconnect are coupled to the main conductive structure; wherein the vertical interconnect is external to the first module encapsulant and external to the shield; wherein the shield is between the first module encapsulant and the main encapsulant; and wherein the main encapsulant is external to the shield and extends between a vertical side of the shield and the vertical interconnect, in the method of Liao, according to the teachings of Kuan, with the motivation of providing isolation of the semiconductor devices to protect against electromagnetic interferences. Liao in view of Kuan shows, in claim 16, comprising: coupling the first component interconnect to the main conductive structure; wherein the main encapsulant extends between the first component module and the top side of the main substrate (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 17, wherein: one end of the vertical interconnect is exposed external to the main encapsulant (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 18, wherein: a top side of the first component module is exposed from the main encapsulant (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 19, wherein: the main encapsulant covers a top side of the first component module (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 20, wherein: the main substrate is provided after the main encapsulant is provided (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Liao in view of Kuan shows, in claim 21, wherein: the main substrate is provided before the main encapsulant is provided (figure 9; col. 11, lines 40-60; col. 12, lines 1-28). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 11-8. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/ Examiner, Art Unit 2898 December 27, 2025
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Prosecution Timeline

Apr 11, 2023
Application Filed
Nov 08, 2023
Response after Non-Final Action
Dec 02, 2023
Non-Final Rejection — §103
Feb 22, 2024
Response Filed
Jun 12, 2024
Final Rejection — §103
Aug 15, 2024
Response after Non-Final Action
Aug 15, 2024
Examiner Interview (Telephonic)
Aug 22, 2024
Response after Non-Final Action
Aug 30, 2024
Request for Continued Examination
Sep 03, 2024
Response after Non-Final Action
Oct 19, 2024
Non-Final Rejection — §103
Jan 23, 2025
Response Filed
May 07, 2025
Final Rejection — §103
Jul 21, 2025
Interview Requested
Jul 30, 2025
Examiner Interview Summary
Jul 30, 2025
Examiner Interview (Telephonic)
Aug 12, 2025
Request for Continued Examination
Aug 15, 2025
Response after Non-Final Action
Dec 27, 2025
Non-Final Rejection — §103
Mar 30, 2026
Response Filed

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Prosecution Projections

5-6
Expected OA Rounds
86%
Grant Probability
43%
With Interview (-42.3%)
2y 7m
Median Time to Grant
High
PTA Risk
Based on 946 resolved cases by this examiner