DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The replacement drawings received on 4/14/2026 are accepted.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-7, 9-11, 15-18 and 21-22 are rejected under 35 U.S.C. 1023 as being unpatentable over Peng et al. (PG Pub. No. US 2022/0123023 A1) in view of Peng et al. (PG Pub. No. US 2022/0122971 A1, hereinafter referenced as ‘Peng-971’).
Regarding claim 1, Peng teaches a cell architecture (figs. 2A-2D) comprising at least one semiconductor device cell (¶ 0054: 200A) which comprises:
a 1st active pattern (¶ 0049: 122 and/or 126) and a 2nd active pattern (¶ 0045: 112 and/or 116) extended in a 1st direction (fig. 2A: 122/126 and 112/116 extend in 1st horizontal direction), the 1st active pattern at least partially overlapping the 2nd active pattern in a 3rd direction intersecting the 1st direction (fig. 2D: 122/126 at least partially overlaps 112/116 in a vertical direction);
a plurality of gate structures (¶¶ 0045, 0053: plurality of 130 arranged in parallel) extended in a 2nd direction across the 1st and 2nd active patterns (figs. 2A-2C: 130 extends across 122/126 and 112/116 in a 2nd horizontal direction), the 2nd direction intersecting the 1st direction and the 3rd direction (fig. 2A: 130 extend in 2nd horizontal direction intersecting 1st horizontal direction and vertical direction);
a plurality of metal lines (¶¶ 0056, 0058: 132/134 and/or 142/144) in at least one metal layer of the at least one semiconductor device cell (¶ 0055: 132/134 and/or 142/144 comprised by metal layers L1 or L4), the metal lines being extended in the 1st direction (fig. 2A among others: 134/144 extend in 1st horizontal direction), and at least one of the metal lines being connected to at least one of the 1st and 2nd active patterns and the gate structures (¶ 0059 & fig. 2D among others: at least one 144 electrically connected to 112 or 122 through respective vias 162 or 166, at least one 144 electrically connected to 130 through via 152); and
at least one power rail (¶¶ 0056-0057: 132 and/or 142) connecting the at least one of the 1st and 2nd active patterns to at least one voltage source (¶¶ 0056-0057 & fig. 2D: 132/142 connect at least one of 122/112 to VSS or VDD),
wherein the at least one power rail is disposed to be closer to a virtual horizontal center line of the at least one semiconductor device cell extended in the 1st direction than an upper boundary or a lower boundary of the at least one semiconductor device cell (fig. 2B: 132/142 positioned closer to center of 200A than upper or lower boundary defined by CB).
Peng does not teach wherein at least one of the metal lines and the at least one power rail have a same width in the 2nd direction.
Peng-971 teaches a cell architecture comprising a semiconductor device cell (fig. 2A) including at least one metal line (¶¶ 0038-0039: 134a/134b, or 144a/144b) and at least one power rail (¶ 0040: 132/142) having a same width in a 2nd direction (¶ 0061: width ratio of 132 and 134 is about one in the x-axis direction).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the power rail and metal lines of Peng with the widths of Peng-971, as a means to minimize electrical resistance of the metal lines and/or power rails.
Furthermore, such a modification would have involved a mere change in the size of a component (e.g. increasing width(s) of metal line(s) 134/144). A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 2, Peng in view of Peng-971 teaches the cell architecture of claim 1, wherein the at least one power rail does not overlap the upper boundary or the lower boundary of the at least one semiconductor device cell in the 3rd direction (Peng, figs. 2A-2B: 132/142 does not overlap upper or lower segments of boundary CB).
Regarding claim 3, Peng in view of Peng-971 teaches the cell architecture of claim 2, wherein the at least one power rail is at least one metal line among the metal lines and is included in a back-end-of-line (BEOL) of the at least one semiconductor device cell (Peng, ¶ 0058: at least 132 among metal lines 132/134 comprised by a backside interconnect structure).
Regarding claim 4, Peng in view of Peng-971 teaches the cell architecture of claim 3, further comprising a gate contact plug (Peng, ¶ 0059: 152) on at least one of the gate structures (Peng, fig. 2D: 152 at least indirectly disposed on 130), wherein the gate contact plug does not overlap at least one of the 1st and 2nd active patterns in the 3rd direction (Peng, fig. 2D: 152 formed on 130 and not vertically overlapping 112 or 122).
Regarding claim 5, Peng in view of Peng-971 teaches the cell architecture of claim 4, wherein the at least one gate contact plug does not overlap either of the 1st and 2nd active patterns in the 3rd direction (Peng, fig. 2D: 152 does not vertically overlap either 112 or 122).
Regarding claim 6, Peng in view of Peng-971 teaches the cell architecture of claim 3, wherein the at least one metal line is disposed vertically above at least one of the 1st and 2nd active patterns in the 3rd direction (Peng, fig. 2A: at least one 144 disposed in layer L4, which is vertically above levels L2 and L3 comprising 112 and 122).
Regarding claim 7, Peng in view of Peng-971 teaches the cell architecture of claim 6, further comprising a gate contact plug (Peng, ¶ 0059: 152) on at least one of the gate structures (Peng, fig. 2D: 152 at least indirectly disposed on 130), wherein the gate contact plug does not overlap at least one of the 1st and 2nd active patterns (Peng, fig. 2D: 152 does not vertically overlap 112 or 122).
Regarding claim 9, Peng in view of Peng-971 teaches the cell architecture of claim 8, further comprising at least one gate contact plug (Peng, ¶ 0059: 152) on at least one of the gate structures (Peng, fig. 2D: 152 at least indirectly disposed on 130) wherein the at least one power rail does not overlap the upper boundary or the lower boundary of the at least one semiconductor device cell in the 3rd direction (Peng, figs. 2A-2D: 132/142 does not vertically overlap upper and lower segments of cell boundary CB), and
wherein the gate contact plug does not overlap at least one of the 1st and 2nd active patterns (Peng, fig. 2B: fig. 2D: 152 does not vertically overlap active pattern portions 112 or 122).
Regarding claim 10, Peng in view of Peng-971 teaches the cell architecture of claim 1, wherein the at least one power rail comprises two power rails respectively connected to a positive voltage source and a ground voltage source (Peng, ¶ 0062: 132/142 provide connections to VSS and VDD).
Regarding claim 11, Peng in view of Peng-971 teaches the cell architecture of claim 10, wherein the two power rails do not vertically overlap the upper boundary or the lower boundary of the at least one semiconductor device cell in the 3rd direction (Peng, figs. 2B-2C: 132/142 do not vertically overlap upper or lower segments of cell boundary CB).
Regarding claim 15, Peng in view of Peng-971 teaches the semiconductor device cell of claim 1, wherein the at least one power rail is at least one metal line among the metal lines (Peng, ¶¶ 0056-0057: 132/142 are power rails), included in a lowest metal layer of the at least one metal layer on the at least one semiconductor device cell (Peng figs. 2A-2D: 132 is a portion of lowest metal layer L1, and at disposed on a bottom of the semiconductor device cell bounded by CB).
Regarding claim 16, Peng teaches a cell architecture (figs. 2A-2D) comprising at least one semiconductor device cell (¶ 0054: 200A) which comprises:
a 1st active pattern (¶ 0049: 122 and/or 126) and a 2nd active pattern (¶ 0045: 112 and/or 116) extended in a 1st direction (fig. 2A: 122/126 and 112/116 extend in 1st horizontal direction), the 1st active pattern stacked on the 2nd active pattern in a direction intersecting the 1st direction (fig. 2D: 122/126 stacked on 112/116 in a vertical direction);
a plurality of gate structures (¶¶ 0045, 0053: plurality of 130 arranged in parallel) extended in a 2nd direction across the 1st and 2nd active patterns (figs. 2A-2C: 130 extends across 122/126 and 112/116 in a 2nd horizontal direction), the 2nd direction intersecting the 1st direction and the 3rd direction (fig. 2A: 130 extend in 2nd horizontal direction intersecting 1st horizontal direction and vertical direction); and
a plurality of metal lines (¶¶ 0056, 0058: 132/134 and/or 142/144) in at least one metal layer of the at least one semiconductor device cell (¶ 0055: 132/134 and/or 142/144 comprised by metal layers L1 or L4), the metal lines being extended in the 1st direction (fig. 2A among others: 134/144 extend in 1st horizontal direction),
wherein at least one of the metal lines is a power rail (¶¶ 0056-0057: 132 and/or 142 comprise rails to provide VSS and/or VDD) connecting at least one of the 1st and 2nd active patterns to at least one voltage source (fig. 2D: at least one of 116/126 connected to VSS/VDD), and
wherein another at least one of the metal lines is connected to at least one of the 1st and 2nd active patterns and the gate structures (¶ 0059 & fig. 2D among others: at least one 144 electrically connected to 112 or 122 through respective vias 162 or 166, at least one 144 electrically connected to 130 through via 152).
Peng does not teach wherein each of the metal lines has a same width in the 2nd direction.
Peng-971 teaches a cell architecture comprising a semiconductor device cell (fig. 2A) including at least one metal line (¶ 0040: power rail 132 or 142) connecting at least one of 1st and 2nd active patterns to at least one voltage source (figs. 2A-2E: 132/142 electrically connect active patterns 196 to VSS and/or VDD) and another at least one of the metal lines (¶¶ 0038-0039: 134a, 134b, 144a, or 144b) is connected to at least one of the 1st and 2nd active patterns and the gate structures (figs. 2A-2E: 134a, 134b, 144a, or 144b electrically connected to at least one 196 and 130),
wherein each of the at least one metal line and the another at least one metal line has a same width in a 2nd direction (¶ 0061 & fig. 2A: width ratio of 132 and 134 is about one in the x-axis direction).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the metal lines of Peng with the widths of Peng-971, as a means to minimize electrical resistance of the metal lines and/or power rails.
Furthermore, such a modification would have involved a mere change in the size of a component (e.g. increasing width(s) of metal line(s) 134 and/or 144). A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 17, Peng in view of Peng-971 teaches the cell architecture of claim 16, wherein the at least one of the metal lines is disposed at a position inside the at least one semiconductor device cell where the at least one of the metal lines does not overlap an upper boundary and a lower boundary of the at least one semiconductor device cell in the 3rd direction (Peng, figs. 2B, 2C: 132/142 located inside 200A and does not vertically overlap upper and lower segments of cell boundary CB).
Regarding claim 18, Peng in view of Peng-971 teaches the cell architecture of claim 17, wherein the at least one of the metal lines is disposed at the position that is closer to a virtual horizontal center line of the at least one semiconductor device cell extended in the 1st direction than the upper boundary or the lower boundary of the at least one semiconductor device cell (Peng, figs. 2B, 2C: 132/142 disposed at the position that is closer to a virtual horizontal center line of 200A extended in the 1st horizontal direction than the upper and lower segments of cell boundary CB).
Regarding claim 21, Peng teaches a cell architecture (figs. 2A-2D) comprising at least one semiconductor device cell (¶ 0054: 200A) which comprises:
a 1st active pattern (¶ 0049: 122 and/or 126) and a 2nd active pattern (¶ 0045: 112 and/or 116) extended in a 1st direction (fig. 2A: 122/126 and 112/116 extend in 1st horizontal direction), the 1st active pattern at least partially overlapping the 2nd active pattern in a direction intersecting the 1st direction (fig. 2D: 122/126 at least partially overlaps 112/116 in a vertical direction);
a plurality of gate structures (¶¶ 0045, 0053: plurality of 130 arranged in parallel) extended in a 2nd direction across the 1st and 2nd active patterns (figs. 2A-2C: 130 extends across 122/126 and 112/116 in a 2nd horizontal direction), the 2nd direction intersecting the 1st direction and the 3rd direction (fig. 2A: 130 extend in 2nd horizontal direction intersecting 1st horizontal direction and vertical direction);
a plurality of metal lines (¶¶ 0056, 0058: 132/134 and/or 142/144) in at least one metal layer of the at least one semiconductor device cell (¶ 0055: 132/134 and/or 142/144 comprised by metal layers L1 or L4), the metal lines being extended in the 1st direction (fig. 2A among others: 134/144 extend in 1st horizontal direction), and at least one of the metal lines being connected to at least one of the 1st and 2nd active patterns and the gate structures (¶ 0059 & fig. 2D among others: at least one 144 electrically connected to 112 or 122 through respective vias 162 or 166, at least one 144 electrically connected to 130 through via 152); and
at least one power rail (¶¶ 0056-0057: 132 and/or 142) connecting the at least one of the 1st and 2nd active patterns to at least one voltage source (¶ 0073, fig. 2D: 132 electrically connected to 116, 142 electrically connected to 126),
wherein the at least one power rail is disposed to be closer to at least one of the 1st and 2nd active pattern than an upper boundary or a lower boundary of the at least one semiconductor device cell (fig. 2B: 132/142 disposed closer to 122/126 or 112/116 than upper or lower boundary defined by CB).
Peng does not teach wherein each of the metal lines and the at least one power rail have a same width in the 2nd direction.
Peng-971 teaches a cell architecture comprising a semiconductor device cell (fig. 2A) including at least one metal line (¶¶ 0038-0039: 134a/134b, or 144a/144b) and at least one power rail (¶ 0040: 132/142) having a same width in a 2nd direction (¶ 0061: width ratio of 132 and 134 is about one in the x-axis direction).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the power rail and metal lines of Peng with the widths of Peng-971, as a means to minimize electrical resistance of the metal lines and/or power rails.
Furthermore, such a modification would have involved a mere change in the size of a component (e.g. increasing width(s) of metal line(s) 134/144). A change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 22, Peng in view of Peng-971 teaches the cell architecture of claim 21, wherein the at least one power rail is disposed to be closer to a virtual horizontal center line of the at least one semiconductor device cell extended in the 1st direction than an upper boundary or the lower boundary of the at least one semiconductor device cell (Peng, fig. 2B: 132/142 positioned closer to center of 200A than upper or lower boundary defined by CB).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Peng-971 as applied to claim 1 above, and further in view of Peng et al. (PG Pub. No. US 2020/0104460 A1, hereinafter referenced as ‘Peng-460’).
Regarding claim 8, Peng in view of Peng-971 teaches the cell architecture of claim 1, wherein the 1st and 2nd active patterns and the gate structures comprise a circuit (Peng, ¶ 0058).
Peng in view of Peng-971 does not teach the circuit is a logic circuit configured to perform a logic operation.
Peng-460 teaches a cell architecture (¶ 0122: 900) including a logic circuit configured to perform a logic operation (¶ 0123: 900 formed in a logic circuit).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the cell architecture of Peng in view of Peng-971 in a logic circuit, as a means to provide functions such as logic AND and NOR, enhancing functionality of the device.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Peng-971 as applied to claim 11 above, and further in view of You et al. (PG Pub. No. US 2021/0305232 A1).
Regarding claim 12, Peng in view of Peng-971 teaches the cell architecture of claim 11, wherein at least one of the two power rails is disposed vertically above at least one of the 1st and 2nd active patterns in the 3rd direction (Peng, figs. 2A, 2D: 142 disposed in layer L4 above 112 in layer L2 and 122 in layer L3).
Peng in view of Peng-971 does not teach both power rails disposed vertically above at least one of the 1st and 2nd active patterns in the 3rd direction.
You teaches a cell architecture (¶ 0036 & figs. 3-4 among others: CR1) including two power rails (VSS, VDD) disposed vertically above at least one of a 1st and a 2nd active pattern in a vertical direction (¶ 0115 & fig. 4: VSS, VDD positioned higher than active fins F1-F4).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure both power rails of Peng in view of Peng-971 vertically above at least one of the 1st and 2nd active patterns in the 3rd direction, as a means to reduce high level wiring, power loss and PnR resource loss (You, ¶ 0006), avoiding degradation in the performance and productivity of the semiconductor device (You, ¶ 0153).
Furthermore, it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japiske, 86 USPQ 70. In the instant case, rearranging the second power rail vertically above at least one of the 1st and 2nd active patterns in the 3rd direction would involve only routine skill.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Peng-971 as applied to claim 1 above, and further in view of Chen et al. (PG Pub. No. US 2019/0155984 A1).
Regarding claim 13, Peng in view of Peng-971 teaches the cell architecture of claim 1, wherein the at least one semiconductor device cell comprises a plurality of cells (Peng, ¶¶ 0037, 0069).
Peng is silent to wherein the plurality of cells is serially connected and arranged in the 1st direction, and
wherein a first cell height of a first cell among the cells is different from a second cell height a second cell among the cells.
Chen teaches a cell architecture (fig. 8: 800) including a plurality of cells (¶ 0044: 810a, 825) serially connected and arranged in a 1st direction (fig. 8: 810a, 825 serially connected and arranged in x-direction), and
wherein a first cell height of a first cell is different from a second cell height of a second cell (¶ 0042 & fig. 8: height of 810a different from height of 825).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure serially-connected cells of Peng in view of Peng-971 with different heights, as a means to optimize device layout, provide minimize metal connection lengths to provide a further compact integrated circuit (Chen, ¶ 0047).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of Peng-971 and Chen as applied to claim 13 above, and further in view of Chae et al. (PG Pub. No. US 2021/0151426 A1).
Regarding claim 14, Peng in view of Peng-971 and Chen teaches the cell architecture of claim 13, including 1st and 2nd active patterns (Peng, 112/116 and 122/126, and/or Chen, ¶ 0044: 810 and 821) in a plurality of cells (Peng, ¶ 0069: adjacent cells, and/or Chen, ¶ 0044: 810a, 825).
Peng in view of Peng-971 and Chen is silent to wherein a first width of at least one of the 1st and 2nd active patterns in at least one cell among the cells is different from a second width of corresponding at least one of the 1st and 2nd active patterns in at least another cell among the cells.
Chae teaches a cell architecture (fig. 6) wherein a width of at least one of a 1st and a 2nd active pattern (¶ 0044: ACT_1 or ACT_2) in at least one of the cells (¶ 0081: C1a) is different from a width of corresponding at least one of the 1st and 2nd active patterns of another at least one of the cells (¶¶ 0052-0053 & figs. 4A-4B: width of ACT_1 or ACT_2 in cell C2 different than width of ACT_1 or ACT_2 in cell C1).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to adjust the width of at least one of the 1st and the 2nd active pattern of Peng in view of Peng-971 and Chen, as a means to optimize performance of respective NMOS and PMOS devices (Chae, ¶ 0044: ACT_1 comprised by PMOS device, ACT_2 comprised by NMOS device), and enhance reliability and integration density of the semiconductor device of the cell architecture (Chae, ¶ 0167).
Response to Arguments
Applicant’s arguments, see page 2 of the arguments/remarks filed on 4/14/2026, with respect to the drawing objection have been fully considered and are persuasive. Accordingly, the drawing objection has been withdrawn.
Applicant’s arguments, see page 12 of the arguments/remarks filed on 4/14/2026, with respect to the 35 USC § 102 and 35 USC § 103 rejections of claims 1-18 and 21-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BRIAN TURNER/Examiner, Art Unit 2818
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