DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I, FIG. 5 in the reply filed on October 8, 2025 is acknowledged. The traversal is on the ground(s) that examination of the non-elected species would not create a serious search or examination burden. This is not found persuasive because there would be a serious search and examination burden since a search for one embodiment would not necessarily result in art applicable to all embodiments.
The requirement is still deemed proper and is therefore made FINAL.
Claim 15 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on October 8, 2025.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 12, 2023 and February 8, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 5 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al (U.S. 2014/0131786), and further in view of Han et al (U.S. 2011/0108962).
Regarding claim 1. Ryu et al discloses a semiconductor device (FIG. 3A-3B) comprising:
a substrate (FIG. 3B, item 100) extending in a first direction (FIG. 3A-3B, item D2) and a second direction (FIG. 3A-3B, item D1) perpendicular ([0058]) to the first direction (FIG. 3A-3B, item D2);
a first active pattern (FIG. 3A-3B, item CA) included in an upper portion ([0058]) of the substrate (FIG. 3A-3B, item 100) in a memory cell region (FIG. 3A-3B, item 50), and having an isolated shape ([0058]) extending in a third direction (FIG. 3A-3B, item A) that is oblique ([0058]) to the first direction (FIG. 3A-3B, item X), the third direction (FIG. 3A-3B, item A) being a major axis direction ([0058]) of the first active pattern (FIG. 3A-3B, item 110);
a first device isolation pattern (FIG. 3A-3B, item 107) formed inside a first trench (FIG. 3A-3B, item 105) included in the substrate (FIG. 3A-3B, item 100) in the memory cell region (FIG. 3A-3B, item 50), and covering a side wall ([0061]) of the first active pattern (FIG. 3A-3B, item CA);
a first gate structure (FIG. 3A-3B, item GE) formed inside a gate trench (FIG. 3A-3B, item 105) extending in the first direction (FIG. 3A, item D1) on upper portions of the first active pattern (FIG. 3A-3B, item CA) and the first device isolation pattern (FIG. 3A-3B, item 107);
first (FIG. 3B, item SD1) and second (FIG. 3B, item SD2) impurity regions ([0064]) on the upper portion ([0064]) of the first active pattern (FIG. 3A-3B, item CA) that is adjacent ([0064]) to both sides ([0064]) of the first gate structure (FIG. 3A-3B, item GE)
Ryu et al fails to explicitly disclose a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern;
However, Han et al teaches a barrier impurity region (FIG 3, item 122a; [0031], i.e. polysilicon doped with impurities having the same conductivity as the channel of the transistor) selectively formed only on surfaces of both side walls ([0043]-[0045]) of the major axis of the first active pattern (FIG 4, item 102; [0028]);
Since Ryu et al and Han et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Ryu et al with the teachings of a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern as disclosed by Han e al. The use of polysilicon doped with impurities having the same conductivity as the channel of the transistor in Han et al provides for preventing holes from being induced to the active regions and adjacent the filling dielectric layer (Han et al, [0031]).
Regarding claim 2. Ryu et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Han et al further discloses wherein the barrier impurity region (FIG 3, item 122) includes an impurity ([0031]) having a negative charge ([0031]) when doped ([0031]; [0027]) to the substrate (FIG 3, item 100).
Regarding claim 5. Ryu et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Han et al further discloses wherein a bottom surface of the barrier impurity region (FIG 4, item 122a; [0031]) is lower than a bottom surface of the first gate structure (FIG 4, item 160; [0028]).
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2022/0028868), and Glass et al (U.S. 2021/0005748).
Regarding claim 1. Kim et al discloses a semiconductor device (FIG. 8-11) comprising:
a substrate (FIG. 9, item 100) extending in a first direction (FIG. 9, item D1) and a second direction (FIG. 9, item D2) perpendicular ([0024]) to the first direction (FIG. 9, item D1);
a first active pattern (FIG. 8, item CACT) included in an upper portion ([0034]) of the substrate (FIG. 8, item 100) in a memory cell region (FIG. 8, item CR), and having an isolated shape ([0034]) extending in a third direction (FIG. 9, item D3) that is oblique ([0024]) to the first direction (FIG. 9, item D1), the third direction (FIG. 9, item D3) being a major axis direction ([0024], [0034]) of the first active pattern (FIG. 9, item CACT);
a first device isolation pattern (FIG. 8, item GI) formed inside a first trench ([0056]) included in the substrate (FIG. 8, item 100) in the memory cell region (FIG. 8, item CR), and covering a side wall ([0034]) of the first active pattern (FIG. 8, item CACT);
a first gate structure (FIG. 11, item GE) formed inside a gate trench ([0056]) extending in the first direction (FIG. 9, item D1) on upper portions of the first active pattern (FIG. 8, item CACT) and the first device isolation pattern (FIG. 11, item GI);
first (FIG. 11, item SD1) and second (FIG. 11, item SD2) impurity regions ([0057]) on the upper portion ([0057]) of the first active pattern (FIG. 11, item CACT) that is adjacent ([0057]) to both sides ([0057]) of the first gate structure (FIG. 11, item CACT).
Kim et al fails to explicitly disclose a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern;
However, Glass et al teaches a barrier impurity region (FIG 2L, item 212; [0025]) selectively formed only on surfaces of both side walls ([0025], i.e. Dopant diffusion barrier is configured to separate source/drain fin structures 202 from shallow trench isolation (STI) regions 220) of the major axis of the first active pattern ([0025]);
Since Kim et al and Han et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al with the teachings of a dopant diffusion barrier is configured to separate source/drain fin structures from shallow trench isolation (STI) regions as disclosed by Glass et al. The use of polysilicon doped with impurities having the same conductivity as the channel of the transistor in glass et al provides for any material or composition that inhibits the diffusion of S/D dopant into the neighboring STI areas, particularly in the context of a n-type Ge-rich channel device (Glass et al, [0025]).
Regarding claim 4. Kim et al and Glass et al discloses all the limitations of the semiconductor device of claim 1 above.
Glass et al further discloses wherein the barrier impurity region (FIG. 2L, item 212) is not formed on side walls of a minor axis (FIG. 2L, shows item 212 is not formed on the sidewalls of item X of items 230) of the first active pattern ([0025]Dopant diffusion barrier 212 is configured to separate source/drain fin structures 202 from shallow trench isolation (STI) regions 220).
Claims 1, 6-8, 10, 11, 13, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2022/0028868), and Han et al (U.S. 2011/0108962).
Regarding claim 1. Kim et al discloses a semiconductor device (FIG. 8-11) comprising:
a substrate (FIG. 9, item 100) extending in a first direction (FIG. 9, item D1) and a second direction (FIG. 9, item D2) perpendicular ([0024]) to the first direction (FIG. 9, item D1);
a first active pattern (FIG. 8, item CACT) included in an upper portion ([0034]) of the substrate (FIG. 8, item 100) in a memory cell region (FIG. 8, item CR), and having an isolated shape ([0034]) extending in a third direction (FIG. 9, item D3) that is oblique ([0024]) to the first direction (FIG. 9, item D1), the third direction (FIG. 9, item D3) being a major axis direction ([0024], [0034]) of the first active pattern (FIG. 9, item CACT);
a first device isolation pattern (FIG. 8, item GI) formed inside a first trench ([0056]) included in the substrate (FIG. 8, item 100) in the memory cell region (FIG. 8, item CR), and covering a side wall ([0034]) of the first active pattern (FIG. 8, item CACT);
a first gate structure (FIG. 11, item GE) formed inside a gate trench ([0056]) extending in the first direction (FIG. 9, item D1) on upper portions of the first active pattern (FIG. 8, item CACT) and the first device isolation pattern (FIG. 11, item GI);
first (FIG. 11, item SD1) and second (FIG. 11, item SD2) impurity regions ([0057]) on the upper portion ([0057]) of the first active pattern (FIG. 11, item CACT) that is adjacent ([0057]) to both sides ([0057]) of the first gate structure (FIG. 11, item CACT).
Kim et al fails to explicitly disclose a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern;
However, Han et al teaches a barrier impurity region (FIG 3, item 122a; [0031], i.e. polysilicon doped with impurities having the same conductivity as the channel of the transistor) selectively formed only on surfaces of both side walls ([0043]-[0045]) of the major axis of the first active pattern (FIG 4, item 102; [0028]);
Since Kim et al and Han et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al with the teachings of a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern as disclosed by Han e al. The use of polysilicon doped with impurities having the same conductivity as the channel of the transistor in Han et al provides for preventing holes from being induced to the active regions and adjacent the filling dielectric layer (Han et al, [0031]).
Regarding claim 6. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Han et al further discloses wherein the barrier impurity region (FIG 4, item 122a; [0031]) extends from a top surface ([0043]) of the first active pattern (FIG 4, item 122a; [0031]) to a portion (FIG. 4, item 166) under a bottom surface ([0036]) of the first device isolation pattern (FIG. 4, item 166).
Regarding claim 7. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al wherein two first gate structures (FIG. 11, item GE) are spaced apart ([0056]) from each other ([0056]) in one first active pattern (FIG. 11, item CACT), and one first gate structure (FIG. 11, item GE) is disposed in each ([0056]) of first device isolation patterns (FIG. 11, item GI) contacting both ends ([0056]) of the one first active pattern (FIG. 11, item CACT) in a major axis direction (FIG. 11, item D1).
Regarding claim 8. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein the first impurity region (FIG. 11, item SD1) is located at a central portion ([0057]) of the first active pattern (FIG. 11, item SD1) in the major axis direction (FIG. 11, item D1) the second impurity region (FIG. 11, item SD2) is located at both edges ([0057]) of the first active pattern (FIG. 11, item CACT) in the major axis direction (FIG. 11, item D1), and the semiconductor device (FIG. 11) further comprises: a bit line structure (FIG. 11, item DC) electrically connected ([0059]) to the first impurity region (FIG. 11, item SD1); and a capacitor electrically (FIG. 11, item CA) connected ([0059]) to the second impurity region (FIG. 11, item SD2).
Regarding claim 9. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Kim et al further discloses wherein a second trench (FIG. 8, item 200T) is included in the substrate (FIG. 8, item 100) in a boundary region (FIG. 8, item BR), which makes contact with an edge of the memory cell region (FIG. 8, item CR), a second device isolation pattern (FIG. 8, item 200) filling the second trench (FIG. 8, item 200T) is provided, and a bottom surface (FIG. 8, item 200B) of the second trench (FIG. 8, item 200T) has a step shape ([0046]) without being flat ([0046]).
Regarding claim 10. Kim et al discloses A semiconductor device (FIG. 8-11) comprising: a substrate (FIG. 8, item 100) including a memory cell region (FIG. 8, item CR), a core-peripheral region (FIG. 8, item PR), and a boundary region (FIG. 8, item BR) between the memory cell region (FIG. 8, item CR) and the core-peripheral region (FIG. 8, item PR);
a first active pattern (FIG. 8, item CACT) and a first device isolation pattern (FIG. 8, item GI), which are formed on an upper portion of the substrate (FIG. 8, item 100) in the memory cell region (FIG. 8, item CR);
a second device isolation pattern (FIG. 8, item 200) filling a second trench (FIG. 8, item 200T) included in the substrate (FIG. 8, item 100) in the boundary region (FIG. 8, item BR) between the memory cell region (FIG. 8, item CR) and the core-peripheral region (FIG. 8, item PR);
a third device isolation pattern (FIG. 11, item 150C2) filling a third trench included in the substrate (FIG. 11, item 100) in the core-peripheral region (FIG. 11, item CR);
a first gate structure (FIG. 11, item GE) formed inside a gate trench ([0056]) extending in a first direction (FIG. 11, item D4 on upper portions of the first active pattern (FIG. 11, item GE) and the first device isolation pattern (FIG. 11, item GI);
first (FIG. 11, item SD1) and second (FIG. 11, item SD2) impurity regions ([0057]) on the upper portion of the first active pattern (FIG. 11, item CACT) that is adjacent to both sides ([0057]) of the first gate structure (FIG. 11, item GE),
wherein a bottom surface (FIG. 8, item 200B) of the second trench (FIG. 8, item 200T) has a step shape ([0046]) without being flat ([0046]).
Kim et al fails to explicitly disclose a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern;
However, Han et al teaches a barrier impurity region (FIG 3, item 122a; [0031], i.e. polysilicon doped with impurities having the same conductivity as the channel of the transistor) selectively formed only on surfaces of both side walls ([0043]-[0045]) of the major axis of the first active pattern (FIG 4, item 102; [0028]);
Since Kim et al and Han et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al with the teachings of a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern as disclosed by Han e al. The use of polysilicon doped with impurities having the same conductivity as the channel of the transistor in Han et al provides for preventing holes from being induced to the active regions and adjacent the filling dielectric layer (Han et al, [0031]).
Regarding claim 11. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Han et al further discloses wherein the barrier impurity region (FIG 3, item 122) includes an impurity ([0031]) having a negative charge ([0031]) when doped ([0031]; [0027]) to the substrate (FIG 3, item 100).
Regarding claim 13. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 10 above.
Han et al wherein a bottom surface (FIG. 4, bottom surface of item 122a) of the barrier impurity region (FIG. 4, item 122a) is lower (FIG. 4 shows bottom surface of item 122a is lower than a bottom surface of item 160) than a bottom surface (FIG. 4, bottom surface of item 160) of the first gate structure (FIG. 4, item 160).
Regarding claim 16. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 10 above.
Kim et al wherein two first gate structures (FIG. 11, item GE) are spaced apart ([0056]) from each other ([0056]) in one first active pattern (FIG. 11, item CACT), and one first gate structure (FIG. 11, item GE) is disposed in each ([0056]) of first device isolation patterns (FIG. 11, item GI) contacting both ends ([0056]) of the one first active pattern (FIG. 11, item CACT) in a major axis direction (FIG. 11, item D1).
Regarding claim 17. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 10 above.
Kim et al wherein the first impurity region (FIG. 11, item SD1) is located at a central portion ([0057]) of the first active pattern (FIG. 11, item SD1) in the major axis direction (FIG. 11, item D1) the second impurity region (FIG. 11, item SD2) is located at both edges ([0057]) of the first active pattern (FIG. 11, item CACT) in the major axis direction (FIG. 11, item D1), and the semiconductor device (FIG. 11) further comprises: a bit line structure (FIG. 11, item DC) electrically connected ([0059]) to the first impurity region (FIG. 11, item SD1); and a capacitor electrically (FIG. 11, item CA) connected ([0059]) to the second impurity region (FIG. 11, item SD2).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2022/0028868), and Han et al (U.S. 2011/0108962) as applied to claim 1 above, and further in view of Lee et al (U.S. 2015/0021684).
Regarding claim 3. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 1 above.
Han et al discloses the wherein an impurity included in the barrier impurity region (FIG 3, item 122a; [0031], i.e. polysilicon doped with impurities)
Kim et al and Han et al fails to explicitly disclose an impurity includes silicon germanium or fluorine.
However Lee et al teaches wherein an impurity included in the barrier impurity region ([0078], i.e. the carrier barrier layer item 106c) includes silicon germanium or fluorine ([0078], i.e. be formed of or may include, e.g., one of carbon, germanium, and argon, which are non-conductive impurities).
Since Kim et al, Han et al and Lee et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al and Han et al with the teachings of wherein an impurity included in the barrier impurity region includes silicon germanium or fluorine as disclosed by Lee et al. The use of the carrier barrier layer may be formed of or may include, e.g., one of carbon, germanium, and argon, which are non-conductive impurities in Lee et al provides for the electrical characteristics of the device may not be affected even the carrier barrier layer extends across the entire active region 101 (Lee et al, [0078]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2022/0028868), and Han et al (U.S. 2011/0108962) as applied to claim 10 above, and further in view of Lee et al (U.S. 2015/0021684).
Regarding claim 12. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 10 above.
Han et al discloses the wherein an impurity included in the barrier impurity region (FIG 3, item 122a; [0031], i.e. polysilicon doped with impurities)
Kim et al and Han et al fails to explicitly disclose an impurity includes silicon germanium or fluorine.
However Lee et al teaches wherein an impurity included in the barrier impurity region ([0078], i.e. the carrier barrier layer item 106c) includes silicon germanium or fluorine ([0078], i.e. be formed of or may include, e.g., one of carbon, germanium, and argon, which are non-conductive impurities).
Since Kim et al, Han et al and Lee et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semid as disclosed to modify Kim et al and Han et al with the teachings of wherein an impurity included in the barrier impurity region includes silicon germanium or fluorine as disclosed by Lee et al. The use of the carrier barrier layer may be formed of or may include, e.g., one of carbon, germanium, and argon, which are non-conductive impurities in Lee et al provides for the electrical characteristics of the device may not be affected even the carrier barrier layer extends across the entire active region 101 (Lee et al, [0078]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2022/0028868), and Han et al (U.S. 2011/0108962) as applied to claim 10 above, and further in view of Kim (U.S. 2004/0183139).
Regarding claim 14. Kim et al and Han et al discloses all the limitations of the semiconductor device of claim 10 above.
Kim et al teaches the second trench (FIG. 7, item 200T).
Some fails to explicitly disclose wherein the second trench includes:
a first region that is adjacent to the memory cell region in the boundary region;
a second region that is adjacent to the core-peripheral region in the boundary region; and
a third region between the first region and the second region, and a bottom surface of the third region is lower than a bottom surface of each of the first and second regions.
However, Kim (‘139) teaches wherein the second trench includes (FIG. 17, item 85d):
a first region (FIG. 17, item 85A) that is adjacent ([0046]) to the memory cell region (FIG. 17, item A) in the boundary region (FIG. 17, item D);
a second region that (FIG. 17, item 85B) is adjacent ([0046]) to the core-peripheral region (FIG. 17, item B) in the boundary region (FIG. 17, item D); and
a third region (FIG. 17, item 85d) between the first region (FIG. 17, item 85A) and the second region(FIG. 17, item 85B), and a bottom surface of the third region (FIG. 17, item 85d) is lower ([0046]; i.e. the peripheral circuit trench region 85b is formed to be deeper than the cell trench region 85a, and the border trench region 85d is formed to be deeper than the peripheral circuit trench region 85b) than a bottom surface of each of the first (FIG. 17, item 85A) and second regions (FIG. 17, item 85B).
Since Kim et al, Han et al and Kim (‘139) teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor as disclosed to modify Kim et al, and Han et al with the teachings of the second trench includes, a first region that is adjacent to the memory cell region in the boundary region, a second region that is adjacent to the core-peripheral region in the boundary region, and a third region between the first region and the second region, and a bottom surface of the third region is lower than a bottom surface of each of the first and second regions as disclosed by Kim (‘139). The use of the peripheral circuit trench region is formed to be deeper than the cell trench region, and the border trench region is formed to be deeper than the peripheral circuit trench region in Kim (‘139) provides for semiconductor memory devices according to some embodiments of the invention do not have undesired active regions formed in the border region (Kim (‘139), [Abstract]).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al (U.S. 2022/0028868), Han et al (U.S. 2011/0108962), and Lee et al (U.S. 2015/0021684).
Regarding claim 18. Kim et al discloses A semiconductor device (FIG. 8-11) comprising: a substrate (FIG. 8, item 100) including a memory cell region (FIG. 8, item CR), a core-peripheral region (FIG. 8, item PR), and a boundary region (FIG. 8, item BR) between the memory cell region (FIG. 8, item CR) and the core-peripheral region (FIG. 8, item PR);
a first active pattern (FIG. 8, item CACT) and a first device isolation pattern (FIG. 8, item GI), which are formed on an upper portion of the substrate (FIG. 8, item 100) in the memory cell region (FIG. 8, item CR);
a second device isolation pattern (FIG. 8, item 200) filling a second trench (FIG. 8, item 200T) included in the substrate (FIG. 8, item 100) in the boundary region (FIG. 8, item BR) between the memory cell region (FIG. 8, item CR) and the core-peripheral region (FIG. 8, item PR);
a third device isolation pattern (FIG. 11, item 150C2) filling a third trench included in the substrate (FIG. 11, item 100) in the core-peripheral region (FIG. 11, item CR);
a first gate structure (FIG. 11, item GE) formed inside a gate trench ([0056]) extending in a first direction (FIG. 11, item D4 on upper portions of the first active pattern (FIG. 11, item GE) and the first device isolation pattern (FIG. 11, item GI);
first (FIG. 11, item SD1) and second (FIG. 11, item SD2) impurity regions ([0057]) on the upper portion of the first active pattern (FIG. 11, item CACT) that is adjacent to both sides ([0057]) of the first gate structure (FIG. 11, item GE),
wherein a bottom surface (FIG. 8, item 200B) of the second trench (FIG. 8, item 200T) has a step shape ([0046]) without being flat ([0046]).
a bit line structure (FIG. 11, item DC) electrically connected ([0059]) to the first impurity region (FIG. 11, item SD1); and a capacitor electrically (FIG. 11, item CA) connected ([0059]) to the second impurity region (FIG. 11, item SD2).
Kim et al fails to explicitly disclose a barrier impurity region selectively formed only on surfaces of both side walls of a major axis of the first active pattern, and doped with silicon germanium or fluorine.
However, Han et al teaches a barrier impurity region (FIG 3, item 122a; [0031], i.e. polysilicon doped with impurities having the same conductivity as the channel of the transistor) selectively formed only on surfaces of both side walls ([0043]-[0045]) of the major axis of the first active pattern (FIG 4, item 102; [0028]);
Since Kim et al and Han et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semiconductor device as disclosed to modify Kim et al with the teachings of a barrier impurity region selectively formed only on surfaces of both side walls of the major axis of the first active pattern as disclosed by Han e al. The use of polysilicon doped with impurities having the same conductivity as the channel of the transistor in Han et al provides for preventing holes from being induced to the active regions and adjacent the filling dielectric layer (Han et al, [0031]).
Kim et al and Han et al fails to explicitly disclose an impurity includes silicon germanium or fluorine.
However Lee et al teaches wherein an impurity included in the barrier impurity region ([0078], i.e. the carrier barrier layer item 106c) includes silicon germanium or fluorine ([0078], i.e. be formed of or may include, e.g., one of carbon, germanium, and argon, which are non-conductive impurities).
Since Kim et al, Han et al and Lee et al teach semiconductor devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the semid as disclosed to modify Kim et al and Han et al with the teachings of wherein an impurity included in the barrier impurity region includes silicon germanium or fluorine as disclosed by Lee et al. The use of the carrier barrier layer may be formed of or may include, e.g., one of carbon, germanium, and argon, which are non-conductive impurities in Lee et al provides for the electrical characteristics of the device may not be affected even the carrier barrier layer extends across the entire active region 101 (Lee et al, [0078]).
Regarding claim 19. Kim et al, Han et al, and Lee et al discloses all the limitations of the semiconductor device of claim 1 above.
Han et al further discloses wherein a bottom surface of the barrier impurity region (FIG 4, item 122a; [0031]) is lower than a bottom surface of the first gate structure (FIG 4, item 160; [0028]).
Regarding claim 20. Kim et al, Han et al, and Lee et al discloses all the limitations of the semiconductor device of claim 18 above.
Han et al further discloses wherein the barrier impurity region (FIG 4, item 122a; [0031]) extends from a top surface ([0043]) of the first active pattern (FIG 4, item 122a; [0031]) to a portion (FIG. 4, item 166) under a bottom surface ([0036]) of the first device isolation pattern (FIG. 4, item 166).
Conclusion
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815