DETAILED ACTION
This action is responsive to the amendment received on 10/14/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for priority under 35 U.S.C. 119(a)-(d) or (f), 365(a) or (b), or 386(a) based upon an application filed in TAIWAN on 12/08/2022.
Specification
The amendment filed 10/14/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
[0022], lines 17-19, “the thickness of epitaxially grown silicon sacrificial layers 120 is preferably controlled so that they may provide sufficient protection for the gates 110 and the substrate 100 in the etchback process”. The original description described only complete removal of sacrificial layers. The amendment encompasses new embodiments wherein the silicon sacrificial layers have a thickness beyond what would be completely removed by the etchback to ensure protection of underlying structures.
Applicant is required to cancel the new matter in the reply to this Office Action.
Drawings
The amendment filed 10/14/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
New Figure 11, added by the amendment, is described in the specification, [0020], as “each gate 110 may be a select gate in flash memory, and the control gate 108 connects the floating gate 104 through an opening 130 of the inter-gate dielectric layer 106 as shown in FIG. 11”.
This drawing represents new matter as it shows the control gate as making direct contact with the floating gate through the opening. This is contradictory to the standard structural relationship of control and floating gates wherein the electrical connection is opposing plates of a capacitor with the dielectric therebetween to ensure the floating gate is actually floating. This direct contact structure does not appear to have support in the originally filed specification as it represents an entirely different gate structure than previously provided.
Applicant is required to cancel the new matter in the reply to this Office Action. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 1 recites the limitation “performing an epitaxy process to form epitaxially grown silicon sacrificial layers . . . performing a first etchback process using phosphoric acid to pull back said silicon nitride spacers, and said first etchback process removes said epitaxially grown silicon sacrificial layers”. This limitation Is not interpreted as enabled by the specification based on the level of understanding of one of ordinary skill in the art. As such, the specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and used the claimed invention without undue experimentation.
Enablement, or lack thereof, is best understood through a framework of factors, referred to as the Wands factors, to assess whether any necessary experimentation required by the specification is “reasonable” or is “undue”. Several of these factors will be considered below in relation to the claimed invention.
The amount of direction provided by the inventor is interpreted to be insufficient by the examiner. Specifically, applicant states in [0021] that “thin epitaxially grown silicon sacrificial layers 120 are formed on exposed substrate 100 and top surfaces of gates 110, which may be formed on Si-based surfaces through epitaxial growth in MOCVD process” then further provides in [0022] that “the thickness of epitaxially grown silicon sacrificial layers 120 is preferably controlled so that they may provide sufficient protection for the gates 110 and the substrate 100 in the etchback process. For example, if the dimension of silicon nitride spacers 114a pulled back in this etchback process is 3-5nm, the thickness of epitaxially grown silicon sacrificial layer 120 is approximately 10nm.” No further explanation appears to be given about the silicon material’s growth or the etchback process. Applicant has not provided any details about the etchback process such as etchant concentrations, times, or temperatures. All of these factors are essential in achieving applicant‘s claimed results. The claims suggest that this process is performed such that the epitaxially grown silicon sacrificial layer is entirely removed (see claim), while the silicon nitride spacers are just slightly pulled back (see claim), and with no damage to the underlying active layer structures under the epitaxial silicon sacrificial structures (see [0021], “the function of epitaxially grown silicon sacrificial layers 120 is to prevent additional etchback process later for the silicon nitride spacers 114a damaging exposed top surfaces of gates 110 as well as active areas or STIs in the substrate”). Yet, all of the above parameters (thickness, times, etchant concentration, etc.) will have extensive implications on the outcome of the process and are not sufficiently detailed by the applicant.
Examiner was unable to find any existence of working examples wherein a silicon nitride layer is etched to a lesser extent (3-5 nm) than an epitaxial silicon layer (10 nm) by a phosphoric acid etchant in the same process. Applicant has not provided any references by way of an IDS and examiner’s search has not yielded any further references that provide an example of a Si-based epitaxial material which may be fully etched away at a thickness of 10 nm while a neighboring silicon nitride layer is etched by only 3-5 nm as indicated by the quote above from [0022]. All of the references identified by the examiner appear to suggest the opposite, that phosphoric acid is commonly selected specifically for its selectivity in etching silicon nitride over other silicon based materials (additional details will be provided below) such that no working examples were found where silicon nitride is etched to a lesser extent than other Si-based epitaxial materials such that the epitaxial silicon layer may be completely removed while the silicon nitride layer remains as required by the claim.
The state of the prior art, the level of predictability in the art, and the level of one of ordinary skill all point to silicon nitride being preferentially etched by phosphoric acid over other epitaxial silicon materials. Several references identified by the examiner and corresponding quotes which support this interpretation are provided below. Pending the existence of further evidence, the prior art identified and level of one of ordinary skill in the art based on the available art would not enable producing an epitaxial silicon film which is completely etched by phosphoric acid while silicon nitride remains, given the thicknesses indicated in the applicant provided example.
US 20250254912 A1; Chen et al.; 08/2025; [0047] – “Phosphoric acid is effective at etching nitride-based materials at a significantly higher etch rate compared to silicon, allowing for the precise removal of the SiOCN isolation sidewall dielectrics 232 without affecting the silicon epitaxial layers”.
US 2020/0373323 A1; Inoue, Shigehisa; 11/2020; [0030] – “Phosphoric acid is often used to etch silicon nitride films because of its selectivity for etching silicon nitride over silicon oxide and etching rate for silicon nitride”.
US 2020/0126987 A1; Rubin et al.; 04/2020; [0065] – “when formed of silicon nitride, the etch stop layer can be etched away using a hot mixture of phosphoric acid and water at a high temperature to etch silicon nitride selective to the materials of, e.g., the insulating layer (e.g., silicon dioxide), the epitaxial material of the source/drain layers, and the dielectric materials of the gate sidewall spacers, the gate capping layers, and the inner spacers . . . the dielectric materials of the gate sidewall spacers, the gate capping layers, and the inner spacers are formed of dielectric materials such as, e.g., SiBCN, SiOCN, etc. which have etch electivity with respect to the dielectric material of the etch stop layer”.
Understanding the Role of Concentrated Phosphoric Acid Solutions as High-Temperature Silicon Nitride Etchants, Tal Joseph and Daniela White 2021 ECS J. Solid State Sci. Technol. 10 024006; page 1, column 1, “High Si3N4 removal rates and low SiO2 removal rates are required for high-selectivity formulations based on phosphoric acid.”
The quantity of experimentation needed to make or use the invention based on the content of the disclosure is extensive given the lack of provided details. The epitaxial silicon’s growth conditions would need to be identified/optimized to provide the correct thickness to ensure protection of the underlying structures. Given the selected thickness, one of ordinary skill in the art would need to figure out the necessary etching conditions to achieve the desired result including etchant concentration, time, and temperature among other conditions to subsequently completely remove the epitaxial silicon layer without any damage to underlying structures while also sufficiently pulling back the silicon nitride layers as claimed. All of the requirements combined are interpreted by the examiner to represent an extensive, and beyond reasonable, amount of experimentation to make or use the claimed invention.
Based on the lack of enablement for “performing an epitaxy process to form silicon-based sacrificial layers . . . performing a first etchback process using phosphoric acid to pull back said silicon nitride spacers, and said first etchback process removes said silicon-based sacrificial layers” in view of the specification, claims, and available prior art, the application does not enable one skilled in the art to which it pertains, or with which it is most nearly connected to make and/or use the claimed invention. Claim 1 is therefore rejected under 35 U.S.C. 112(a) for lacking enablement and the balance of claims are rejected under 35 U.S.C. 112(a) at least for their dependencies.
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “in each of said select gates, said control gate connects said floating gate through an opening of said multilayer structure” in lines 3-4 of the claim. This limitation is unclear in view of the specification and drawings. It is unclear if applicant is claiming the standard structural relationship of control and floating gates wherein the connection is electrical as opposing plates of a capacitor with the dielectric therebetween to ensure the floating gate is actually floating. Newly added Figure 11 and amended description in [0020] of the specification shows control gates which are directly connected to the floating gates, i.e. the floating gates are no longer floating which would represent a 112(b) issue for lack of clarity of the meaning of “floating gate”. Either of these interpretations may be applicant’s intent and the examiner is unable to determine which. Claim 9 is therefore rejected under 35 U.S.C. 112(b).
Response to Arguments/Amendments
Applicant’s amendment to the drawings and corresponding remarks, see page 11 of the remarks, filed 10/14/2025, with respect to the objections to the drawings have been fully considered. The amendments to the drawings have resolved the previous issue of not showing claimed subject matter such that the previous objection has been withdrawn. However, the addition of new Figure 11 is interpreted by the examiner to represent new matter as described above. Specifically, new Figure 11 represents new matter as it shows the control gate as making direct contact with the floating gate through the opening. This is contradictory to the standard structural relationship of control and floating gates wherein the electrical connection is opposing plates of a capacitor with the dielectric therebetween to ensure the floating gate is actually floating. This direct contact structure does not appear to have support in the originally filed specification as it represents an entirely different gate structure than previously provided. The drawings remain objected to.
Applicant’s amendments to the specification and claims and corresponding arguments, see pages 12-14 of the remarks, filed 10/14/2025, with respect to the 35 U.S.C. 112(a) rejections of claims 1-9, have been fully considered but are not found persuasive. Applicant provides the following arguments in the remarks:
Argument (1), page 12 of the remarks – Applicant has amended [0022] of the specification to recite “the thickness of epitaxially grown silicon sacrificial layers 120 is preferably controlled so that they may provide sufficient protection for the gates 110 and the substrate 100 in the etchback process. For example, if the dimension of silicon nitride spacers 114a pulled back in this etchback process is 3-5nm, the thickness of epitaxially grown silicon sacrificial layer 120 is approximately 10nm.” and further suggests in the remarks that the intended meaning of this description in the specification is that “the thickness of the Si sacrificial layer 120 should be less than 10 nm, and the actual thickness of the Si layer 120 may vary depending on etching conditions”.
Argument (2), pages 12-14 of the remarks – Applicant has amended all instances of “Si-based sacrificial layer” to read as “epitaxially grown silicon sacrificial layer”, or the like, in the claims and specification. Applicant further argues that one of ordinary skill in the art would be able to grow and subsequently etch the sacrificial layer to achieve the desired result of protecting the underlying structures during the etch without undue experimentation and through routine optimization.
Examiner respectfully disagrees with applicant’s conclusion and arguments. Specifically, while applicant has amended the specification as described in arguments (1) and (2), applicant’s argument regarding interpretation of the specification as amended is not believed to be a reasonable interpretation of the provided language. The specification explicitly states “if the dimension of silicon nitride spacers 114a pulled back in this etchback process is 3-5nm, the thickness of Si-based epitaxially grown silicon sacrificial layer 120 is approximately 10nm”. This does not appear to encompass applicants interpretation that the sacrificial layer “should be less than 10 nm”. In fact, the use of the word “approximately” encompasses values which are greater than 10 nm. In argument (1), applicant “concurs with the Examiner's observation that phosphoric acid tends to etch silicon nitride (SiN) more readily than silicon (Si)”. Furthermore, while the examiner agrees with applicant that one of ordinary skill in the art would be able to grow/etch the sacrificial layer as necessary, without undue experimentation, and through routine optimization; the applicant has provided only one example which is not believed to be within the range of ordinary. The combination of both the cited prior art and applicant’s concurrence with the examiner’s interpretation renders the provided example outside the scope of one of ordinary skill in the art. It remains unclear how one may etch back silicon nitride with phosphoric acid to only 3-5 nm while completely etching silicon sacrificial layers of approximately 10 nm, the only provided example, when all evidence (cited prior art and concurrence between examiner and applicant) points to silicon nitride being preferentially etched at a greater rate than epitaxial silicon. Therefore, it is the examiners interpretation that the provided example in the specification combined with all available evidence does not render claim 1 as enabled. Claim(s) 1-9 stand rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement.
Applicant’s amendments to claims 1 and 2 and corresponding remarks, see pages 14-16 of the remarks, filed 10/14/2025, with respect to the 35 U.S.C. 112(b) rejections of claims 1-9 have been fully considered. The amendments to the claims have resolved some of the previous issues, the 35 U.S.C. 112(b) rejections of claims 1-8 have been withdrawn. However, claim 9 stands rejected under 35 U.S.C. 112(b) for the reasons described above and discussed further below.
Applicant’s amendments to the drawings and corresponding remarks, see pages 16 of the remarks, filed 10/14/2025, with respect to the 35 U.S.C. 112(b) rejection of claims 9 have been fully considered. The amendments to the drawings, while resolving the previous issue, have created a new issue which renders the claim indefinite as described above. Newly added Figure 11 and amended description in [0020] of the specification shows control gates which are directly connected to the floating gates, i.e. the floating gates are no longer floating which represents a lack of clarity of the meaning of “floating gate”. The 35 U.S.C. 112(b) rejection of claim 9 is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TYLER JAMES WIEGAND whose telephone number is (571)270-0096. The examiner can normally be reached Mon-Fri. 8AM-5PM.
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/TYLER J WIEGAND/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812