DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 01/14/2026.
Claims 9-16, and 21-31 are pending in this application.
Claims 1-8, and 17-20 have been cancelled.
Remarks
2. Applicant's arguments have been fully considered, but are moot in view of a new ground of rejection. See details below.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 22-24, 26-28, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hshieh (US 7,863,685)
Regarding claim 22, Hshieh discloses an integrated circuit, comprising:
an epitaxial layer N (see Fig. 1C and col. 1, line 64 – col. 2, line 9: Fig. 1C shown a prior art from U.S. Pat. No. 6,433,396 to Kinzer; see also the Annotated Drawing below) having a first conductivity type (N-type layer) over a semiconductor substrate (bottom N+ layer);
a trench gate transistor extending into the substrate, the transistor including first and second trench gates extending into the epitaxial layer N;
a body region P having an opposite second conductivity type (p-type) extending contiguously from a first dielectric layer (first gate dielectric surrounding the leftmost trench gate) that touches the first trench gate to a second dielectric layer (second gate dielectric surrounding the middle trench gate) that touches the second trench gate; and
a metal-containing layer (Alum layer) that extends over and touches the body region P and the epitaxial layer N.
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Regarding claim 23, Hshieh discloses the integrated circuit of claim 22, wherein the trench gate transistor is one of a plurality of trench gate transistors arranged in a linear array, and the metal-containing layer Al Alloys connects body regions of the plurality of trench gate transistors. See fig. 1D.
Regarding claim 24, Hshieh discloses the integrated circuit of claim 23, wherein the linear array is a first linear array, and the plurality of trench gate transistors includes a second linear array of trench gate transistors parallel to the first linear array. Note that this is a common structure of integrated circuit in the art, and hence would not bear any critical value for patentability.
Regarding claim 26, Hshieh discloses the integrated circuit of claim 22, wherein the metal-containing layer 140 (fig. 6) comprises TiN or TaN. Note that one of ordinary skills in the art would understand that a barrier Silicide/TiN metal layer like layer 140 in fig. 6 can always be added into the Al Alloys contact of fig. 1C to improve contact resistance, un-wanted ion diffusion, etc, and this would involve only routine skills in the art.
Regarding claim 27, Hshieh disclseos the integrated circuit of claim 22, wherein the first conductivity type is n-type and the second conductivity type is p-type. See fig. 1C.
Regarding claim 28, Hshieh discloses an integrated circuit, comprising:
an epitaxial layer N (fig. 1D) having a first conductivity type (n-type) over a semiconductor substrate N+;
first and second portions of the epitaxial layer N (the first portion is portion of the epitaxial layer N between the leftmost Doped Poly gate and the left Al Alloys/Trench Schottky, and protruding above the bottom of the Al Alloys/Trench Schottky in fig. 1D, and the second portion is between the Al Alloys/Trench Schottky and the middle Doped Poly gate, protruding above the bottom of the Al Alloys/Trench Schottky) that extend to a planar surface (surface at the interface between the epitaxial layer N and the body region P, or upper surface) of the epitaxial layer N;
a trench gate transistor located between first and second trenches and including a body region P having an opposite second conductivity type (p-type) touching the first and second portions of the epitaxial layer N and having a body surface (bottom surface) coplanar with the planar surface (upper surface) of the epitaxial layer N; and
a metal-containing layer (Al Alloys, or Silicide/TiN layer 140 in fig. 1D and/or fig. 6) on the first and second portions of the epitaxial layer N and the body regions P, the metal-containing layer forming a Schottky barrier with the first and second portions of the epitaxial layer N.
Regarding claim 30, Hshieh discloses the integrated circuit of claim 28, wherein the metal-containing layer comprises TiN or TaN. See also the rejection of claim 26.
Claim Rejections - 35 U.S.C. § 103
5. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 9-16, 21, 25, 29, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Hshieh (US 7,863,685) in view of Zitouni et al. (US 2016/0064546).
Regarding claim 9, Hshieh discloses an integrated circuit, comprising:
a semiconductor substrate 105 (see fig. 2, fig. 6) having an n-type epitaxial layer 110 thereon;
a plurality of trench gate MOSFET cells over the semiconductor substrate 105 each including a corresponding one of a plurality of trench gates 120 in the epitaxial layer 110, each trench gate 120 having a trench dielectric layer 115 filled with a polysilicon gate 120 over a gate dielectric layer 115;
p-type body regions 125 in an upper portion of the epitaxial layer 110 between adjacent ones of the plurality of the trench gates 120, adjacent pairs of p-type body regions 125 having one of a plurality of surface regions 138 of the epitaxial layer 110 (forming part of JBS Schottky Diode shown in figs. 2, 6) located therebetween, top surfaces of the p-type body regions 125 coplanar with top surfaces of the surface regions 138 (of the epitaxial layer 110);
n-type source regions 130 at a top surface of the substrate within the body regions 125;
a metal-containing layer 140 located directly on the surface regions of the epitaxial layer 110; and
a metal layer 150 over the metal-containing layer 140 that electrically connects the p-type body regions 125, the n-type source regions 130 and the surface regions.
Hshieh fails to disclose:
The polysilicon gate over a lower polysilicon portion spaced apart from the poly silicon gate by a dielectric layer.
Zitouni discloses:
An integrated circuit comprising a plurality of trench gate MOSFET cells (see figs. 5, 7) comprising a plurality of trench gates 114-116, each trench gate 114-116 having a trench dielectric layer 214 & 503 filled with a polysilicon gate 125 over a lower polysilicon portion 130 spaced apart from the polysilicon gate 125 by a dielectric layer (upper part of dielectric layer 503 in figs. 2, 6, or inter-poly dielectric layer 212 shown in fig. 2; see also paras. 0043, 0049).
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Hshieh to have trench gates as that/those taught by Zitouni in order to effectively maintain the RESURF condition at the edge of the device while having the device in a cost-effective manner. See para. 0035 of Zitouni.
Regarding claim 10, Hshieh/Zitouni discloses the integrated circuit of claim 9, comprising all claimed limitations, as discussed above.
Hshieh fails to disclose wherein each of the trench gates has a double shield field plate.
Zitouni discloses:
An integrated circuit, shown in figs. 20-26, comprising a plurality of trench gate MOSFET cells 2008, 2010 comprising a plurality of trench gates (formed in trenches 115, 116, referenced in fig. 5) wherein each of the trench gates has a double shield field plate.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Hshieh so that each of the trench gates would have a double shield filed plate, as that taught by Zitouni, in order to enhance the electrical characteristics around the gate, thereby to increase the performance of the device. See para. 0035 of Zitouni.
Regarding claim 11, Hshieh/Zitouni discloses the integrated circuit of claim 9, wherein the metal-containing layer 140 comprises TiN or TaN. See col. 7, lines 46-53 of Hshieh.
Regarding claim 12, Hshieh/Zitouni discloses the integrated circuit of claim 9, wherein the substrate provide a drain for the trench gate MOSFET cells. See figs. 6, 7 of Hshieh.
Regarding claim 13, Hshieh/Zitouni discloses the integrated circuit of claim 9, comprising all claimed limitations, as discussed above.
Hshieh does not particularly disclose the integrated circuit further comprising an outer junction termination trench that provides a junction termination region which surrounds the active area.
Zitouni discloses a trench gate FET comprising an outer junction termination trench 118 that provides a junction termination region which surrounds the active area (comprising active trenches 114-116). See para. 0049, and fig. 5 of Zitouni.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify the invention of Hshieh to further include an outer junction termination trench, as that taught by Zitouni, in order to provide edge termination effects, thereby to prevent the edge cessl from being damaged by higher current density. See para. 0035 of Zitouni.
Regarding claim 14, Hshieh/Zitouni discloses the integrated circuit of claim 9, wherein each of the polysilicon gates includes a top recess (in which tungsten layer W 148 is formed, see fig. 6 of Hshieh).
Regarding claim 15, Hshieh/Zitouni discloses the integrated circuit of claim 9, wherein the metal-containing layer 140 extends through each of the n-type source regions and into a corresponding one of the p-type body regions. See figs. 6, 7 of Hshieh.
Regarding claim 16, Hshieh/Zitouni discloses the integrated circuit of claim 9, comprising all claimed limitations, as discussed above, except for wherein a thickness of the metal-containing layer 140 being within a range of about 10 nm to about 50 nm.
However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions or thickness of the claimed element, and a device having the claimed relative dimensions/thickness would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size of a component is generally recognized as being within the level of ordinary skill in the art.
It is to be expected that a change in size/thickness would be an unpatentable modification.
Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art, such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955).
The instant specification contains no disclosure of either the critical nature of the claimed dimensions/thickness or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (.In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).)
The claimed limitation regarding to the thickness of the meta-containing layer does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in size/thickness of a component. A change in size/thickness is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04).
Regarding claim 21, Hshieh/Zitouni discloses the integrated circuit of claim 9, wherein the p-type body regions 125 each extend without interruption between adjacent pairs of the trench gates 120. See figs. 6, 7 of Hshieh.
Regarding claim 25, 29, and 31, Hshieh/Zitouni discloses the integrated circuit comprising all claimed limitations. See the rejections of claims 10, 13.
Conclusion
7. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/Dao H Nguyen/
Primary Examiner, Art Unit 2818
February 21, 2026