DETAILED ACTION
Claim Rejections - 35 USC § 102
1. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
2. Claim(s) 1, 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Miyazaki (12238438).
With regard to claim 1, Miyazaki discloses a display device (for example, see figs. 1 - 3), comprising:
a display panel (a panel including a light-receiving pixel region R1, fig. 1 functioning as a display area, a dummy area R2, and peripheral area including regions 12, 14, 20, fig. 1) including a display area (a light-receiving pixel region R1, fig. 1 functioning as a display area) and a dummy area (R2) extending from the display area (R1);
a plurality of sub-pixels (P1) disposed in the display area (R1);
a plurality of dummy sub-pixels (P2) disposed in the dummy area (R2);
a pixel circuit (a pixel circuit including transistors; for example, see column 4, lines 21 - 25) disposed in the plurality of sub-pixels (P1); and
a pair of low potential power supply lines (referred to as “GN1” by examiner’s annotation shown in figs. 2 below; wherein the low potential power supply lines GN1 are ground voltage lines) disposed in the plurality of sub-pixels (P1); and
a pair of low potential power supply lines (referred to as “GN2” by examiner’s annotation shown in figs. 2 below; wherein the low potential power supply lines GN2 are ground voltage lines) disposed in the plurality of dummy sub-pixels (P2);
wherein in each of the plurality of sub-pixels (P1) and the plurality of dummy sub-pixels (P2), the pair of low potential power supply lines (GN1, GN2) are spaced apart from each other.
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With regard to claim 2, Miyazaki discloses the pixel circuit (a pixel circuit including transistors; for example, see column 4, lines 21 – 25, forming in the sub-pixels P1) is not disposed in the plurality of dummy sub-pixels P2).
Claim Rejections - 35 USC § 103
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki (12238438) in view of Jang et al. (11742358).
With regard to claim 3, Miyazaki do not clearly disclose first pad electrodes disposed on a front surface of the display panel and configured to transmit signals to the plurality of sub-pixels; second pad electrodes disposed on a rear surface of the display panel and connected to driving components for driving the plurality of sub-pixels; and side lines configured to electrically connect the first pad electrodes and second pad electrodes.
However, Jang et al. disclose first pad electrodes (121; for example, column 7, lines 66, 67) disposed on a front surface of the display panel (100) and inherently configured to transmit signals to the plurality of sub-pixels (131, 132, 133, fig. 1B); second pad electrodes (123; for example, column 10, lines 53, 54) disposed on a rear surface of the display panel (100) and connected to driving components (137, fig. 1B) for driving the plurality of sub-pixels (131, 132, 133, fig. 1B); and side lines (171, 172, 173) configured to electrically connect the first pad electrodes (121; for example, column 7, lines 66, 67) and second pad electrodes (123; for example, column 10, lines 53, 54). (for example, see column 6, line 67; and column 7, lines 1, 2, figs. 1B, 2).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Miyazaki’s device to have first pad electrodes disposed on a front surface of the display panel and configured to transmit signals to the plurality of sub-pixels; second pad electrodes disposed on a rear surface of the display panel and connected to driving components for driving the plurality of sub-pixels; and side lines configured to electrically connect the first pad electrodes and second pad electrodes as taught by Jang et al. in order to electrically connect the pixel driving circuit to the panel driver for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
5. Claims 4, 6, 7, 9, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki (12238438) in view of KIM et al. (20220130921).
With regard to claim 4, Miyazaki disclose light emitting elements (PD) disposed on (on the side or bottom or top side) the at least pair of low potential power supply lines (GN1) in the plurality of sub-pixels (P1) and disposed on (on the side or bottom or top side) the at least pair of low potential power supply lines (GN2) in the plurality of dummy sub-pixels (P2), but Miyazaki do not clearly disclose pixel electrodes disposed on the light emitting elements in the plurality of sub-pixels and the plurality of dummy sub-pixels, wherein the light emitting elements disposed in the plurality of sub-pixels are electrically connected to the pixel electrodes and the pixel circuit.
However, KIM et al. disclose light emitting elements (LEDs forming in the plurality of pixels) disposed on (on the bottom surface) the at least pair (270A, 270B) of low potential power supply lines in the plurality of sub-pixels and disposed on the at least pair (270C, 270D) of low potential power supply lines in the plurality of dummy sub-pixels; and pixel electrodes (191, 510) disposed on (on the bottom surface) the light emitting elements in the plurality of sub-pixels and the plurality of dummy sub-pixels, wherein the light emitting elements (LEDs) disposed in the plurality of sub-pixels are electrically connected to the pixel electrodes (191) and the pixel circuit (the pixel circuit including the semiconductor layer 130).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Miyazaki’s device to have pixel electrodes disposed on the light emitting elements in the plurality of sub-pixels and the plurality of dummy sub-pixels, wherein the light emitting elements disposed in the plurality of sub-pixels are electrically connected to the pixel electrodes and the pixel circuit as taught by KIM et al. in order to secure the potential efficiency of the devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 6, Miyazaki do not clearly disclose an insulating layer disposed between the light emitting elements and the pixel electrodes in the display area and the dummy area, wherein the light emitting elements disposed in the plurality of sub-pixels are exposed from the insulating layer and electrically connected to the pixel electrodes, and the light emitting elements disposed in the plurality of dummy sub-pixels are separated from the pixel electrodes by the insulating layer.
However, KIM et al. disclose an insulating layer (355) disposed between the light emitting elements (light emitting elements having emission layers 370, 375 forming in an array) and the pixel electrodes (191, 510) in the display area (DA) and the dummy area (MA), wherein the light emitting elements (light emitting elements having emission layers 370, 375 forming in an array) disposed in the plurality of sub-pixels are exposed from the insulating layer (355) and electrically connected to the pixel electrodes (191, 510), and the light emitting elements (light emitting elements having emission layers 375 forming in an array) disposed in the plurality of dummy sub-pixels are separated from the pixel electrodes (191) by the insulating layer (355).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Miyazaki’s device to have an insulating layer disposed between the light emitting elements and the pixel electrodes in the display area and the dummy area, wherein the light emitting elements disposed in the plurality of sub-pixels are exposed from the insulating layer and electrically connected to the pixel electrodes, and the light emitting elements disposed in the plurality of dummy sub-pixels are separated from the pixel electrodes by the insulating layer as taught by KIM et al. in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 7, Miyazaki disclose the light emitting elements (FD) disposed in the plurality of sub-pixels (P1) are electrically connected to the pair of low potential power supply lines (GN1) disposed in the plurality of sub-pixels (P1), and the light emitting elements (FD) disposed in the plurality of dummy sub-pixels (P2) are separated from the pair of low potential power supply lines (GN2) disposed in the plurality of dummy sub-pixels (P2).
With regard to claim 9, Miyazaki discloses light emitting elements (PD) disposed on (on the side or bottom or top side) the at least pair of low potential power supply lines (GN1) in the plurality of sub-pixels (P1), but Miyazaki do not clearly disclose pixel electrodes disposed on each of the plurality of sub-pixels and the plurality of dummy sub-pixels; wherein the pixel electrodes disposed in the plurality of sub-pixels are electrically connected to the light emitting elements.
However, KIM et al. disclose light emitting elements (light emitting elements having emission layers 370 forming in an array) disposed on (on the bottom surface) the at least pair (270A, 270B) of low potential power supply lines in the plurality of sub-pixels; and pixel electrodes (electrodes 191, 510 forming in the array) disposed on each of the plurality of sub-pixels and the plurality of dummy sub-pixels; wherein the pixel electrodes (electrodes 191 forming in the array) disposed in the plurality of sub-pixels are electrically connected to the light emitting elements (the light emitting elements having emission layers 370 forming in an array).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Miyazaki’s device to have pixel electrodes disposed on each of the plurality of sub-pixels and the plurality of dummy sub-pixels; wherein the pixel electrodes disposed in the plurality of sub-pixels are electrically connected to the light emitting elements as taught by KIM et al. in order to secure the potential efficiency of the devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
With regard to claim 10, Miyazaki discloses light emitting elements (PD) disposed on (on the side or bottom or top side) the at least pair of low potential power supply lines (GN1) in the plurality of sub-pixels (P1), but Miyazaki do not clearly disclose pixel electrodes disposed on each of the plurality of sub-pixels and the plurality of dummy sub-pixels; wherein the pixel electrodes disposed in the plurality of sub-pixels are electrically connected to the light emitting elements.
However, KIM et al. disclose a passivation layer (180) disposed on (on the bottom) the at least pair (270A, 270B, 270C, 270D) of low potential power supply lines in the display area (DA) and the dummy area (MA); contact electrodes (173, 175) disposed on (on the bottom) the passivation layer (180) in the plurality of sub-pixels; and dummy contact electrodes (referred to as “DA1” by examiner’s annotation shown in fig. 12 below) disposed on the passivation layer (180) in the plurality of dummy sub-pixels (the pixels forming dummy area MA).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Miyazaki’s device to have pixel electrodes disposed on each of the plurality of sub-pixels and the plurality of dummy sub-pixels; wherein the pixel electrodes disposed in the plurality of sub-pixels are electrically connected to the light emitting elements as taught by KIM et al. in order to secure the potential efficiency of the devices for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
6. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Miyazaki (12238438) in view of Park et al. (9711098).
With regard to claim 12, Miyazaki do not clearly disclose the display panel further includes a gate driving area at least partially overlapping the dummy area, wherein the display device further comprises a gate driver disposed in the gate driving area, and wherein at least a portion of the gate driver overlaps the dummy area.
However, Jang et al. disclose the display panel further includes a gate driving area (area having the gate driver 300, fig. 3A) at least partially overlapping the dummy area (an area including the dummy gate line DGL1, fig. 3A, gate driving area 300 and the dummy area having dummy gate line DGL1, connecting together as shown in fig. 3A, so they are overlapping together), wherein the display device further comprises a gate driver (300) disposed in the gate driving area, and wherein at least a portion of the gate driver (300) overlaps the dummy area (an area including the dummy gate line DGL1, fig. 3A, gate driving area 300 and the dummy area having dummy gate line DGL1, connecting together as shown in fig. 3A, so they are overlapping together).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Miyazaki’s device to have the display panel further includes a gate driving area at least partially overlapping the dummy area, wherein the display device further comprises a gate driver disposed in the gate driving area, and wherein at least a portion of the gate driver overlaps the dummy area as taught by Park et al. in order to enhance a high output efficiency from a gate signal applied to the gate line for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
7. Claims 5, 8, 11, 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 5, 8, 11, 13 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as the pixel electrodes disposed in the plurality of dummy sub-pixels are floating as recited in claim 5, each of the contact electrode and the dummy contact electrode is electrically connected to the at least pair of low potential power lines through a contact hole of the passivation layer as recited in claim 11, and the gate driver includes: a logic unit configured to generate a scan signal and output the scan signal to each of the plurality of sub-pixels; a power supply unit including a power supply line for applying a power supply voltage to the logic unit; and a clock unit including a plurality of clock signal lines for supplying a clock signal to the logic unit, wherein at least one the power supply unit and the clock unit is disposed between the display panel and the at least pair of low potential power supply lines in the dummy area as recited in claim 13.
Response to Amendment
8. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Note, the indicated allowability of claim 7 is withdrawn in view of the newly discovered reference(s) to claim 7 based on the amendment of claim 7.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TAN N TRAN/
Primary Examiner, Art Unit 2812