DETAILED ACTION
Notice of Pre-AIA
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
Acknowledgment is made of applicant’s Amendment, filed 23 December 2025. The changes and remarks disclosed therein have been considered.
No claims have been cancelled/added by Amendment. Therefore, claims 1-7 are pending in the application.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the feature “memory buffer” as recited in claim 1; the feature “host” as recited in claim 2, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 recites the limitation "wherein the controller" in claim 7. There is insufficient antecedent basis for this limitation in the claim..
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-7 are reject on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-10 of U.S Patent No. 10,192,591 B2 (‘591). Although the conflicting claims are not identical, they are not patentably distinct from each other because the instant application claims are obvious variants of the ‘591claims.
US Patent No. 10,192,591 B2
US Patent Application No. 2023/0335166 A1
1. A memory device comprising a register, a memory array, and a serial interface controller configured to receive and operate using a serial message to access the register that controls operation of the memory array by storing bits, the serial message having a format that comprises: a command field of the serial message configured to enable the serial interface controller to access the register; a register address field of the serial message immediately following the command field indicating an address of the register; and a data field of the serial message immediately following the register address field; wherein the serial interface controller is configured to receive the serial message, wherein the command field of the serial message comprises a command that the serial interface controller is configured to interpret as enabling write access to a special mode enable register of the memory device, wherein the address of the register is configured to identify the special mode enable register, wherein the data field of the serial message comprises data to be written into the special mode enable register that is configured, when written into the special mode enable register, to cause the memory device to operate according to a special mode of operation, wherein the special mode of operation comprises a one time programmable (OTP) access mode, a parameter page access mode, or a block lock access mode, or any combination thereof.
2. The memory device of claim 1, wherein the command field has a size of one byte, the register address has a size of one byte, and the data field has a size of one byte.
3. A memory device, comprising: a serial interface controller; a register coupled to the serial interface controller; and a memory array coupled to the serial interface controller, wherein the serial interface controller is configured to receive and operate using a serial message comprising a command field configured to enable the serial interface controller to access the register, a register address field immediately following the command field indicating an address of the register, and a data field immediately following the register address field to access the register that controls operation of the memory array by storing bits; wherein the serial interface controller is configured to write data of the data field into a special mode enable register to cause the memory device to operate according to a special mode of operation, wherein the special mode of operation comprises a one time programmable (OTP) access mode, a parameter page access mode, or a block lock access mode, or any combination thereof.
4. The memory device of claim 3, wherein the serial interface controller is configured to interpret a command in the command field as enabling write access to a special mode enable register of the memory device.
5. The memory device of claim 3, wherein the serial interface controller is configured to identify a special mode enable register based on the address in the register address field.
6. The memory device of claim 3, wherein the one time programmable (OTP) access mode is configured to enable the memory device to perform operations on nonvolatile memory of the memory device.
7. The memory device of claim 3, wherein the parameter page access mode is configured to enable the memory device to read parameter page contents from a page of memory of a NAND memory array of the memory device.
8. The memory device of claim 3, wherein the block lock access mode is configured to enable the memory device to prevent writing to a page of one time programmable (OTP) memory of the memory device.
9. The memory device of claim 8, wherein the one time programmable (OTP) memory comprises nonvolatile memory of the memory device.
10. The memory device of claim 3, wherein the serial interface controller is configured to interpret a first byte of the serial message as the command field, a second byte of the serial message as the register address field, and a third byte of the serial message as the data field.
1. A NAND flash memory device comprising: a controller; a memory buffer; and a NAND memory array comprising a one time programmable (OTP) block comprising a plurality of OTP pages, wherein an address of each of the plurality of OTP pages is associated with respective a flash lock enable bit configured to disallow writing to each of the plurality of OTP pages when the respective flash lock enable bit is set.
2. A memory device comprising: a memory array comprising a one time programmable (OTP) portion; and a serial controller configured to receive a first serial message from a host, wherein the serial message is configured to cause the memory device to permit access to the OTP portion.
3. The memory device of claim 2, comprising a special mode enable register that comprises an OTP enable portion, an OTP lock portion, or an OTP protect portion, or any combination thereof, wherein the memory device is configured to selectively permit access to the OTP portion based at least in part on data that is written to the special mode enable register in response to the first serial message.
4. The memory device of claim 3, wherein the serial controller is configured to receive a second serial message from the host, wherein the second serial message is configured to access the OTP portion after the first message has been received by the serial controller.
5. The memory device of claim 4, wherein the OTP portion comprises a plurality of OTP pages, wherein each of the plurality of OTP pages is associated with a respective page lock portion comprising at least one bit, wherein each page lock portion is configured to disallow writing to the respective one of the OTP pages when set, and wherein the serial controller is configured to be enable the memory device to write to one of the plurality of OTP pages upon receipt of the second serial message when the respective page lock portion associated with the one of the plurality of OTP pages is not set and after the first message has been received by the serial controller.
6. The memory device of claim 5, wherein the serial controller is configured to cause the memory device to set the page lock portion associated with the one of the plurality of OTP pages after writing to the one of the plurality of OTP pages a defined number of times.
7. The memory device of claim 3, wherein the controller is configured to communicate with the host over a serial peripheral interface (SPI) protocol.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(b) the invention was patented or described in a printed publication in this or a foreign country or in public use or on sale in this country, more than one year prior to the date of application for patent in the United States.
Claim 1 is rejected under pre-AIA 35 U.S.C. 102(b) as being anticipated by Lee et al (US 7,031,188 B2 hereinafter “Lee”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Lee, for example in Figs. 1-7, discloses a NAND flash memory device (e.g., The flash memory device 120 is a NAND flash memory device; in Figs. 1-2, 5 related in Figs. 3-4, 6-7) comprising: a controller (e.g., control 140; in Figs. 1, 5 related in Figs. 2-4, 6-7); a memory buffer (e.g., 207; in Fig. 2 related in Figs. 1, 3-7); and a NAND memory array (as discussed above; in Figs. 1-2, 5 related in Figs. 3-4, 6-7) comprising a one time programmable (OTP) block (e.g., OTP BLK; in Figs. 1-3, 5 related in Figs. 4, 6-7) comprising a plurality of OTP pages (e.g., pages P0-Pn; in Fig. 3 related in Figs. 1-2, 4-7), wherein an address of each of the plurality of OTP pages (via row address RA; in Figs. 2-3 related in Figs. 1, 4-7) is associated with a respective flash lock enable bit (via OTP_EN signal; in Figs. 2-4 related in Figs. 1, 5-7) configured to disallow writing to each of the plurality of OTP pages when the respective flash lock enable bit is set (e.g., OTP block locked/OTP block unlocked; in Fig. 3 related in Figs. 1-2, 4-7).
The structure in of the prior art (Lee et al) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation dose not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to pre-AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-7 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lee et al (US 7,031,188 B2 hereinafter “Lee_1”) in view of Lee et al (US 2006/0236204 A1 hereinafter “Lee_2”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 2, Lee_1, for example in Figs. 1-7, discloses a memory device (e.g., memory device 100; in Figs. 1, 5 related in Figs. 2-4, 6-7) comprising: a memory array (e.g., within memory flash 120; in Figs. 1-2, 5 related in Figs. 3-4, 6-7) comprising a one time programmable (OTP) portion (e.g., OTPBLK; in Figs. 1-3, 5 related in Figs. 4, 6-7); and a serial controller (e.g., block 140, the data inputted serially through the input/output IOi or IO0-IO15; in Figs. 1-5 related in Figs. 6-7) configured to receive a first command from a host (e.g., host command from host 160; in Figs. 1, 5 related in Figs. 2-4, 6-7), wherein the serial message is configured to cause the memory device to permit access to the OTP portion (via OTP_Access_CMD and OTP_EN; in Figs. 1-2, 5 related in Figs. 3-4, 6-7).
However, Lee is silent with regard to the serial controller configured to receive a first serial message from the host.
In the same field of endeavor, Lee_2, for example in Figs. 1-4, discloses the serial controller (e.g., SPI controller 210; in Fig. 2 related in Figs. 1, 3-4) configured to receive a first serial message from the host (e.g., SPI controller received an external data or command from SPI controller 260; in Fig. 2 related in Figs. 1, 3-4).
It would have been obvious at the time the invention was made to a person having ordinary skill in the art to modify the teaching of Lee_1 such as memory system having flash memory where a one-time programmable block is included (see for example in Figs. 1-7 of Lee_1) by incorporating the teaching of Lee_2 such as method device with serial transmission interface and error correction method for serial transmission interface (see for example in Fig. 1-4 of Lee_2), for the purpose of controlling the data transmission while the serial transmission interface accesses the memory (Lee_2, see abstract).
The structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation dose not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, the above Lee-1/Lee_2, combination discloses comprising a special mode enable register that comprises an OTP enable portion (via command register and control logic 208; in Fig. 2 related in Figs. 1, 3-7 of Lee_1 and also see in Figs. 1-4 of Lee_2, as discussed above), an OTP lock portion, or an OTP protect portion, or any combination thereof (see for example in Fig. 2 related in Figs. 1, 3-7 of Lee_1 and also see in Figs. 1-4 of Lee_2, as discussed above), wherein the memory device is configured to selectively permit access to the OTP portion based at least in part on data that is written to the special mode enable register in response to the first serial message (see for example in Fig. 2 related in Figs. 1, 3-7 of Lee_1 and also see in Fig. 2 related in Figs. 1, 3-4 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation dose not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, the above Lee_1/Lee_2, combination discloses wherein the serial controller is configured to receive a second serial message from the host (see for example in Fig. 2 related in Figs. 1, 3-7 of Lee_1 and also see in Fig. 2 related in Figs. 1, 3-4 of Lee_2, as discussed above), wherein the second serial message is configured to access the OTP portion after the first message has been received by the serial controller (see for example in Fig. 2 related in Figs. 1, 3-7 of Lee_1 and also see in Fig. 2 related in Figs. 1, 3-4 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation dose not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Lee_1/Lee_2, combination discloses wherein the OTP portion comprises a plurality of OTP pages, wherein each of the plurality of OTP pages is associated with a Page 3 respective page lock portion comprising at least one bit (see for example in Figs. 2-3 related in Figs. 1, 4-7 of Lee_1 and also see in Fig. 2 related in Figs. 1, 3-4 of Lee_2, as discussed above), wherein each page lock portion is configured to disallow writing to the respective one of the OTP pages when set, and wherein the serial controller is configured to be enable the memory device to write to one of the plurality of OTP pages upon receipt of the second serial message when the respective page lock portion associated with the one of the plurality of OTP pages is not set and after the first message has been received by the serial controller (see for example in Figs. 2-3 related in Figs. 1, 4-7 of Lee_1 and also see in Fig. 2 related in Figs. 1, 3-4 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation dose not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Lee_1/Lee_2, combination discloses wherein the serial controller is configured to cause the memory device to set the page lock portion associated with the one of the plurality of OTP pages after writing to the one of the plurality of OTP pages a defined number of times (see for example in Figs. 2-3 related in Figs. 1, 4-7 of Lee_1 and also see in Fig. 2 related in Figs. 1, 3-4 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation dose not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Lee_1/Lee_2, combination discloses wherein the controller is configured to communicate with the host over a serial peripheral interface (SPI) protocol (see for example in Figs. 2-3 related in Figs. 1, 4-7 of Lee_1 and also see in Fig. 2 related in Figs. 1, 3-4 of Lee_2, as discussed above). Also, the structure in of the prior art (Lee_1 and Lee_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation dose not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Applicant are reminded that when presenting amendments to claims. In order to be fully responsive, an attempt should be made to point out the patentable novelty (see MPEP 714.04). Additionally, Applicant should point out where and/or how the originally filed disclosure supports the amendment(s) (see MPEP 2163 II A).
Response to Arguments
Applicant's arguments filed 23 December 2025 have been fully considered but they are not persuasive.
Applicant argues that the reference of Lee does not disclose “an address of each of the plurality of OTP pages is associated with a respective flash lock enable bit” as recited in claim 1 (see remarks file 23 December 2025, page 1).
In response to applicant’s argument that the reference of Lee discloses an address of each of the plurality of OTP pages (via row address RA; in Figs. 1-3, 5 related in Figs. 4, 6-7 of Lee) with a respective flash lock enable bit (via bit 0 0 as locked or bit 1 X X 1 as unlocked; in Fig. 3 related in Figs. 1-2, 4-7 of Lee) as recited in claim 1 (see remarks file 23 December 2025, page 1).
Applicant’s arguments, see remarks, filed 23 December 2025, with respect to the rejection(s) of claim(s) 2-7 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Lee et al (US 2006/0236204 A1 hereinafter “Lee_2”).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THA-O H BUI whose telephone number is (571)270-7357. The examiner can normally be reached M-F 7:00AM - 3:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALEXANDER SOFOCLEOUS can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THA-O H BUI/Primary Examiner, Art Unit 2825 03/18/2026