DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5,6,11,12,15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US20190081069A1) in view of Shin et al. (US10032787B2).
Regarding claim 1, Fig. 2 of Lu teaches a semiconductor memory device comprising:
a stack 242 (para.0059) comprising interlayer insulating layers 236 (para.0059) and conductive patterns 234/238 (para.0059), which are alternately stacked;
a source conductive pattern 250 (para.0062) on the stack 242; and
vertical structures 230 (para.0060) provided to penetrate the stack 242, the vertical structures 230 being connected to the source conductive pattern 250,
wherein each of the vertical structures 230 comprises:
a vertical channel pattern 228 (para.0060);
a data storage pattern 229 (para.0060) enclosing an outer side surface of the vertical channel pattern 228;
the vertical conductive pillar 251 being connecting the vertical channel pattern 228 to the source conductive pattern 250.
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Lu does not teach wherein a vertical insulating pillar is in the vertical channel pattern; and
a vertical conductive pillar disposed between the vertical insulating pillar and the source conductive pattern.
Figs. 10A and 10B of Shin teach a three-dimensional semiconductor memory device a vertical structure VS that includes a first semiconductor pattern SP1 and a second semiconductor pattern SP2; and an insulating material 300 fills an inner region defined by the first semiconductor pattern SP1 (col.8, lines 3-6,11-13). Fig.10A also discloses wherein contact pads D are disposed on upper ends of the vertical structures VS to be connected to the bit line contact plug BPLG (col.10, lines 51-53); wherein contact pads are disposed between the insulating material 300 and the bit lines BL.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the insulating material of Shin in the teachings of Lu wherein the contact pad is disposed between the insulating material and the bit lines in order for insulating material to provide insulation and the contact pad to provide electrical connection between the bit lines and the vertical structures (Shin, [col.10, lines 51-53]).
Regarding claim 2, Lu further teaches the semiconductor memory device of claim 1, wherein a uppermost conductive pattern 238 (para.0062) of the conductive patterns 234/238 (para.0059) is provided to enclose the vertical conductive pillar 251 (para.0062, epitaxial layer 251 can be epitaxially grown from a semiconductor layer 244. Layer 244 can be partially doped or fully doped by p-type or n-type dopants) and the uppermost conductive pattern 238 is adjacent to the source conductive pattern 250 (para.0062).
Regarding claim 3, Lu further teaches the semiconductor memory device of claim 1, wherein the vertical conductive pillar 251 (para.0062, epitaxial layer 251 can be epitaxially grown from a semiconductor layer 244. Layer 244 can be partially doped or fully doped by p-type or n-type dopants) comprises a doped semiconductor material.
Regarding claim 5, Lu further teaches the semiconductor memory device of claim 2, wherein a portion of the data storage pattern 229 (para.0060) encloses each of the vertical portions.
Regarding claim 6, the combination of Lu and Shin further teaches the semiconductor memory device of claim 1, wherein the conductive patterns 234/238 (para.0059) comprise (i) a first erase gate pattern 238 (para.0061) that is most adjacent to the source conductive pattern 250 (para.0062) and (ii) a second erase gate pattern 234 (para.0059, see annotated Fig.2) that is provided on the first erase gate pattern 238, and
an interface between the vertical conductive pillar and the vertical insulating pillar 300 (col.8, lines11-12) is located at a level between top and bottom surfaces of the second erase gate pattern 234.
Regarding claim 11, Lu further teaches the semiconductor memory device of claim 1, wherein the source conductive pattern 250 (para.0062) is in contact with a top surface of the uppermost interlayer insulating layer 236 (para.0059) of the interlayer insulating layers 236 (para.0059) of the stack 242 (para.0059) and a top surface of the data storage pattern 229 (para.0060).
Regarding claim 12, Fig. 2 of Lu teaches a semiconductor memory device comprising:
a substrate 202 (para.0071); a peripheral circuit structure 222 (para.0068) comprising (i) peripheral circuits 214 () that are integrated on the substrate 202 and (ii) first bonding pads 220 (para.0070) that are connected to the peripheral circuits 222; and
a cell array structure 262 (para.0071) comprising second bonding pads 224 (para.0068) that are bonded to the first bonding pads 220,
wherein the cell array structure 262 comprises:
a stack 242 (para.0059) comprising interlayer insulating layers 236 (para.0059) and conductive patterns 234 (para.0059), the interlayer insulating layers 236 and the conductive patterns 234 being alternately stacked;
a source conductive pattern 250 (para.0062) on the stack 242; and
vertical structures 230 (para.0060) provided to penetrate the stack 242 and connected to the source conductive pattern 250,
wherein each of the vertical structures 230 comprises:
a vertical channel pattern 228 (para.0060),
a data storage pattern 229 (para.0060) enclosing an outer side surface of the vertical channel pattern 228,
wherein a uppermost conductive pattern 238 (para.0062) of the conductive patterns 234 encloses the vertical conductive pillar 251, and
wherein the uppermost conductive pattern 234 is adjacent to the source conductive pattern 250.
Lu does not teach a vertical insulating pillar in the vertical channel pattern, and
a vertical conductive pillar disposed between the vertical insulating pillar and the source conductive pattern to connect the vertical channel pattern to the source conductive pattern.
Figs. 10A and 10B of Shin teach a three-dimensional semiconductor memory device a vertical structure VS that includes a first semiconductor pattern SP1 and a second semiconductor pattern SP2; and an insulating material 300 fills an inner region defined by the first semiconductor pattern SP1 (col.8, lines 3-6,11-13). Fig.10A also discloses wherein contact pads D are disposed on upper ends of the vertical structures VS to be connected to the bit line contact plug BPLG (col.10, lines 51-53); wherein contact pads are disposed between the insulating material 300 and the bit lines BL.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the insulating material of Shin in the teachings of Lu wherein the contact pad is disposed between the insulating material and the bit lines in order for insulating material to provide insulation and the contact pad to provide electrical connection between the bit lines and the vertical structures (Shin, [col.10, lines 51-53]).
Regarding claim 15, Lu further teaches the semiconductor memory device of claim 12, wherein the conductive patterns comprise a first erase gate pattern 238 (para.0061) that is most adjacent to the source conductive pattern 250 (para.0062), and a second erase gate pattern (see annotated Fig.2) that is provided on the first erase gate pattern 238, and a bottom surface of the vertical conductive pillar 251 (para.0062) is located at a level between top and bottom surfaces of the second erase gate pattern.
Regarding claim 18, Lu further teaches the semiconductor memory device of claim 12, further comprising bit lines 226 (para.0068) (i) that are extended in a specific direction to cross the stack and (ii) that are connected to the vertical channel patterns 228 (para.0060) of the vertical structures 230 (para.0060), wherein the bit lines 226 are adjacent to the peripheral circuit structure 222 (para.0057).
Claims 4,7,13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US20190081069A1) in view of Shin et al. (US10032787B2) and in further view of MIZUTANI et al. (US20210035965A1).
Regarding claim 4, Lu teaches the semiconductor memory device of claim 1, wherein: the source conductive pattern 250 (para.0062) comprises (i) a horizontal portion that is parallel to the stack 242 (para.0059).
Lu does not teach protruding portions that protrude from the horizontal portion, and the vertical channel pattern and the vertical conductive pillar are in contact with each of the vertical portions.
Fig. 19C of MIZUTANI teaches a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate and a source layer is formed directly on the distal end each of the vertical semiconductor channels; the source layer 18 comprises vertically protruding portions 18P that protrude through the horizontal plane including the horizontal interface between the source layer 18 (para.0140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include MIZUTANI’s source layer 18 that comprises vertically protruding portions 18P that protrude through the horizontal plane including the horizontal interface between the source layer 18 and the vertical semiconductor channels 60 because it provides contacts to the sidewalls of the vertical semiconductor channels 60 (MIZUTANI, [para.0140]).
Regarding claim 7, Lu does not teach wherein the source conductive pattern comprises a metallic material.
Fig.27A of MIZUTANI teaches a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate and a source layer comprising a metallic source layer 240 can be formed by depositing at least one metallic material on the distal end of each of the vertical semiconductor channels 60 and by patterning the at least one metallic material (para.0213).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the source layer of MIZUTANI in the teachings of Lu metallic materials are known to be better conductors than doped semiconductor materials.
Regarding claim 13, Lu teaches the semiconductor memory device of claim 12, wherein the vertical conductive pillar 251 (para.0062, epitaxial layer 251 can be epitaxially grown from a semiconductor layer 244. Layer 244 can be partially doped or fully doped by p-type or n-type dopants) comprises a doped semiconductor material.
Lu does not teach the source conductive pattern comprises a metal material.
Fig.27A of MIZUTANI teaches a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate and a source layer comprising a metallic source layer 240 can be formed by depositing at least one metallic material on the distal end of each of the vertical semiconductor channels 60 and by patterning the at least one metallic material (para.0213).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the source layer of MIZUTANI in the teachings of Lu because metallic materials are known to be better conductors than doped semiconductor materials.
Regarding claim 16, Lu further teaches the semiconductor memory device of claim 12, wherein the source conductive pattern 250 (para.0062) comprises (i) a horizontal portion that is parallel to the stack 242 (para.0059).
Lu does not teach protruding portions that vertically protrude from the horizontal portion and that are connected to the vertical conductive pillar.
Fig. 19C of MIZUTANI teaches a three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a carrier substrate and a source layer is formed directly on the distal end each of the vertical semiconductor channels; the source layer 18 comprises vertically protruding portions 18P that protrude through the horizontal plane including the horizontal interface between the source layer 18 (para.0140).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include MIZUTANI’s source layer 18 that comprises vertically protruding portions 18P that protrude through the horizontal plane including the horizontal interface between the source layer 18 and the vertical semiconductor channels 60 because it provides contacts to the sidewalls of the vertical semiconductor channels 60 (MIZUTANI, [para.0140]).
Claims 8-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US20190081069A1) in view of Shin et al. (US10032787B2) and in further view of Kai et al. (US10629616B1).
Regarding claim 8, Lu does not teach wherein the semiconductor memory device of claim 1, further comprising an insulating reflection layer between the source conductive pattern and a uppermost interlayer insulating layer of the interlayer insulating layers.
Fig. 14 of Kai teaches a contact level dielectric layer 73 can be formed over the alternating stack (32, 42) of insulating layer 32 and sacrificial material layers 42, and over the memory stack structures 55 and the support pillar structures 20. The contact level dielectric layer 73 is disposed between the uppermost insulating layer 32 and the bit lines 98.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the contact level dielectric layer 73 of Kai in the teachings of Lu because the contact level dielectric layer 73 can be used as a chemical mechanical planarization (CMP) stopping layer (Kai, [col.17, lines 23-24]).
Regarding claim 9, Kai further teaches the semiconductor memory device of claim 8, wherein the insulating reflection layer 73 (col.14, lines 32-33, the contact level dielectric layer 73 can include silicon oxide) is formed of an insulating material different from the interlayer insulating layers 32 (col.15, lines 18-19, wherein insulating layers 32 and the stepped dielectric material portion 65 can be selected from silicon oxide and dielectric metal oxides).
Regarding claim 10, Kai further teaches the semiconductor memory device of claim 8, wherein a portion of the insulating reflection layer 73 (col.14, lines 32-33 is disposed between a top surface of the data storage pattern 23 (col.23, line 60) and the source conductive pattern 98 (col.17, line 57).
Regarding claim 17, Lu does not teach wherein the semiconductor memory device of claim 12, further comprising an insulating reflection layer between the source conductive pattern and the uppermost one of the interlayer insulating layers.
Fig. 14 of Kai teaches a contact level dielectric layer 73 can be formed over the alternating stack (32, 42) of insulating layer 32 and sacrificial material layers 42, and over the memory stack structures 55 and the support pillar structures 20. The contact level dielectric layer 73 is disposed between the uppermost insulating layer 32 and the bit lines 98.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the contact level dielectric layer 73 of Kai in the teachings of Lu because the contact level dielectric layer 73 can be used as a chemical mechanical planarization (CMP) stopping layer (Kai, [col.17, lines 23-24]).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US20190081069A1) in view of Shin et al. (US10032787B2) and in further view of Jung et al. (US20210202458A1).
Regarding claim 19, Lu further teaches the semiconductor memory device of claim 12, further comprising: a lower insulating layer 210/212/218 (para.0057) covering the source conductive pattern 250 (para.0062);
Lu does not expressly disclose an input/output plug laterally spaced apart from the stack and the source conductive pattern and coupled to one of the second bonding pads; and an input/output pad disposed on the lower insulating layer and connected to the input/output plug.
Fig.3 of Jung teaches a semiconductor device that includes a first chip structure CS1 and a second chip structure CS2; the second chip structure CS2 may further include wiring structures 160, 162, 164, and 166 in the capping insulating layer 120c. The wiring structures 160, 162, 164, and 166 may include a bitline structure 160, a gate wiring structure 162, a source wiring structure 164, and an input/output wiring structure 166. The input/output wiring structure 166 may include an input/output contact plug 166a and an input/output connection pattern 166b for electrically connecting the input/output contact plug 166a and the second circuit junction pads 170c. The input/output contact plug 166a may extend from a portion disposed in the second insulating structure 120 into the third material layer 177b of the conductive pad 175b (para.0065).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the input/output wiring structure of Jung in the teachings of Lu, as modified by Shin, in order to provide electrical connection between the input/output contact plug 166a and any one of the second circuit junction pads 170c of the second junction pads 170 (Jung, [para.0155]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (US20190081069A1) in view of Shin et al. (US10032787B2).
Regarding claim 20, Fig. 2 of Lu teaches an electronic system comprising: a semiconductor memory device comprising a substrate 202 (para.0071), a peripheral circuit structure 222 (para.0068) on the substrate 202, and a cell array structure 262 (para.0071) on the peripheral circuit structure 222; wherein the cell array structure 262 comprises: a stack 242 (para.0059) comprising interlayer insulating layers 236 (para.0059) and conductive patterns 234 (para.0059), the interlayer insulating layers 236 and the conductive patterns 234 being alternately stacked; a source conductive pattern 250 (para.0062) on the stack 242; and vertical structures 230 (para.0060) provided to penetrate the stack 242 and connected to the source conductive pattern 250, wherein each of the vertical structures 230 comprises: a vertical channel pattern 228 (para.0060); a data storage pattern 229 (para.0060) enclosing an outer side surface of the vertical channel pattern 228;.
Lu does not teach a controller that is electrically connected to the semiconductor memory device through an input/output pad, the controller being used to control the semiconductor memory device and a vertical insulating pillar in the vertical channel pattern; and a vertical conductive pillar disposed between the vertical insulating pillar and the source conductive pattern to connect the vertical channel pattern to the source conductive pattern
Figs. 10A and 10B of Shin teach a three-dimensional semiconductor memory device a vertical structure VS that includes a first semiconductor pattern SP1 and a second semiconductor pattern SP2; and an insulating material 300 fills an inner region defined by the first semiconductor pattern SP1 (col.8, lines 3-6,11-13). Fig.10A also discloses wherein contact pads D are disposed on upper ends of the vertical structures VS to be connected to the bit line contact plug BPLG (col.10, lines 51-53); wherein contact pads are disposed between the insulating material 300 and the bit lines BL;
wherein Fig.25 teaches memory system 1100 that includes a controller 1110 and an input/output device (I/O device) 1120 such as a keypad, a keyboard, and a display device (col.19, lines 38-40). The controller 1110 includes at least one of a microprocessor, a digital signal processor, a micro controller, and the other processing devices capable of performing similar functions thereto. The memory 1130 may serve to store commands executed by the controller 1110. The I/O device 1120 may receive data or a signal from the outside of the memory system 1100 or output data or a signal to the outside of the memory system 1100 (col.19, lines 43-50).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Shin’s controller and the input/output device in the teachings of Lu because the memory 1130 may serve to store commands executed by the controller 1110 and the I/O device 1120 may receive data or a signal from the outside of the memory system 1100 or output data or a signal to the outside of the memory system 1100 and to incorporate the insulating material 300 of Shin in the teachings of Lu wherein the contact pad is disposed between the insulating material and the bit lines in order for insulating material to provide insulation and the contact pad to provide electrical connection between the bit lines and the vertical structures (Shin, [col.10, lines 51-53, col.19, lines 46-50]).
Allowable Subject Matter
Claim 14 is allowed.
The following is an examiner’s statement of reasons for the indication of allowable subject matter:
Regarding claim 14, prior art fails to disclose the combination of limitations including “wherein a top surface of the vertical conductive pillar is located at a level that (i) is lower than a top surface of the data storage pattern and (ii) is higher than a top surface of the uppermost one of the conductive patterns adjacent to the source conductive pattern”.
Conclusion
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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