DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 8 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 8 recites “one or more of the first insulating substrate and the second insulating substrate further includes a protrusion protruding from a portion of a chamber”. Here, it is unclear whether the claimed “chamber” in claim 8 is intended to refer to the previously recited chamber in claim 2. For examination purposes, the Examiner will interpret the chamber of claim 8 to be a different chamber than the chamber recited in claim 2 because the chambers are separately recited in a manner such that they would be referring to different elements of the semiconductor device.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 6-10 are rejected under 35 U.S.C. 103 as being unpatentable over Funakoshi et al. (“Funakoshi” US 2008/0224303) and Stegmeier (US 2018/0301392).
Regarding claim 1, Funakoshi discloses a power module (Figure 1) comprising:
at least one insulating substrate (lower insulating substrate 5/7/9/10/11); and
at least one semiconductor chip (1) disposed on the at least one insulating substrate (5/7/9/10/11, see Figure 1),
wherein the at least one insulating substrate (5/7/9/10/11) includes:
an insulating layer (9, ceramic, AlN, substrate); and
a metal layer (copper sheet 10) disposed between the at least one semiconductor chip (1) and the insulating layer (9, see Figure 1), forming electrical connection with the at least one semiconductor chip (10) through a circuit pattern (solder joining material 7),
wherein the power module further includes one or more of a signal lead (signal G/28, see Figure 3B and para. [0046]) and a power lead (P/26 in Figure 3A), and
wherein the one or more of the signal lead (28) and the power lead (26) are bonded and electrically connected to the metal layer (10, power lead 26 is directly contacting, thus is bonded and electrically connected to, the metal layer 10, see Figure 1, and the signal lead 28 is bonded and electrically connected to the metal layer 10 through solder layers and the semiconductor chip between the signal lead 28 and the metal layer 10, see Figure 1, here, “bonded to” and “electrically connected to” does not require direct physical contact and allows for interstitial electrical connection and/or bonding elements).
Funakoshi does not disclose that the metal layer has a sealed cavity with fluid filled therein.
Stegmeier discloses in Figure 2, however, a metal layer (180, between power component 10 and ceramic substrate 90, see Figure 2) having a sealed cavity with fluid filled therein (cooling fluid flows in the heat pipe/metal layer 180, see para. [0025], from the open porosity of the metal contact piece 70 that comprises the heat pipe/metal layer 180, see also Figure 2 which shows the heat pipe/metal layer 180 being sealed, and para. [0025] discloses a fluid-tight metal enclosure 182).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Stegmeier into the teachings of Funakoshi to include the metal layer (heat pipe 180) as disclosed by Stegmeier for the metal layer (10) of Funakoshi for the purpose of utilizing additional heat dissipation means by evaporation and condensation of the metal plated heat pipe/fluid chamber of Stegmeier (Stegmeier, para. [0026]).
Regarding claim 2, Stegmeier discloses wherein the metal layer (180) includes:
a chamber (plated exterior 182 and open contact piece 70 having spaced formed therein, i.e. “pores”, of the heat pipe 180) forming the cavity (the chamber 182 constitutes exterior walls of the heat pipe 180, thus forms the inside cavity of the heat pipe 180); and
an inlet (inlets are formed in/on the surface of the open pore contact piece 70 of the heat pipe 180, see para. [0025], [0011]) formed at at least one side of the chamber (70/182, since the inlets are formed throughout the contact piece 70, see Figure 3 and para. [0025], the inlets would be formed at at least one side of the chamber 70/182) and closed (since the open pore contact piece 70 is closed within the plated exterior 182, i.e. part of the chamber, of the heat pipe 180, the inlets/pores are thereby closed).
Regarding claim 3, Stegmeier discloses wherein the chamber (70/182) extends to partially vertically overlap the insulating layer (100, see Figure 2), and the inlet (inlets of the open contact piece 70 of the chamber, para. [0011]) is disposed at a portion of the chamber (70/182) located outside a vertical overlap area between the chamber (70/182) and the insulating layer (100, since the inlets are formed on all surfaces of the open core contact piece 70 and a portion of the open pore contact piece 70 does not overlap with the insulating layer 100, see Figure 2 and para. [0011], at least one of the inlets/pores would be disposed such that it does not vertically overlap the region in which the chamber overlaps the insulating layer 100).
Regarding claim 6, Funakoshi discloses wherein the at least one insulating substrate (5/7/9/10/11) further includes a heat dissipation layer (copper sheet 11, which has heat dissipation capabilities) spaced from the metal layer (10) by the insulating layer (9, see Figure 1).
Regarding claim 7, Funakoshi discloses wherein the at least one insulating substrate (5/7/9/10/11) includes a first insulating substrate (5/7/9/10/11) and a second insulating substrate (18/19/20/21) which are spaced from and opposite to each other in a vertical direction (see Figure 1) with the at least one semiconductor chip (1) therebetween (see stacked configuration in Figure 1, with semiconductor chip 1 between the upper and lower substrates).
Regarding claim 8, Funakoshi discloses wherein one or more of the first insulating substrate (5/7/9/10/11) and the second insulating substrate (18/19/20/21) further includes a protrusion (spacer and joining material 5/7 of first/lower insulating substrate) protruding from a portion of a chamber (here, the chamber is separately recited from the chamber of the metal layer, thus is interpreted to refer to another chamber, which here is interpreted to be the enclosed space formed by the encapsulant/resin 25 and the casing 14/24, and the protrusions, i.e. the spaces and joining materials, protrude from portions within the chamber), which faces a power pad (3) of the at least one semiconductor chip (1), toward the at least one semiconductor chip (1) in a vertical direction (see Figure 1) to further space the insulating layer (9) apart from the at least one semiconductor chip (1) as much as a protruding thickness of the protrusion (5/7, see Figure 1, see also. para. [0036] which discloses that the spacer 5 serves to separate the electrodes/leads of the chip to prevent electrical discharge).
Regarding claim 9, Funakoshi discloses wherein the protrusion (5/7) is bonded to the power pad (3, electrically connected to power terminal 26, thus is considered a power pad) of the at least one semiconductor chip (1).
Regarding claim 10, Funakoshi discloses wherein the signal lead (28) is connected to a signal pad (16) of the at least one semiconductor chip (1) through a conductor (the conductor here, facilitating electrical connection, is the copper sheet 20 of the upper substrate).
Response to Arguments
Applicant’s amendments to claims 2-3 and 8, filed February 3 2026, with respect to the 112 rejections of claims 2-5 and 8 have been fully considered and overcome the 112 rejections. Applicant has also cancelled claims 4-5, thus the 112 rejection for claims 4-5 is moot. The 112 rejections of claims 2-3 and 8 has been withdrawn.
Applicant’s amendment to claim 1 overcomes the objection to claim 1. The objection to claim 1 has been withdrawn.
Applicant’s arguments regarding the combination of Stegmeier and Funakoshi is not persuasive. Applicant argues that because the heat pipe 180 of Stegmeier is an element dedicated to providing heat dissipation means to the device and does not serve circuit connection functions, one of ordinary skill in the art would not be motivated to combine Funakoshi and Stegmeier. The Examiner respectfully disagrees. The incorporation of Stegmeier’s heat pipe 180 into the metal layer 10 of Funakoshi is to teach a metal layer having a sealed cavity with fluid filled therein, not to provide electrical connection with the semiconductor chip, since Funakoshi teaches electrical connection with its metal layer 10. The Examiner has also provided a motivation to combine such teachings, specifically that the heat pipe 180 of Stegmeier in place of the metal layer 10 of Funakoshi would enhance heat dissipation properties. Further, the combination of Stegmeier’s heat pipe 180 into the metal layer 10 of Funakoshi would still result in a metal layer having electrical connection with the semiconductor chip, since Stegmeier’s heat pipe is plated (182) with a metallic, therefor electrically conductive, material. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899