CTFR 18/134,919 CTFR 86596 DETAILED ACTION Remarks Applicant presents a communication dated 13 February 2026 responsive to the 13 November 2025 non-final Office action (the “Previous Action”). Claims 1-2, 8-9 and 15 are amended. New claims 21-24 are also added. Claim 1-24 are pending. Claims 1, 8 and 15 are the independent claims. Any unpersuasive arguments are addressed in the “Response to Arguments” section below. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 37 C.F.R. § 1.121 Applicant’s claim listing is not compliant with 37 C.F.R. § 1.121, which requires all added claim language to be shown via underlining and all cancelled subject matter to be shown via strike-through or double bracketing. In particular, Applicant underlines the word “computational” in the phrase “computational graph nodes” in line 5 of claim 15 when that word already appeared in the claim and is therefore not added subject matter The claims are nonetheless examined in the interests of compact prosecution. Examiner Notes Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Applicant argues with respect to claim 1 that Meixner discloses concatenation of kernels as opposed to combining nodes from across stages of a computational graph. (Remarks. p. 7 last par. – p. 8 par. 1). Examiner respectfully disagrees and submits that at least the combined producer and consumer nodes in the graph taught by Meixner comprise stages because each consumer kernel “represent[s] the next stage/operation” in the pipeline/DAG.” (Meixner, par. [0037]). The graph is also a computational graph because kernels provide tasks such as convolutions and matrix multiply. (Meixne at par., [0093]). Applicant argues that McGuire does not disclose execution of the computational graph by differently architecture processors because McGuire discloses that certain kernels are target a specific type of processing element or are more efficient when executed on a particular processing element. (Remarks, p. 8 last par. – p. 9 par. 1). Examiner respectfully disagrees and points out that while certain kernels of McGuire may target a specific processing element “in some embodiments” or be more efficient when executing on a particular processing element, this does not change the fact that McGuire also discloses processing elements that “may not have the same architecture” executing programs compiled from the graph. (McGuire, pars. [0011], [0047] and [0054]). Or the fact that McGuire “generates multiple copies of compiled programs, one for each type of processing element.” McGuire accordingly teaches both heterogeneous compilation and execution on differently architecture processors as claimed. Note too that the “for execution…” language only appears to be directed to an intended use of the compiled graph. “Claim scope is not limited by claim language that suggests or makes optional but does not require steps to be performed, or by claim language that does not limit a claim to a particular structure.” M.P.E.P. § 2111.04(I). Applicant argues with respect to claim 2 that this claim distinguishes from the applied references because it recites that the threshold for partitioning is equal to or below a threshold and that “Examiner agrees that the threshold is limited by the capability of the hardware.” (Remarks, p. 9 par. 1). Examiner believes that Applicant is suggesting that because Meixner partitions the graph so that all kernels are within a memory size threshold, Meixner does not so partition the graph “to limit compilation times” as claimed. Examiner respectfully points out, however, that the “to limit compilation times” language only appears to refer to express the intended result of the already recited step of partitioning the graph so that the kernels are at or below a threshold size. The language is non-limiting and given no patentable weight. See M.P.E.P. § 2111.04(I). The language is treated as limiting below solely in the interests of compact prosecution. Applicant’s arguments with respect to the remaining claims by virtue of their dependence from claim 1, similarity with claim 1 or 2 or dependence from a similar claim are unpersuasive for the same reason. Applicant argues that new claims 21-24 distinguish from Meixner and McGuire as well, though without any specific analysis. (Remarks, p. 10). As to claim 23, examiner respectfully disagrees for the reasons set forth below. As to the other new claims, Applicant’s arguments are moot in view of the new ground(s) of rejection necessitated by Applicant’s amendments. Claim Rejections - 35 USC § 112 07-30-01 AIA 10. The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. 07-31-01 Claims 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. As to claim 21 , the claim recites that …wherein the one or more instances of combining nodes across stages of the computational graph and, then, backward traversal thereof, results in selective kernel generation There is insufficient support in the originally filed specification for these features. For example, per paragraphs [0058-0060], the graph is traversed backwards to identify materialized nodes and it is these nodes that are combined to form kernels. That is to say backwards traversal is performed before combining nodes. There is no support for combining nodes and “then” performing backward traversal as claimed. 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As to claim 22 , the claim refers to “the” backward traversal. There is insufficient antecedent basis for these limitations in the claim and it is unclear to which previously recited element, if any, the claim is referring. For the purposes of examination, claim 22 will be construed as additionally requiring that the circuitry of claim 1 is configured to perform backward traversal and identification of materialized nodes and nodes that have not been materialized. 07-36 AIA The following is a quotation of 35 U.S.C. 112(d): (d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph: Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers. 07-36-01 AIA Claim 23 rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements. As to claim 23 , the claim recites: [t]he one or more processors of claim 1, wherein the one or more processor-executable kernels are to be generated based, at least in part, on the one or more instances of the combined nodes from across the stages of the computational graph comprising combining two or more computational graph nodes across stages of the computational graph to result in common subexpression elimination and/or dead code elimination. The “to result in common subexpression elimination and/or dead code elimination” only describes an intended use of the other limitations recited. It therefore does not limit the claim because claim language that does not require a step to be performed or limit the claim to a particular structure does not limit claim scope. See M.P.E.P. § 2111.04. And the rest of the limitations of the claim are already recited by claim 1. Claim 23 accordingly does not further limit claim 1. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1, 3-8, 10-20 and 23 are rejected under 35 U.S.C. 103 as unpatentable over Meixner et al. (US 2017/0249716) (art of record – hereinafter Meixner) in view of McGuire (US 2007/0294663) (art of record – hereinafter McGuire). As to claim 1 , Meixner discloses one or more processors, comprising : one or more circuits (e.g., Meixner, par. [0159]: embodiments of the invention may include various processes as set forth above. The processes may be embodied in machine-readable instructions. The instructions can cause a processor to perform certain processes) to: combine across stages of a computational graph two or more computational graph nodes of the computational graph in one or more instances across the computational graph; (e.g., Meixner, par. [0093]: a directed acyclic graph “(DAG)”; par. [0102]: a DAG of kernels; abstract: at least one of the kernels is more computationally intensive than another one of the kernels; par. [0093]: kernels to perform one or more of the following tasks: convolutions, matrix multiply; par. [0113]: FIGS. 13a through 13c pertain to vertical fusion. As observed in FIG. 13a, a producer /consumer relationship exists between kernels [which each are nodes, see figure] being fused. For example, kernel K1 is a producer for kernel K2. After restructuring, a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; par. [0037]: one or more “consumer” kernels that represent the next stage/operation in the pipeline/DAG. In this manner, a “producer” kernel has its output data forwarded to a “consumer” kernel where the consumer kernel performs the next set of tasks after the producer kernel [so consumer and producer kernels each comprise a stage]) and generate one or more processor-executable processor kernels based, at least in part, on the one or more instances of the nodes combined from across the stages of the computational graph (e.g., Meixner, par. [0113]: a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; abstract, kernels that are to execute on respective ones of the stencil processors). Meixner does not explicitly disclose to heterogeneously compile the computational graph for execution of the computational graph by differently architectured processors. However, in an analogous art, McGuire discloses: to heterogeneously compile the computational graph for execution of the computational graph by differently architectured processors (e.g., McGuire, par. [0054]: the IR nodes are organized into a directed acyclic graph (DAG); par. [0044]: each IR node representing an operation; par. [0272]: to fuse operations; par. [0047]: ProgGen 600 returns a sequence of compiled programs corresponding to the IR nodes. The ProgGen 600 generates multiple copies of compiled programs, one for each type of processing element of the parallel-processing computer system for executing the compiled programs; par. [0011]: a parallel-processing computer system including multiple processing elements that may or may not have the same processor architecture; par. [0029]: types of processing elements including processors and/or coprocessors, although embodiments described below are related to particular types such as graphics processing units (GPUs) and multi-core CPU). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the generated kernels included in a graph taught by Meixner by heterogeneously compiling the graph for execution of the graph by differently architectured processors, as taught by McGuire, as McGuire would provide the advantage of a means of executing the kernel operations in a parallel-processing system having processing elements with different processor architectures. (See McGuire, par. [0011]) As to claim 3 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above), Meixner further discloses: wherein the one or more processor-executable processor kernels are to include operations capable of being performed together (e.g., Meixner, par. [0113]: After restructuring, a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2 [the function of each kernel being an operation]; par. [0094]: each kernel runs on its own stencil processor). As to claim 4 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above) Meixner further discloses: wherein the one or more processor-executable processor kernels are generated as one or more processor-executable processor kernels, (e.g., Meixner, par. [0113]: FIGS. 13a through 13c pertain to vertical fusion. As observed in FIG. 13a, a producer /consumer relationship exists between kernels being fused [so they are not able to be performed independently from one another, see above]. After restructuring, a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; Fig. 10a and associated text [see figure, there can be any number of kernels in the graph, so when two kernels are vertically fused, the graph would still comprise two or more kernels]; par. [0121]: there are other consumers of the producing kernel portion’s output that were not fused with the producing kernel portion, the producing kernel portion’s output is written to a line buffer so that external consuming kernels can receive the producer’s data). Meixner does not explicitly disclose where the one or more processor-executable processor kernels are to include operations capable of being performed on different processing architectures However, in an analogous art, McGuire discloses: where the one or more processor-executable processor kernels are to include operations capable of being performed on different processing architectures (e.g., McGuire, par. [0044]: each IR node representing an operation; par. [0272]: to fuse operations; par. [0047]: ProgGen 600 returns a sequence of compiled programs corresponding to the IR nodes. The ProgGen 600 generates multiple copies of compiled programs, one for each type of processing element of the parallel-processing computer system for executing the compiled programs; par. [0060]: the system prepares compute kernels for different types of processing elements; par. [0011]: processing elements may or may not have the same processor architecture). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the kernels of Meixner such that they include operations to be performed on different processing architectures, as taught by McGuire, as McGuire would provide the advantage of a means of executing the program on a high-performance processing system comprised of different types of processors. (See McGuire, par. [0011]). As to claim 5 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above), but Meixner does not explicitly disclose wherein the one or more circuits are further to identify the two or more computational graph nodes based, at least in part, on traversing the graph until a first object is reached that is to be materialized as an input of a second object. However, in an analogous art, McGuire discloses wherein the one or more circuits are further to identify the two or more computational graph nodes based, at least in part, on traversing the graph until a first object is reached that is to be materialized as an input of a second object (e.g., McGuire, par. [0044]: each IR node [object] representing an operation to be performed by the system; par. [0318]: in some embodiments a simpler algorithm is used to assign operations to kernels. In such a scheme, the ProgGen 600 essentially traverses the operation dependence graph in order to find operations eligible for fusion. Operations [objects] are eligible to be fused into the kernel currently being formed once all their inputs are guaranteed to have been previous computed [materialized] by this compute kernel or a previously generated one; par. [0045]: a map operation takes one or more arrays as input [i.e., inputs include data structures as well]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combination of nodes into kernels of Meixner such that the nodes are identified based on traversing a graph until a first object is reached that is to be materialized as an input to a second object, as taught by McGuire, as McGuire would provide a simple means of identifying operations eligible for fusion. (See McGuire, par. [0318]). As to claim 6 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above), Meixner further discloses: wherein the one or more processor-executable processor kernels are further to include a first and a second processor-executable processor kernel, the second processor-executable processor kernel to be dependent on the first processor-executable processor kernel (e.g., Meixner, par. [0037]: one or more “consumer” kernels that represent the next stage/operation in the pipeline/DAG. In this manner, a “producer” kernel has its output data forwarded to a “consumer” kernel). As to claim 7 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above), Meixner further discloses: wherein the one or more circuits are further to store one or more results of one or more first operations performed on the one or more processor-executable processor kernel to be input into one or more second operations (e.g., Meixner, Fig. 10a and associated text, par. [0095]: Output images from kernel K1 are forwarded to a second line buffer unit 1001_2 (LBU_2). These groups are then forwarded to a second processor upon which kernel K2 executes; par. [0128]: kernel K2 reads line buffers created by kernel K1 from a line buffer unit that kernel K1 writes it[s] output line buffers into; par. [0086]: circuitry that implements the line buffer unit). As to claim 8 , Meixner discloses a system, comprising memory to store executable instructions that, if executed by one or more processors, (e.g., Meixner, par. [0159]: embodiments of the invention may include various processes as set forth above. The processes may be embodied in machine-readable instructions. The instructions can cause a processor to perform certain processes) cause the system to: combine across stages of the computational graph two or more computational graph nodes of the computational graph in one or more instances across the computational graph, (e.g., Meixner, par. [0093]: a directed acyclic graph “(DAG)”; par. [0102]: a DAG of kernels; abstract: at least one of the kernels is more computationally intensive than another one of the kernels; par. [0093]: kernels to perform one or more of the following tasks: convolutions, matrix multiply; par. [0113]: FIGS. 13a through 13c pertain to vertical fusion. As observed in FIG. 13a, a producer /consumer relationship exists between kernels [which each are nodes, see figure] being fused. For example, kernel K1 is a producer for kernel K2. After restructuring, a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; par. [0037]: one or more “consumer” kernels that represent the next stage/operation in the pipeline/DAG. In this manner, a “producer” kernel has its output data forwarded to a “consumer” kernel where the consumer kernel performs the next set of tasks after the producer kernel [so consumer and producer kernels each comprise a stage]) and generate one or more processor-executable kernels based, at least in part, on the one or more instances of the nodes combined from across the stages of the computational graph (e.g., Meixner, par. [0113]: a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; abstract, kernels that are to execute on respective ones of the stencil processors); and Meixner does not explicitly disclose to heterogeneously compile the computational graph for execution of the computational graph by differently architectured processors. However, in an analogous art, McGuire discloses to heterogeneously compile the computational graph for execution of the computational graph by differently architecture processors (e.g., McGuire, par. [0054]: the IR nodes are organized into a directed acyclic graph (DAG); par. [0044]: each IR node representing an operation; par. [0272]: to fuse operations; par. [0047]: ProgGen 600 returns a sequence of compiled programs corresponding to the IR nodes. The ProgGen 600 generates multiple copies of compiled programs, one for each type of processing element of the parallel-processing computer system for executing the compiled programs; par. [0011]: a parallel-processing computer system including multiple processing elements that may or may not have the same processor architecture; par. [0029]: types of processing elements including processors and/or coprocessors, although embodiments described below are related to particular types such as graphics processing units (GPUs) and multi-core CPU). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the generated kernels included in a graph taught by Meixner by heterogeneously compiling the graph for execution of the graph by differently architectured processors, as taught by McGuire, as McGuire would provide the advantage of a means of executing the kernel operations in a parallel-processing system having processing elements with different processor architectures. (See McGuire, par. [0011]) As to claim 10 , Meixner/McGuire discloses the system of claim 8 (see rejection of claim 8 above), Meixner further discloses: wherein the one or more processor-executable processor kernels are to include operations capable of being performed together (e.g., Meixner, par. [0113]: After restructuring, a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2 [the function of each kernel being an operation]; par. [0094]: each kernel runs on its own stencil processor). As to claim 11 , Meixner/McGuire discloses the system of claim 8 (see rejection of claim 8 above), Meixner further discloses: wherein the one or more processor-executable processor kernels are generated as one or more processor-executable processor kernels (e.g., Meixner, par. [0113]: FIGS. 13a through 13c pertain to vertical fusion. As observed in FIG. 13a, a producer /consumer relationship exists between kernels being fused [so they are not able to be performed independently from one another, see above]. After restructuring, a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; Fig. 10a and associated text [see figure, there can be any number of kernels in the graph, so when two kernels are vertically fused, the graph would still comprise two or more kernels]; par. [0121]: there are other consumers of the producing kernel portion’s output that were not fused with the producing kernel portion, the producing kernel portion’s output is written to a line buffer so that external consuming kernels can receive the producer’s data). Meixner does not explicitly disclose where the one or more processor-executable processor kernels are to include operations capable of being performed on different processing architectures. However, in an analogous art, McGuire discloses: where the one or more processor-executable processor kernels are to include operations capable of being performed on different processing architectures (e.g., McGuire, par. [0044]: each IR node representing an operation; par. [0272]: to fuse operations; par. [0047]: ProgGen 600 returns a sequence of compiled programs corresponding to the IR nodes. The ProgGen 600 generates multiple copies of compiled programs, one for each type of processing element of the parallel-processing computer system for executing the compiled programs; par. [0060]: the system prepares compute kernels for different types of processing elements; par. [0011]: processing elements may or may not have the same processor architecture). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the kernels of Meixner such that they include operations to be performed on different processing architectures, as taught by McGuire, as McGuire would provide the advantage of a means of executing the program on a high-performance processing system comprised of different types of processors. (See McGuire, par. [0011]). As to claim 12 , Meixner/McGuire discloses the system of claim 8 (see rejection of claim 8 above, but does not explicitly disclose wherein the memory stores further executable instructions that, if executed by the one or more processors, cause the system to identify the two or more computational graph nodes based, at least in part, on traversing the graph until a first data structure is reached that is to be materialized as an input of a second data structure However, in an analogous art, McGuire discloses: wherein the memory stores further executable instructions that, if executed by the one or more processors, cause the system to identify the two or more computational graph nodes based, at least in part, on traversing the graph until a first data structure is reached that is to be materialized as an input of a second data structure (e.g., McGuire, par. [0044]: each IR node [object] representing an operation to be performed by the system; par. [0318]:in some embodiments a simpler algorithm is used to assign operations to kernels. In such a scheme, the ProgGen 600 essentially traverses the operation dependence graph in order to find operations eligible for fusion. Operations are eligible to be fused into the kernel currently being formed once all their inputs are guaranteed to have been previously computed [materialized] by this compute kernel or a previously generated one; par. [0045]: a map operation takes one or more arrays as input [i.e., inputs include data structures as well]; par. [0044]: each IR node representing an operation to be performed by the system; par. [0140]: “Data” node identifies an input to a particular parse node). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combination of nodes into kernels of Meixner such that the nodes are identified based on traversing a graph until a first object is reached that is to be materialized as an input to a second object, as taught by McGuire, as McGuire would provide a simple means of identifying operations eligible for fusion. (See McGuire, par. [0318]). As to claim 13 , Meixner/McGuire discloses the system of claim 8 (see rejection of claim 8 above), Meixner further discloses: wherein the one or more processor-executable processor kernels are further to include a first and a second processor-executable processor kernel, the second processor-executable processor kernel to be dependent on an output of the first processor-executable processor kernel (e.g., Meixner, par. [0037]: one or more “consumer” kernels that represent the next stage/operation in the pipeline/DAG. In this manner, a “producer” kernel has its output data forwarded to a “consumer” kernel). As to claim 14 , Meixner/McGuire discloses the system of claim 8 (see rejection of claim 8 above), but does not explicitly disclose further comprising a register, wherein the memory stores further executable instructions that, if executed by the one or more processors, cause the system to store, in the register, one or more results of one or more first operations performed on the one or more processor-executable processor kernels to be input into one or more second operations. However, in an analogous art, McGuire discloses: further comprising a register , (see immediately below) wherein the memory stores further executable instructions that, if executed by the one or more processors, cause the system to store, in the register, one or more results of one or more first operations performed on the one or more processor-executable processor kernels to be input into one or more second operations (e.g., McGuire, par. [0044]: each IR node representing an operation. These IR nodes are used by the runtime system (e.g., the program generator 600) to generate computer kernels; par. [0061]: the ProgGen 600 determines which set of IR nodes should correspond to a computer kernel and attempts to merge operations into the compute kernel [an operation in a kernel being “on” the kernel]; par. [0272]: the result(s) of one fused operation may be passed directly to a consuming operation using the most efficient means possible on the target architecture “(e.g., using registers)” [i.e., storing the results in those registers]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the storing of results of Meixner to include a register and storing, in the register, one or more results of one or more first operations performed on the processor-executable processor kernel to be input into one or more second operations, as taught by McGuire, as McGuire would provide the advantage of a means of passing the results to a consuming operation using the most efficient means possible. (See McGuire, par. [0272]). As to claim 15, Meixner discloses a method comprising: identifying two or more computational graph nodes of a computational graph in one or more instances across stages of the computational graph (see immediately below) combining across the stages of the computational graph the identified two or more computational graph nodes of the computational graph in one or more instances across the computational graph; (e.g., Meixner, par. [0093]: a directed acyclic graph “(DAG)”; par. [0102]: a DAG of kernels; abstract: at least one of the kernels is more computationally intensive than another one of the kernels; par. [0093]: kernels to perform one or more of the following tasks: convolutions, matrix multiply; par. [0113]: FIGS. 13a through 13c pertain to vertical fusion. As observed in FIG. 13a, a producer /consumer relationship exists between kernels [which each are nodes, see figure] being fused. For example, kernel K1 is a producer for kernel K2. After restructuring, a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; par. [0037]: one or more “consumer” kernels that represent the next stage/operation in the pipeline/DAG. In this manner, a “producer” kernel has its output data forwarded to a “consumer” kernel where the consumer kernel performs the next set of tasks after the producer kernel [so consumer and producer kernels each comprise a stage]) and generating one or more software kernels corresponding to the computational graph based at least in part on combined identified two or more computation graph nodes from across stages of the computational graph; (e.g., Meixner, par. [0113]: a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; abstract, kernels that are to execute on respective ones of the stencil processors) and Meixner does not explicitly disclose heterogeneously compiling the computational graph for execution of the computational graph by differently architecture processors. However, in an analogous art, McGuire discloses: heterogeneously compiling the computational graph for execution of the computational graph by differently architecture processors (e.g., McGuire, par. [0054]: the IR nodes are organized into a directed acyclic graph (DAG); par. [0044]: each IR node representing an operation; par. [0272]: to fuse operations; par. [0047]: ProgGen 600 returns a sequence of compiled programs corresponding to the IR nodes. The ProgGen 600 generates multiple copies of compiled programs, one for each type of processing element of the parallel-processing computer system for executing the compiled programs; par. [0011]: a parallel- processing computer system including multiple processing elements that may or may not have the same processor architecture; par. [0029]: types of processing elements including processors and/or coprocessors, although embodiments described below are related to particular types such as graphics processing units (GPUs) and multi-core CPU). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the generated kernels included in a graph taught by Meixner by heterogeneously compiling the graph for execution of the graph by differently architectured processors, as taught by McGuire, as McGuire would provide the advantage of a means of executing the kernel operations in a parallel-processing system having processing elements with different processor architectures. (See McGuire, par. [0011]) As to claim 16 , Meixner/McGuire discloses the method of claim 15 (see rejection of claim 15 above), Meixner discloses: wherein the one or more software kernels include sequential phases of operations, the sequential phases of operations represented one or more instances across the graph of by the two or more computational graph nodes (e.g., Meixner, Figs. 13a 13b and associated text, par. [0114]: Kernel K1 is a producer for kernel K2 “(kernel K2 is a consumer of kernel K1)” [i.e., they are sequential phases of operations, see figure]; par. [0114]: FIG. 13b shows the construction of the new kernel. Here, the consuming kernel K2 is concatenated after kernel K [as sequential phases, see figure]). As to claim 17 , Meixner/McGuire discloses the method of claim 15 (see rejection of claim 15 above), Meixner further discloses: wherein the one or more software kernels include operations performed together in a single kernel launch (e.g., Meixner, Figs. 13a, 13b and associated text, par. [0113]: a new kernel K1/K2 is generated that performs the function of fused kernels K1 and K2; par. [0120]: as a consequence of the producing and consuming kernel portions being fused and executed [launched] on the same stencil processor, the output generated by the producing kernel portion may remain local. Rather than read data from a line buffer unit, the consuming kernel portion reads the output data from the memory that is local to the stencil processor). As to claim 18 , Meixner/McGuire discloses the method of claim 15 (see rejection of claim 15 above), but Meixner does not explicitly disclose wherein the one or more software kernels corresponding to the graph perform operations for the graph executable on differently architectured processors, and wherein each software kernel of the two or more software kernels is to include a set of operations of the two or more sets of operations to be performed on a processing architecture of the two or more processing architectures. However, in an analogous art, McGuire discloses: wherein the one or more software kernels corresponding to the graph perform operations for the graph executable on differently architecture processors, (e.g., McGuire, par. [0545]: a uniform intermediate representation (IR). The intermediate representation is represented as a directed acyclic graph (DAG); par. [0061]: the ProgGen 600 determines which set of IR nodes should correspond to a computer kernel and attempts to merge operations into the compute kernel; par. [0035]: a compute kernel is an executable program that runs on one or more processing elements; par. [0060]: the system prepares compute kernels for different types of processing elements; par. [0011]: this invention relates to high-performance computing on a parallel architecture computer system including multiple processing elements that may or may not have the same processor architecture). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the two or more kernels of Meixner such that they perform operations for the graph executable on differently architecture processors, as taught by McGuire, as McGuire would provide the advantage of a means of executing the program on a high-performance processing system comprised of different types of processors. (See McGuire, par. [0011]). As to claim 19 , Meixner/McGuire discloses the method of claim 15 (see rejection of claim 15 above), Meixner further discloses: wherein the one or more software kernels include a first software kernel and a second software kernel, (see below) and wherein the first software kernel provides the input to the second software kerne l (e.g., Meixner, Fig. 10a and associated text, par. [0095]: Output images from kernel K1 are forwarded to a second line buffer unit 1001_2 (LBU_2). These groups are then forwarded to a second processor upon which kernel K2 executes; par. [0128]: kernel K2 reads line buffers created by kernel K1 from a line buffer unit that kernel K1 writes it[s] output line buffers into). Meixner does not explicitly disclose wherein identifying the two or more computational graph nodes comprises traversing the graph until a first data structure is reached that is materialized as an input of a second data structure. However, in an analogous art, McGuire discloses: wherein identifying the two or more computational graph nodes comprises traversing the graph until a first data structure is reached that is materialized as an input of a second data structure, (e.g., McGuire, par. [0044]: each IR node [object] representing an operation to be performed by the system; par. [0318]: in some embodiments a simpler algorithm is used to assign operations to kernels. In such a scheme, the ProgGen 600 essentially traverses the operation dependence graph in order to find operations eligible for fusion. Operations [object]s are eligible to be fused into the kernel currently being formed once all their inputs are guaranteed to have been previous computed [materialized] by this compute kernel or a previously generated one; par. [0045]: a map operation takes one or more arrays as input [i.e., inputs include data structures as well]; par. [0140]: “Data” node identifies an input to a particular parse node). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of nodes into kernels of Meixner such that the nodes are identified based on traversing a graph until a first object is reached that is to be materialized as an input to a second object, as taught by McGuire, as McGuire would provide a simple means of identifying operations are eligible for the fusion. (See McGuire, par. [0318]). As to claim 20 , Meixner/McGuire discloses the method of claim 15 (see rejection of claim 15 above), Meixner further discloses: further comprising storing one or more results of one or more first operations performed on a first set of software kernels input into one or more second operations performed on a second set of software kernels (e.g., Meixner, par. [0121]: there are other consumers of the producing kernel portion’s output that were not fused with the producing kernel portion, the producing kernel portion’s output is written to a line buffer so that external consuming kernels can receive the producer’s data). As to claim 23 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above) Meixner further discloses: wherein the one or more processor-executable processor kernels are to be generated based, at least in part on the one or more instances of the combined nodes from across the stages of the computational graph comprising two or more computational graph nodes across the stages of the computational graph (see rejection of claim 1 above). Meixner does not explicitly discloses wherein the processor executable kernels are to be generated to result in common subexpression elimination and/or dead code elimination. However, in an analogous art, McGuire discloses: wherein the one or more processor-executable processor kernels are to be generated to result in common subexpression elimination and/or dead code elimination (e.g., McGuire, par. [0272]: stores of results may be omitted entirely in the case that all consumers of a result are fused into the same kernel. It is also possible to eliminate redundant calculations within a compute kernel by common sub-expression elimination). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the generating of processor-executable processor kernels based at least in part on the one or more instances of the combined nodes from across the stages of the computational graph comprising two or more computational graph nodes across the stages of the computational graph taught by Meixner such that the kernels are generated to result in common subexpression elimination, as taught by McGuire, as McGuire would provide the advantage of a means of eliminating redundant calculations within the kernels. (See McGuire, par. [0272]). Claim 2 and 9 are rejected under 35 U.S.C. 103 as unpatentable over Meixner (US 2017/0249716) in view of McGuire (US 2007/0294663) in further view of Eble et al. (US 2016/0147511) (art made of record – hereinafter Eble). As to claim 2 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above), Meixner further discloses: wherein the one or more processor-executable processor kernels are to be generated by partitioning the graph so that any and all processor-executable kernels are equal to or below a threshold size (Meixner, par. [0102]: a DAG of kernels; par. [0137]: in the case of graph splitting, the amount of data that is processed by the DAG exceeds the internal memory requirements of the image processor. As such, the DAG has to be split into multiple DAGs, each of which process an amount of data that is within the internal storage space limits of the image processor. If the storage requirements of a single DAG exceed the memory capacity of one or more of these memories [i.e., a threshold], multiple DAGs are created; par. [0123]: a fission split may be imposed by the compiler if the kernel being split K is more computationally intense and/or its instruction footprint is too large to fit into the stencil processor memory [the size of that memory being a threshold]). Meixner/McGuire does not explicitly disclose a threshold size to limit compilation times. (BUT note that this language is not limiting as to only expresses the intended result of the positively recited step. See M.P.E.P. § 2111.04). However, in an analogous art, Eble discloses: a threshold size to limit compilation times (e.g., Eble, par. [0073]: the one or more complexity metrics may include a count of lines of code in a candidate splitting region; par. [0074]: use of a function splitting technique may be necessary or desirable only when a source function has a complexity level that exceeds the maximum complexity level; par. [0033]: to divide large size functions into smaller size functions, which by virtue of their size, can be quickly compiled). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the threshold size of Meixner/McGuire, such that it comprises a size to limit compilation times, as taught by Eble, as Eble would provide the advantage of a means of ensuring the kernels can be quickly compiled. (See Eble, par. [0033]). As to claim 9 , Meixner/McGuire discloses the system of claim 8 (see rejection of claim 8 above), Meixner further discloses: wherein the one or more processor-executable processor kernels are to be generated by partitioning the graph so that any and all processor-executable processor kernels are equal to or below a threshold size (Meixner, par. [0102]: a DAG of kernels; par. [0137]: in the case of graph splitting, the amount of data that is processed by the DAG exceeds the internal memory requirements of the image processor. As such, the DAG has to be split into multiple DAGs, each of which process an amount of data that is within the internal storage space limits of the image processor. If the storage requirements of a single DAG exceed the memory capacity of one or more of these memories [i.e., a threshold], multiple DAGs are created; par. [0123]: a fission split may be imposed by the compiler if the kernel being split K is more computationally intense and/or its instruction footprint is too large to fit into the stencil processor memory [the size of that memory being a threshold]). Meixner/McGuire does not explicitly disclose a threshold size to limit compilation times. (BUT note that this language is not limiting as to only expresses the intended result of the positively recited step. See M.P.E.P. § 2111.04). However, in an analogous art, Eble discloses: a threshold size to limit compilation times (e.g., Eble, par. [0073]: the one or more complexity metrics may include a count of lines of code in a candidate splitting region; par. [0074]: use of a function splitting technique may be necessary or desirable only when a source function has a complexity level that exceeds the maximum complexity level; par. [0033]: to divide large size functions into smaller size functions, which by virtue of their size, can be quickly compiled). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the threshold size of Meixner/McGuire, such that it comprises a size to limit compilation times, as taught by Eble, as Eble would provide the advantage of a means of ensuring the kernels can be quickly compiled. (See Eble, par. [0033]). Claims 21 and 22 are are rejected under 35 U.S.C. 103 as unpatentable over Meixner (US 2017/0249716) in view of McGuire (US 2007/0294663) in further view of Aman et al. (US 9,184,980) (art made of record – hereinafter Aman). As to claim 21 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1) but Meixner does not explicitly disclose wherein the one or more instances of combining nodes across stages of the computational graph and then, backward traversal thereof, results in selective kernel generation. However, in an analogous art, McGuire discloses wherein the one or more instances of combining nodes across stages of the computational graph and then, traversal thereof, results in selective kernel generation (e.g., McGuire, Fig. 6 and associated text, par. [0315]: the ProgGen 600 schedules as many operations as possible into the program until none is left for fusion or the size of the program reaches a limit set by a processing element. At that point, the ProgGen 600 compiles the program (650). The ProgGen 600 repeats the process until all operations are scheduled 662 [so operations are fused, and then the fusion process repeats]; par. [0054]: the IR nodes are organized into a directed acyclic graph (DAG); par. [0044]: each IR node representing an operation; par. [0318]: ProgGen 600 traverses the operation dependence graph in order to find operations eligible for fusion. Operations are eligible to be fused into the compute kernel currently being formed once all their inputs are guaranteed to have been computed by this kernel [so fusion includes traversing the graph]; par. [0272]: to fuse operations; par. [0276]: operations computing a scalar result [a stage] could be fused with an operation that multiplies that scalar by a vector [another stage]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fusing of nodes and graph of Meixner such that the one or more instances of combining nodes across stages of the computational graph and then, traversal thereof, results in selective kernel generation, as taught by McGuire, as McGuire would provide a simple means of identifying which operations eligible for fusion. (See McGuire, par. [0318]). Further, in an analogous art, Aman discloses: backward traversal (e.g., Aman, col. 1 ll. 24-26: a graph can be traversed both forwards and backwards across many nodes) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traversal of McGuire such that it is backwards, as taught by Aman. McGuire suggests the combination because McGuire discloses traversing the graph without limiting that traversal to any particular direction. It would also have been obvious to try and modify the traversal of McGuire such that it is performed backwards, as, per Aman, successful traversal of a graph can be successfully performed in either a forwards or backwards direction. See M.P.E.P. § 2143(I)(E). As to claim 22 , Meixner/McGuire discloses the one or more processors of claim 1 (see rejection of claim 1 above) but Meixner does not explicitly disclose wherein the backward traversal is to identify nodes that have been materialized and to identify node that have not been materialized to assist in the combining across stages of the computational graph. However, in an analogous art, McGuire discloses: wherein the traversal is to identify nodes that have been materialized and to identify node that have not been materialized (e.g., McGuire, par. [0044]: each IR node [object] representing an operation to be performed by the system; par. [0318]: in some embodiments a simpler algorithm is used to assign operations to kernels. In such a scheme, the ProgGen 600 essentially traverses the operation dependence graph in order to find operations eligible for fusion. Operations [objects] are eligible to be fused into the kernel currently being formed once all their inputs are guaranteed to have been previous computed [materialized] by this compute kernel or a previously generated one; par. [0320]: ProgGen 600 maintains two lists of operations, the non-fusible ready list [nodes that have not been materialized] and the fusible ready list) to assist in the combining across stages of the computational graph (this language is only directed to non-limiting intended use. McGuire also combines across stages as set forth above with respect to claim 21). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to fusing of nodes and graph of Meixner such that traversal of the graph is performed to identify nodes that have been materialized and to identify node that have not been materialized to assist in the combining across stages of the computational graph as taught by McGuire, as McGuire would provide a simple means of identifying operations eligible for fusion. (See McGuire, par. [0318]). Further, in an analogous art, Aman discloses: backward traversal (e.g., Aman, col. 1 ll. 24-26: a graph can be traversed both forwards and backwards across many nodes) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the traversal of McGuire such that it is backwards, as taught by Aman. McGuire suggests the combination because McGuire discloses traversing the graph without limiting that traversal to any particular direction. It would also have been obvious to try and modify the traversal of McGuire such that it is performed backwards, as, per Aman, successful traversal of a graph can be successfully performed in either a forwards or backwards direction. See M.P.E.P. § 2143(I)(E). Claim 24 is rejected under 35 U.S.C. 103 as unpatentable over Meixner (US 2017/0249716) in view of McGuire (US 2007/0294663) in further view of Kerr et al. (US 2015/0339209) (art made of record – hereinafter Kerr). As to claim 24 , Meixner/McGuire disclose the one or more processors of claim 1 (see rejection of claim 1 above) but Meixner does not explicitly disclose wherein library calls are intercepted to form the computational graph. However, in an analogous art, Kerr discloses: wherein library calls are intercepted to form the computational graph (e.g., Kerr, par. [0061]: the dependency extractor instruments a software application to capture data associated with each task that is executed [capturing this information being intercepting it]. Subsequently, the dependency extractor constructs a dependency graph that captures each task as a node; par. [0033]: a task is a component such as an API call or a computation operation on the CPU; par. [0025]: the CUDA API 101 includes calls and libraries; par. [0029]: tasks, such as CUDA API calls). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the computational graph of Meixner such that it is formed by intercepting library calls, as taught by Kerr, as Kerr would provide the advantage of a means of better directing optimization efforts of the program. (See Kerr, par. [0011]). Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TODD AGUILERA whose telephone number is (571)270-5186. The examiner can normally be reached M-F 11AM - 7:30PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hyung S Sough can be reached at (571)272-6799. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TODD AGUILERA/Primary Examiner, Art Unit 2192 Application/Control Number: 18/134,919 Page 2 Art Unit: 2192 Application/Control Number: 18/134,919 Page 3 Art Unit: 2192 Application/Control Number: 18/134,919 Page 4 Art Unit: 2192 Application/Control Number: 18/134,919 Page 6 Art Unit: 2192 Application/Control Number: 18/134,919 Page 7 Art Unit: 2192 Application/Control Number: 18/134,919 Page 8 Art Unit: 2192 Application/Control Number: 18/134,919 Page 9 Art Unit: 2192 Application/Control Number: 18/134,919 Page 10 Art Unit: 2192 Application/Control Number: 18/134,919 Page 11 Art Unit: 2192 Application/Control Number: 18/134,919 Page 12 Art Unit: 2192 Application/Control Number: 18/134,919 Page 13 Art Unit: 2192 Application/Control Number: 18/134,919 Page 14 Art Unit: 2192 Application/Control Number: 18/134,919 Page 15 Art Unit: 2192 Application/Control Number: 18/134,919 Page 16 Art Unit: 2192 Application/Control Number: 18/134,919 Page 17 Art Unit: 2192 Application/Control Number: 18/134,919 Page 18 Art Unit: 2192 Application/Control Number: 18/134,919 Page 19 Art Unit: 2192 Application/Control Number: 18/134,919 Page 20 Art Unit: 2192 Application/Control Number: 18/134,919 Page 21 Art Unit: 2192 Application/Control Number: 18/134,919 Page 22 Art Unit: 2192 Application/Control Number: 18/134,919 Page 23 Art Unit: 2192 Application/Control Number: 18/134,919 Page 24 Art Unit: 2192 Application/Control Number: 18/134,919 Page 25 Art Unit: 2192 Application/Control Number: 18/134,919 Page 26 Art Unit: 2192 Application/Control Number: 18/134,919 Page 27 Art Unit: 2192 Application/Control Number: 18/134,919 Page 28 Art Unit: 2192 Application/Control Number: 18/134,919 Page 29 Art Unit: 2192 Application/Control Number: 18/134,919 Page 30 Art Unit: 2192 Application/Control Number: 18/134,919 Page 32 Art Unit: 2192 Application/Control Number: 18/134,919 Page 33 Art Unit: 2192
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