DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 01/30/2026 have been fully considered but they are not persuasive.
Bang and Bae, each of which discloses the claimed invention see rejection below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bang et al. 20210134928.
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Regarding claim 1, fig. 5 of Bang discloses a display apparatus comprising:
a substrate 100 comprising a sub-pixel area;
a pixel circuit layer located on the substrate and defining a pixel circuit overlapping the sub-pixel area; and
a display element layer located on the pixel circuit layer and comprising a display element OLED,
wherein the pixel circuit layer comprises:
an inorganic insulating layer (101/103/105/107) located on the substrate and comprising a groove (as labeled by examiner above);
an organic insulating layer 109 located on the inorganic insulating layer and filling the groove; and
a plurality of conductive patterns (all conductive patterns directly contacting top surface of 107) located between the inorganic insulating layer and the organic insulating layer,
wherein the plurality of conductive patterns (all conductive patterns directly contacting top surface of 107) comprises a first conductive pattern 10a connected to a data line (10b which is a type of data line), the data line is located on the organic insulating layer,
wherein the groove is located between the first conductive pattern 10a and adjacent conductive patterns (20a CNT2) of the plurality of conductive patterns, the adjacent conductive patterns are spaced apart from the first conductive pattern.
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Regarding claim 11, fig. 5 of Bang discloses a display apparatus comprising:
a substrate 100 comprising a sub-pixel area;
an inorganic insulating layer (101/103/105/107) located on the substrate, the inorganic insulating layer overlapping the sub-pixel area and comprising a groove (as labeled by examiner above);
a plurality of conductive patterns (all conductive patterns directly contacting top surface of 107) located on the inorganic insulating layer; and
an organic insulating layer 109 covering the inorganic insulating layer and the plurality of conductive patterns and filling the groove,
wherein the plurality of conductive patterns comprises a first conductive pattern 10a connected to a data line (10b which is a type of data line) that is located on the organic insulating layer,
a second conductive pattern CNT1 connected to a driving voltage line 10a, and
a third conductive pattern (contact pattern between D1 and CL) connected to an upper conductive pattern CL,
wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are each surrounded by the groove (surface non-uniformities on 107).
Regarding claim 2, fig. 5 of Bang discloses wherein: the groove is filled with the organic insulating layer 109; and the groove overlaps the display element OLED.
Regarding claim 3, fig. 5 of Bang discloses wherein: the inorganic insulating layer comprises a plurality of inorganic insulating patterns (local maximum patterns) spaced apart from each other by the groove; and
a lower inorganic insulating layer (layer 105 to 101) located between the substrate and the plurality of inorganic insulating patterns.
Regarding claim 4, fig. 5 of Bang discloses wherein: the pixel circuit layer further comprises a first semiconductor layer A1 located on the substrate, the first semiconductor layer comprising a silicon semiconductor (par [0103]), wherein the lower inorganic insulating layer comprises at least one insulating layer 103 located between the first semiconductor layer and the plurality of inorganic insulating patterns.
Regarding claim 5, fig. 5 of Bang discloses wherein: the pixel circuit layer further comprises a second semiconductor layer A2 located on the substrate, the second semiconductor layer comprising an oxide semiconductor (par [0103]), wherein the lower inorganic insulating layer comprises at least one insulating layer 105 located between the second semiconductor layer and the plurality of inorganic insulating patterns.
Regarding claim 7, fig. 5 of Bang discloses wherein: the pixel circuit layer further comprises:
an upper conductive pattern CL located on the organic insulating layer and connected to the display element; and
an upper organic insulating layer 111 located on the upper conductive pattern; and
the plurality of conductive patterns comprises:
a second conductive pattern CNT1 connected to a driving voltage line 10a and a third conductive pattern (contact pattern between D1 and CL) connected to the upper conductive pattern,
wherein the groove is further located between the second conductive pattern and the third conductive pattern.
Regarding claim 8, fig. 5 of Bang discloses wherein: the display element layer further comprises a pixel electrode 310 located on the upper organic insulating layer; the first conductive pattern electrically connects the data line 10a to a switching transistor (as the switching is provided with voltage and element 10a is power supply voltage line);
the second conductive pattern electrically connects the driving voltage line to an operation control transistor, and
the third conductive pattern electrically connects the pixel electrode 310 to an emission control transistor T1.
Regarding claim 9, fig. 3 of Bang discloses wherein: the sub-pixel area comprises a first sub-pixel area and a second sub-pixel area each surrounded by the groove of the inorganic insulating layer, wherein the pixel circuit comprises a first pixel circuit overlapping the first sub-pixel area (as shown fig. 5) and a second pixel circuit overlapping the second sub-pixel area (as shown in fig. 4), wherein a connection electrode is located on the organic insulating layer, the connection electrode connecting the first pixel circuit and the second pixel circuit to each other (there exist a physical connection).
Regarding claim 10, fig. 5 of Bang discloses wherein the display element layer further comprises: an intermediate layer 320 located on the pixel electrode; and a counter electrode 330 covering the intermediate layer.
Regarding claim 12, Bang discloses wherein: the inorganic insulating layer comprises a plurality of inorganic insulating patterns (local maximum patterns) spaced apart from each other by the groove, wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are respectively located on the plurality of inorganic insulating patterns.
Regarding claim 13, fig. 5 of Bang discloses wherein the organic insulating layer 109 is located in the groove between the plurality of inorganic insulating patterns.
Regarding claim 16, fig. 5 of Bang discloses wherein the driving voltage line and the upper conductive pattern are located on the organic insulating layer.
Regarding claim 17, fig. 5 of Bang discloses further comprising: an upper organic insulating layer 111 located on the organic insulating layer, and a display element layer located on the upper organic insulating layer, the display element layer comprising a display element OLED, wherein the groove of the inorganic insulating layer overlaps the display element.
Regarding claim 18, fig. 5 of Bang discloses wherein the display element layer further comprises: a pixel electrode 310 located on the upper organic insulating layer and connected to the upper conductive pattern; an intermediate layer 320 located on the pixel electrode; and a counter electrode 330 covering the intermediate layer.
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Regarding claim 11, 14, fig. 5 of Bang discloses a display apparatus comprising:
a substrate 100 comprising a sub-pixel area;
an inorganic insulating layer (101/103/105/107) located on the substrate, the inorganic insulating layer overlapping the sub-pixel area and comprising a groove (as labeled by examiner above);
a plurality of conductive patterns (all conductive patterns directly contacting top surface of 107) located on the inorganic insulating layer and filling the groove; and
an organic insulating layer 109 covering the inorganic insulating layer and the plurality of conductive patterns,
wherein the plurality of conductive patterns comprises a first conductive pattern D2 connected to a data line PL (physically connected) that is located on the organic insulating layer,
a second conductive pattern S2 connected (physically connected) to a driving voltage line 10a, and
a third conductive pattern G2 connected (physically connected) to an upper conductive pattern CL,
wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are each surrounded by the groove (surface non-uniformities on 107);
further comprising: a first semiconductor layer A2 located on the substrate, the first semiconductor layer comprising a silicon semiconductor (par [0103]); and
a second semiconductor layer A1 located on the substrate, the second semiconductor layer comprising an oxide semiconductor (par [0103]),
wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern overlap the first semiconductor layer;
wherein the first semiconductor layer A2 comprises: a source region of a switching transistor T1 connected to the first conductive pattern, a source region of an operation control transistor T1 (T1 is both a switching transistor and an operation control transistor as it control certain operation) connected to the second conductive pattern, and a drain region of an emission control transistor (T1 is also an emission control transistor because without it there will be to emission) connected to the third conductive pattern.
Regarding claim 19, figs. 2-3 of Bang discloses
wherein: the sub-pixel area comprises a first sub-pixel area overlapping a first pixel circuit and a second sub-pixel area overlapping a second pixel circuit, the first sub-pixel area and the second sub-pixel area each being surrounded by the groove,
wherein the first pixel circuit and the second pixel circuit are located on the organic insulating layer,
wherein a connection electrode PL is located on the organic insulating layer and crosses the groove (see fig. 5), the connection electrode connecting the first pixel circuit and the second pixel circuit to each other (par [0075]).
Claims 1-3, 9 and 11-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by BAE et al. 20220045137.
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Regarding claim 1, fig. 14 of BAE disclose a display apparatus comprising:
a substrate 100 comprising a sub-pixel area;
a pixel circuit layer located on the substrate and defining a pixel circuit overlapping the sub-pixel area; and a display element layer located on the pixel circuit layer and comprising a display element OLED,
wherein the pixel circuit layer comprises:
an inorganic insulating layer IL located on the substrate and comprising a groove GR ;
an organic insulating layer 117/OL located on the inorganic insulating layer and filling the groove; and
a plurality of conductive patterns (see patterns on top of 115) located between the inorganic insulating layer and the organic insulating layer (see fig. 6),
wherein the plurality of conductive patterns comprises a first conductive pattern DL connected to a data line (to the point of original of the data line which is a data line),
the data line is located on the organic insulating layer (located on the bottom of),
wherein the groove is located between the first conductive pattern and adjacent conductive patterns of the plurality of conductive patterns, the adjacent conductive patterns are spaced apart from the first conductive pattern.
Regarding claim 11. Fig. 6 of BAE discloses a display apparatus comprising:
a substrate 100 comprising a sub-pixel area;
an inorganic insulating layer IL located on the substrate, the inorganic insulating layer overlapping the sub-pixel area and comprising a groove GR;
a plurality of conductive patterns (see patterns on top of 115) located on the inorganic insulating layer; and
an organic insulating layer 117/OL covering the inorganic insulating layer and the plurality of conductive patterns and filling the groove,
wherein the plurality of conductive patterns comprises a first conductive pattern D connected (physically) to a data line DL that is located on the organic insulating layer,
a second conductive pattern S connected (physically) to a driving voltage line WL (par [0124]), and
a third conductive pattern (contact pattern between CM and D) connected to an upper conductive pattern CM,
wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are each surrounded by the groove.
Regarding claim 2, fig. 6 of Bae discloses wherein: the groove is filled with the organic insulating layer; and the groove overlaps the display element.
Regarding claim 3, fig. 6 of Bae discloses wherein: the inorganic insulating layer comprises a plurality of inorganic insulating patterns (see fig. 6 showing grooves creates patterns in between grooves) spaced apart from each other by the groove; and a lower inorganic insulating layer 111 located between the substrate and the plurality of inorganic insulating patterns.
Regarding claim 12, fig. 6 of Bae discloses wherein: the inorganic insulating layer comprises a plurality of inorganic insulating patterns (see fig. 6 showing grooves creates patterns in between grooves) spaced apart from each other by the groove, wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern are respectively located on the plurality of inorganic insulating patterns.
Regarding claim 13, fig. 6 of Bae discloses wherein the organic insulating layer is located in the groove between the plurality of inorganic insulating patterns.
Regarding claim 14, fig. 6 of BAE discloses further comprising: a first semiconductor layer located on the substrate, the first semiconductor layer comprising a silicon semiconductor (par [0119]); and a second semiconductor layer located on the substrate, the second semiconductor layer comprising an oxide semiconductor (par [0119]), wherein the first conductive pattern, the second conductive pattern, and the third conductive pattern overlap the first semiconductor layer.
Regarding claim 15, fig. 3B of Bae discloses wherein the first semiconductor layer comprises: a source region of a switching transistor T2 connected to the first conductive pattern, a source region of an operation control transistor T5 connected to the second conductive pattern, and a drain region of an emission control transistor T6 connected to the third conductive pattern.
Regarding claim 16, fig. 6 of Bae discloses wherein the driving voltage line and the upper conductive pattern are located on (forming a distinctive or marked part of (the surface of something) the organic insulating layer.
Regarding claim 17, fig. 6 of Bae discloses further comprising: an upper organic insulating layer 118 located on the organic insulating layer, and a display element layer located on the upper organic insulating layer, the display element layer comprising a display element OLED, wherein the groove of the inorganic insulating layer overlaps the display element.
Regarding claim 18, fig. 6 of Bae discloses wherein the display element layer further comprises: a pixel electrode 311 located on the upper organic insulating layer and connected to the upper conductive pattern; an intermediate layer 221 located on the pixel electrode; and a counter electrode 230 covering the intermediate layer.
Regarding claims 9 and 19, fig. 6 of Bae discloses wherein: the sub-pixel area comprises a first sub-pixel area overlapping a first pixel circuit and a second sub-pixel area overlapping a second pixel circuit, the first sub-pixel area and the second sub-pixel area each being surrounded by the groove, wherein the first pixel circuit and the second pixel circuit are located on the organic insulating layer, wherein a connection electrode CL is located on the organic insulating layer and crosses the groove, the connection electrode connecting the first pixel circuit and the second pixel circuit to each other.
Regarding claim 20, fig. 6 of Bae discloses further comprising: a buffer layer 101 located between the substrate and the first semiconductor layer, wherein the groove surrounding the sub-pixel area exposes a portion of the buffer layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893