DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 04/06/2026 Claims 1-20 are pending for this examination.
Response to Arguments
Applicant’s reply filed on 04/06/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8-11 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al (US 2016/0268264 A1; hereafter Hwang).
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Regarding claim 1. Hwang discloses a three-dimensional semiconductor memory device comprising:
a gate stack structure (Fig. [60], entire stack gate electrodes 310 and insulation pattern 115, Para [ 0081]) including insulating layers (Fig. [49-50], insulation patterns 115, Para [ 0081]), a lower selection line (gate electrodes 310 may include a ground selection line (GSL), Para [ 0086]), and word lines (gate electrodes 310 may include, a word line, Para [ 0086]), the word lines including a first word line (Fig. [49-50], gate electrodes 310 may include a word line, Para [ 0086]) close to ( examiner interpreted world line close to ground selection line [GSL]) to the lower selection line (gate electrodes 310 may include a ground selection line (GSL), Para [ 0086]) and
a second word line on the first word line (Fig. [60], another stack gate electrodes 310 include another word line, Para [ 0086]);
a memory channel structure (Fig. [60], first charge storage structure 200, the channel 210 and the filling pattern 220, Para [ 0101]) penetrating the gate stack structure (Fig. [60], stack gate electrodes 310 and insulation patterns 115, Para [ 0081]);
a plurality of first contact plugs (Fig. [60], lateral first and second contact plugs 380, Para [ 0239]) electrically connected to the first word line (Fig. [60], gate electrodes 310 may include a word line, Para [ 0086]);
a plurality of second contact plugs (stack elements [ 385, 380], construed as second plug, Para [ 0239]) electrically connected to the second word line (Fig. [49-50], another stack gate electrodes 310 include another word line, Para [ 0086]);
a first conductive line (Fig. [60], first wiring 425, Para [ 0237]) connected to the plurality of first contact plugs (Fig. [60], lateral first and second contact plugs 380, Para [ 0237-0239]); and
a second conductive line (Fig [60], wiring 420, Para [0237- 0239]) connected to one of the plurality of second contact plugs (stack elements [ 385, 380], construed as second plug, Para [ 0239]).
Regarding claim 2. Hwang discloses the three-dimensional semiconductor memory device as claimed in claim 1, Hwang further discloses wherein:
a portion of the second conductive line (Fig [60], wiring 420, Para [0237- 0239]) is connected to the one of the plurality of second contact plugs and extends in a first direction (Fig. [60], lateral first and second contact plugs 380, Para [ 0237-0239]), and a portion of the first conductive line (Fig. [60], first wiring 425, Para [ 0237]) is connected to the plurality of first contact plugs (Fig. [60], lateral first and second contact plugs 380, Para [ 0237-0239]) and extends in a second direction perpendicular to the first direction (Fig. [60], lateral first and second contact plugs 380, Para [ 0237-0239]).
Regarding claim 5. Hwang discloses the three-dimensional semiconductor memory device as claimed in claim 1, Hwang further discloses further comprising a plurality of separation structures (first insulating interlayer 130, Para [ 0103]) penetrating the gate stack structure and extending in a second direction (Fig. [60], stack gate electrodes 310 and insulation pattern 115, Para [ 0081]), and wherein at least two first contact plugs (Fig. [60], lateral first and second contact plugs 380, Para [ 0237-0239]) or at least two second contact plugs (stack elements [ 385, 380], construed as second plug, Para [ 0239]) are located between the plurality of separation structures (first insulating interlayer 130, Para [ 0103]).
Regarding claim 8. Hwang discloses the three-dimensional semiconductor memory device as claimed in claim 1, Hwang further discloses further including support structures (Fig. [60], semiconductor pattern 160, Para [ 0151]) penetrating the gate stack structure (Fig. [60], stack gate electrodes 310 and insulation pattern 115, Para [ 0081]).
Regarding claim 9. Hwang discloses the three-dimensional semiconductor memory device as claimed in claim 1, Hwang further discloses wherein the first conductive line (Fig. [60], first wiring 425, Para [ 0237]) and the second conductive line (Fig [60], wiring 420, Para [0237- 0239]) are spaced apart from each other.
Regarding claim 10. Hwang discloses a three-dimensional semiconductor memory device comprising:
a gate stack structure (Fig. [60], stack gate electrodes 310 and insulation pattern 115, Para [ 0081]) disposed on an upper surface of a substrate (substrate 100 , Para [ 0144]) and including insulating layers (Fig. [60], insulation patterns 115, Para [ 0081]) and word lines (gate electrodes 310 may include, a word line, Para [ 0086]), the word lines including a first word line corresponding to a lowermost one of the word lines (gate electrodes 310 may include, a word line, Para [ 0086]), and
a second word line on the first word line (Fig. [60], another stack gate electrodes 310 include another word line, Para [ 0086]);
a memory channel structure (Fig. [60], first charge storage structure 200, the channel 210 and the filling pattern 220, Para [ 0101]) penetrating the gate stack structure (Fig. [60], stack gate electrodes 310 and insulation pattern 115, Para [ 0081]);
a plurality of first contact plugs (Fig. [60], lateral first and second contact plugs 380, Para [ 0239]) electrically connected to the first word line (Fig. [49-50], gate electrodes 310 may include a word line, Para [ 0086]);
a plurality of second contact plugs (stack elements [ 385, 380], construed as second plug, Para [ 0239]) electrically connected to the second word line (Fig. [49-50], another stack gate electrodes 310 include another word line, Para [ 0086]);
a first conductive line (Fig. [60], first wiring 425, Para [ 0237]) connected to the plurality of first contact plugs (Fig. [60], lateral first and second contact plugs 380, Para [ 0237-0239]); and
a second conductive line (Fig [60], wiring 420, Para [0237- 0239]) connected to one of the plurality of second contact plugs (stack elements [ 385, 380], construed as second plug, Para [ 0239]).
Regarding claim 11. Hwang discloses the three-dimensional semiconductor memory device as claimed in claim 10, Hwang further discloses wherein:
the first conductive line (Fig. [60], first wiring 425, Para [ 0237]) includes a first connection portion (vertical barrier pattern 405, Para [ 0117]) connected to the plurality of first contact plug (Fig. [60], lateral first and second contact plugs 380, Para [ 0239]); and
a first extension portion (horizontal barrier pattern 405, Para [ 0117]) connected to the first connection portion (vertical barrier pattern 405, Para [ 0117]), the first connection portion (vertical barrier pattern 405, Para [ 0117]) extends in a first direction, and the first extension portion (horizontal barrier pattern 405, Para [ 0117]) extends in a second direction, the first direction and the second direction are parallel to the upper surface of the substrate (Fig. [60], substrate 100), and the first direction intersects the second direction (Fig. [60]).
Regarding claim 13. Hwang discloses the three-dimensional semiconductor memory device as claimed in claim 10, Hwang further discloses wherein the gate stack structure includes a staircase shape (Fig. [60], stack gate electrodes 310 and insulation pattern 115, Para [ 0081]) that becomes lower as a distance of the gate stack structure (Fig. [60], stack gate electrodes 310 and insulation pattern 115, Para [ 0081]) from the memory channel structure (Fig. [60], first charge storage structure 200, the channel 210 and the filling pattern 220, Para [ 0101]) increases.
Allowable Subject Matter
Claims 3-4, 14 and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 3. a dummy line between the lower selection line and the first word line; a plurality of dummy contact plugs electrically connected to the dummy line; and a dummy conductive line connected to the plurality of dummy contact plugs.
Claim 4 is objected based on the dependency of claim 3.
Regarding claim 14. The three-dimensional semiconductor memory device as claimed in claim 10, further including:
a lower selection line disposed under the first word line; a plurality of third contact plugs electrically connected to the lower selection line; and a third conductive line connected to the plurality of third contact plugs, wherein the second conductive line extends in a first direction, wherein the third conductive line extends in a second direction, and wherein the first direction intersects the second direction.
Claim 16 is objected based on the dependency of claim 14.
Regarding claim 17. a lower selection line disposed under the first word line; a plurality of third contact plugs electrically connected to the lower selection line; a third conductive line connected to the plurality of third contact plugs; a dummy line between the lower selection line and the first word line; a plurality of dummy contact plugs electrically connected to the dummy line; and a dummy conductive line connected to the plurality of dummy contact plugs.
Claim 18 is objected based on the dependency of claim 17.
Regarding claim 19. a plurality of separation structures penetrating the gate stack structure, wherein the number of the plurality of first contact plugs between the plurality of separation structures is different from the number of the plurality of second contact plugs between the plurality of separation structures.
Claim 20 is allowed.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
a plurality of second contact plugs electrically connected to the second word line; a plurality of third contact plugs electrically connected to the lower selection line; a plurality of dummy contact plugs electrically connected to the dummy line; a first conductive line connected to the plurality of first contact plugs; a second conductive line connected to one of the plurality of second contact plugs; a third conductive line connected to the plurality of third contact plugs; and a dummy conductive line connected to the plurality of dummy contact plugs, with the combination of other features, as recited in claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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