DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgment has been made to the amendment received on 02/10/2026, Claims 1-26 are pending in this application, claims 11-16 are withdrawn, claims 27-29 previously canceled. claims 1-10 and 17-22 been examined in this application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5 and 9 are under 35 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al (US10192867B1) in view Zhu et al (US20180108577A1).
Re claim1 a 1st source/drain region (S1/D1 shown in fig 7) [col 7, lines 56-59] on a substrate (320, fig 7) [col 5, lines 17] and a 2nd source/drain region (S2/D2 fig 12) [col 9, lines 10-12] on the 1st source/drain region (S1/D1, fig 12); and
a 1st source/drain contact structure (1820, fig 17) [col 10, lines 4-6] on the 1st source/drain region (S1/D1), and a 2nd source/drain contact structure (1840, fig 17) [col 10, lines 3-4] on the 2nd source/drain region (S2/D2 fig 12) [col 9, lines 10-12],
wherein the 2nd source/drain region (S2/D2, fig 12) is isolated from the 1st source/drain region (S1/D2) through an interlayer structure (810, fig 12) [col 7, lines 43-44], and
wherein a spacer (400, fig 3, 12) [col 7, lines 4-5] is formed on an upper portion (upper portion of S2/D2) of a sidewall of the 2nd source/drain contact structure (1840), between the 1st source/drain contact structure (1820, fig 17) and the 2nd source/drain contact structure (1840, fig 17).
Frougier does not teach the interlayer structure separates the 1st source/drain contact structure from the 2nd source/drain contact structure in a direction parallel to a surface of the substrate.
Zhu teaches, the interlayer structure (1035, fig 15) [0089] separates the 1st source/drain contact structure (1037-Vdd, fig 15) [0089] from the 2nd source/drain contact structure (1037-OUT, fig 15) [0089] in a direction parallel to a surface (top surface of 1001, fig 15)of the substrate (1001, fig 15) [0047].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Zhu into the structure of Frougie to include the interlayer structure separates the 1st source/drain contact structure from the 2nd source/drain contact structure in a direction parallel to a surface of the substrate as claimed.
The ordinary artisan would have been motivated to modify Frougier based on the teaching of Zhu in the above manner for the purpose of minimizing electrical cross-talk.
Re claim 5 Frougier in view of Zhu tach, the 3DSFET device of claim 1, wherein the spacer (400, fig 12) comprises a left spacer (left 400, fig 12) and a right spacer (right 400) formed on a left sidewall (left sidewall of 1840) [Frougier, col 10, lines 3-4] and a right sidewall of the 2nd source/drain contact structure (right sidewall of 1840), respectively, and
wherein one of the left spacer (left 400, fig 17) and the right spacer (right 400, fig 17) is formed between the 1st source/drain contact structure ( Frougier, 1820, fig 17) [col 10, lines 4-6] and the 2nd source/drain contact structure (1840, fig 17) [Frougier, col 10, lines 3-4].
Re claim 9 Frougier in view of Zhu teach, the 3DSFET device of claim 1, wherein the spacer (400, fig 17) surrounds the upper portion of the sidewall of the 2nd source/drain contact structure (1840, fig17) [Frougier, col 10, lines 3-4].
Claims 2-4, 6-8, 10 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier as modified by Zhu as applied to claim1 and further in view of Kim et al (US20170317079A1).
Re claim 2 Frougier in view of Zhu teach, the 3DSFET device of claim 1,
Frouiger and Zhu do not teach the spacer has an etch selectivity against the interlayer structure.
Kim teaches, the spacer (Sp1, fig 30B) [0061] has an etch selectivity against the interlayer structure (130, fig 30B) [0037]. (Based on the similar material of the instant application).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kim into the structure of Frouiger and Zhu to include the spacer has an etch selectivity against the interlayer structure as claimed.
The ordinary artisan would have been motivated to modify Frouiger and Zhu based on the teaching of Kim in the above manner for the purpose of improve an operation speed of the semiconductor device [0124].
Re claim 3 Frouiger in view of Zhu and Kim teaches, the 3DSFET device of claim 2,
wherein the spacer (Sp1, fig 30B) [Kim, 0026] has a lower etch rate than the interlayer structure (130, fig 26C) with respect to a same etchant. [Kim, 0037]
Re claim 4 Frouiger in view of Zhu and Kim teach, 3DSFET device of claim 1, wherein the spacer comprises silicon nitride (400, fig 3, 12) [col 7, lines 4-5],
Frouiger and Zhu do not teach the interlayer structure comprises silicon oxide.
Kim teaches, the interlayer structure comprises silicon oxide, (130, fig26C) [0037].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kim into the structure of Frouiger and Zhu to include the interlayer structure comprises silicon oxide as claimed.
The ordinary artisan would have been motivated to modify Frouiger and Zhu based on the teaching of Kim in the above manner for the purpose of to improve an operation speed of the semiconductor device. [0124].
Re claim 6. Froiuger in view of Zhu and Kim teach, the 3DSFET device of claim 5, wherein the spacer (SiN) (SP1, fig. 30B) [Kim, 0026] has an etch selectivity against the interlayer structure (130, fig 30B) [Kim, 0034]. (SiO2) (Based on the material of instant application).respect to a same etchant [Kim, 0037].
Re claim 7. Frouiger in view of Zhu and Kim teach the 3DSFET device of claim 6, wherein the spacer (Sp1, fig 30B) [Kim, 0026] has a lower etch rate than the interlayer structure (130, fig 26C) with respect to a same etchant. [Kim, 0037].
Re claim 8. Frouiger in view of Zhu and Kim teach the 3DSFET device of claim 5, the spacer (Sp1, fig 30B) [Kim, 0026] comprises silicon nitride (SiN) and the interlayer (130, fig 26C,30B) structure comprises silicon oxide (SiO). [Kim, 0037].
Re claim 10 Frouiger in view of Zhu and Kim teach, the 3DSFET device of claim 9, wherein
the spacer (SiN) (SP1, fig. 30B) [Kim, 0026] has an etch selectivity against the interlayer structure (130, fig 30B) [Kim, 0034]. (SiO2) (Based on the material of instant application).
Claims 17-22 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of Kim et al (US20170317079A1) and Zhu et al (US20180108577A1).
Re claim 17 Frougier teaches, a device comprising: device comprising:
a 1st contact structure (1820, fig 17) [col 9, line 62-64] connecting a three-dimensional field effect transistor (3DSFET) (1330/820, fig 17);
a 2ⁿᵈ contact structure (1840, fig 17) [col 9, line 64-67]connecting the 3DSFET (1330/820, fig 17) isolated from the 1st contact structure through an interlayer structure (810, fig 12) [col 7, lines 43-44],
wherein the 1st contact structure (1820, fig 17) [col 9, line 62-64] comprises a spacer (400, fig 3,12) formed on a sidewall (sidewall of 1820, fig 17) thereof,
wherein the spacer is formed of a dielectric material (SiN) [col 6, line 66].
Frougier does not teach the 1st contact structure connecting the 3DSFET to a voltage
source or another circuit element and the 2ⁿᵈ contact structure connecting the 3DSFET to the voltage source or another circuit element and the spacer is formed of the dielectric material different from a material forming the interlayer structure.
Kim teaches, the 1st contact structure (left CA, fig 30B ) [0055] connecting the 3DSFET (fig 30) to a voltage source or another circuit element (left DS, fig 30B) [0123] and the 2ⁿᵈ contact structure (right CA, fig 30) [055] connecting the 3DSFET to the voltage source or another circuit element (right DS, fig 30B) [0123] and the spacer (SP1, fig 30B) is formed of the dielectric material (SiN) [0026] different from a material (SiO2) forming the interlayer structure (130, fig 26C) [0037].
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Kim into the structure of Frouiger to include the 1st contact structure connecting the 3DSFET to a voltage source or another circuit element and the 2ⁿᵈ contact structure connecting the 3DSFET to the voltage source or another circuit element and the spacer is formed of the dielectric material different from a material forming the interlayer structure as claimed.
The ordinary artisan would have been motivated to modify Frouiger based on the teaching of Kim in the above manner for the purpose of improve an operation speed of the semiconductor device. [0124].
Frouiger and Kim do not teach the 3DSFET is on a substrate and the interlayer structure separates the 1st contact structure from the 2nd contact structure in a direction parallel to a surface of the substrate.
Zhu teaches the 3DSFET (p-type device + n-type device) [0049] is on a substrate (1001, fig 15) [0049] and the interlayer structure (1035, fig 15) [0078] separates the 1st contact structure (1037-Vdd, fig 15) [0089] from the 2nd contact structure (1037-OUT, fig 15) [0089] in a direction parallel to a surface of the substrate (1001, fig 15).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching taught by Frouiger and Kim into the structure Zhu of to include the 3DSFET is on a substrate and the interlayer structure separates the 1st contact structure from the 2nd contact structure in a direction parallel to a surface of the substrate as claimed.
The ordinary artisan would have been motivated to modify Frouiger and Kim based teaching of Zhu in the above manner for the purpose of minimizing electrical the crosstalk.
Re claim 18 Frouiger in view of Kim and Zhu teach, the 3DSFET device of claim 17 ,
wherein the spacer (400, fig 17) is formed on an upper portion of the sidewall of the 2nd contact structure (1840, fig17) [Frougier, col 10, lines 3-4].
Re claim 19 Frouiger in view of Kim and Zhu teach the 3DSFET device of claim 17, wherein the spacer (SiN) (SP1, fig. 30B) [Kim, 0026] has an etch selectivity against the interlayer structure (130, fig 30B) [Kim, 0034] (SiO2) (Based on the material of instant application).
Re claim 20 Frouiger in view of Kim and Zhu teach, the 3DSFET device ofclaim17, wherein the spacer (SiN) (SP1, fig 30B) [Kim 0026] has a greater dielectric constant than the interlayer structure (130, fig 30B) (Based on the material of the material of the instant application).
Re claim 21. Frouiger in view of Kim and Zhu teach, the 3DSFET device of claim 17,
wherein the 1st contact structure (1820, fig 17) [col 9, lines 65-66] is a lower source/drain contact structure (1820) formed on a lower source/drain region (S1/D1 shown in fig 7) [Frougier, col 7, lines 56-59] of the 3DSFET (Fig17), and the 2nd contact structure (1840, fig 17) is an upper source/drain contact structure formed on an upper source/drain region [(S1/D1 shown in fig 7) [Frougier, col 7, lines 56-59] of the 3DSFET.
Re claim 22. Frouiger in view Kim and Zhuteaches, the 3DSFET device of claim 17,
wherein the spacer (Sp1, fig 30B) [Kim, 0026] comprises silicon nitride (SiN) and the interlayer (130, fig 26C, 30B) structure comprises silicon oxide (SiO) [Kim, 0037].
Response to Arguments
Applicant’s arguments with respect to claims 1-10 and 17-22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRATIKSHA J LOHAKARE whose telephone number is (571)270-1920. The examiner can normally be reached Monday - Friday 7.30 am-4.30 pm.
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/PRATIKSHA JAYANT LOHAKARE/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 2/25/26