Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/23/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 59-62, 64-65, 71, 74, 79, 82, 85 and 87 are rejected under 35 U.S.C. 103 as being anticipated unpatentable over “Park” (US 10,863,627) in view of “Reynov” (US 9,585,259).
Regarding claim 59, Park discloses 59. A method of making a circuit board core material by:
providing a laminate comprising a resin or resin-glass prepreg and a first clad layer directly on a first side of said prepreg (Fig. 3, col. 4, lines 32-50, col. 6, lines 18-22; the core structure 110 is provided as a laminate comprising the insulating layers 111a-c made of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, or a material including a glass fiber (glass cloth, glass fabric), the first wiring layer 112A, which includes the metal layer 115a and the first pattern layer 112a, is a first clad layer directly on a first side of said prepreg layer);
forming a pocket in said prepreg (Fig. 3, col. 4, lines 32-50; the prepreg layer is formed and comprises a pocket);
inserting an electronic component in said pocket of said prepreg wherein said electronic component comprises a first external termination and a second external termination (Fig. 3, col. 4, lines 32-50; the electronic component 120A is inserted in the pocket of the prepreg, and comprises the connection electrode 122a which is a first external termination, and the connection electrode 123a which is a second external termination);
curing said prepreg to form prepreg with said electronic component in said prepreg (Fig. 3, col. 4, lines 32-50, col. 11, lines 1-28; the thermosetting resin is cured to form the prepreg with the electronic component 120A in the prepreg);
forming a first electrical connection by laminating said first external termination to said first clad layer; and forming a second electrical connection to said second external termination (Fig. 3, col. 4, lines 32-50; the connection electrode 122a which is a first external termination is laminated to and in electrical contact with the first wiring layer 112A, and the connection electrode 123a which is a second external termination is laminated to and in electrical contact with the via 113b which is a conductor).
Park does not disclose the circuit board core material is free of vias providing an electrical connection to the electronic component.
Reynov discloses the circuit board core material is free of vias providing an electrical connection to the electronic component (Figs. 5, 7, 11, claim 1, col. 17, lines 3-10; the components 840′ and 845′ being electrically coupled directly to the circuit lines 850 and 855, respectively, the second portion 827 of the PCB 800 can be devoid of signal vias and ground vias).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure with Reynov’s core material is free of vias in order to have a component density and a cross-talk greater than and less than, respectively, a component density and a cross talk of the first portion 826 of the PCB, as suggested by Reynov at col. 17, lines 7-10.
Regarding claim 60, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 60. The method of claim 59 wherein said laminate further comprises a second clad layer and said forming said second electrical connection includes laminating said second external termination to said second clad layer (Fig. 3, col. 4, lines 32-50; the second wiring layer 112B, which includes the metal layer 115b and the second pattern layer 112b, is a second clad layer on a second side opposite said first side and the connection electrode 123a is laminated to the second wiring layer 112B).
Regarding claim 61, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 61. The method of claim 59 further laminating at least one printed circuit board to said circuit board core material (Fig. 3, col. 4, lines 32-50, col. 5, lines 30-33; the first and second wiring layers 112A and 112B including at least portions of the first and second metal layers 115a and 115b are printed circuit boards).
Regarding claim 62, Park in view of Reynov discloses the claimed invention as applied to claim 61, above.
Park discloses 62. The method of claim 61 further comprising forming at least one via in said printed circuit board (Fig. 3, col. 5, lines 32-50; the via 113a is a via formed in the printed circuit board).
Regarding claim 64, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 64. The method of claim 59 wherein said electronic component is selected from the group consisting of capacitor, resistor, silicon die, diode, inductive material and magnetic device (Fig. 3, col. 4, lines 32-50; the electronic component 120A is a ceramic capacitor).
Regarding claim 65, Park in view of Reynov discloses the claimed invention as applied to claim 64, above.
Park discloses 65. The method of claim 64 wherein said capacitor is selected from a foil capacitor, a pressed powder capacitor and a ceramic capacitor (Fig. 3, col. 4, lines 32-50; the electronic component 120A is a ceramic capacitor).
Regarding claim 71, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 71. The method of claim 59 wherein said first external termination is a counter electrode (Fig. 3, col. 4, lines 32-50; the connection electrode 122a is a counter electrode).
Regarding claim 74, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 74. The method of claim 59 wherein said first clad layer comprises copper (Fig. 3, col. 8, lines 66-67; the first wiring layer 112A includes the metal layer 115a which is copper).
Regarding claim 79, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 79. The method of claim 59 further comprising a via pass through section (Fig. 3, col. 5, lines 32-50; the via 113a is a via pass through section).
Regarding claim 82, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 82. The method of making a circuit board of claim 59 comprising multiple electronic components (Fig. 4, col. 10, line 25; the second electronic component 160 is on the circuit board).
Regarding claim 85, Park anticipates 85. The method of claim 59 further comprising forming a prepreg layer laminated on opposite side of electronic component from first clad layer (Fig. 3, col. 9, line 41; the passivation layer 140 is a prepreg layer laminated on opposite side of electronic component 120a from the metal layer 115a).
Regarding claim 87, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park discloses 87. The method of claim 59 wherein said circuit board core material is flexible (Fig. 3, col. 9, line 41; the circuit board core material is flexible).
Claims 66-70 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Reynov and “Takahashi” (US 2019/0392997).
Regarding claim 66, Park in view of Reynov discloses the claimed invention as applied to claim 64, above.
Park does not disclose the limitations of claim 66.
Takahashi discloses 66. The method of claim 64 wherein said capacitor comprises a porous valve metal layer (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Takahashi’s capacitor in order to suppress an increase in ESR and an increase in leakage current as suggested by Takahashi at Abstract.
Regarding claim 67, Park in view of Reynov and Takahashi discloses the claimed invention as applied to claim 66, above.
Park does not disclose the limitations of claim 67.
Takahashi discloses 67. The method of claim 66 wherein said capacitor comprises a dielectric on said porous valve metal layer (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
Regarding claim 68, Park in view of Reynov and Takahashi discloses the claimed invention as applied to claim 66, above.
Park does not disclose the limitations of claim 68.
Takahashi discloses 68. The method of claim 66 wherein said porous valve metal layer is selected from the group consisting of aluminum, tantalum, niobium and NbO (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
Regarding claim 69, Park in view of Reynov and Takahashi discloses the claimed invention as applied to claim 66, above.
Park does not disclose the limitations of claim 69.
Takahashi discloses 69. The method of claim 66 wherein said porous valve metal layer is a foil (Figs. 1-2, [0019]; the capacitor comprises a porous valve metal layer foil made from tantalum, aluminum or niobium).
Regarding claim 70, Park in view of Reynov and Takahashi discloses the claimed invention as applied to claim 66, above.
Park does not disclose the limitations of claim 70.
Takahashi discloses 70. The method of claim 66 wherein said capacitor comprises a capacitor core (Fig. 3, col. 4, lines 32-50; the electronic component 120A is a ceramic capacitor comprising a capacitor core).
Claims 72-73 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Reynov and “Nishino” (US 4,737,889).
Regarding claim 72, Park in view of Reynov discloses the claimed invention as applied to claim 71, above.
Park does not disclose the limitations of claim 72.
Nishino discloses 72. The method of claim 71 further comprising a conductive paint on said counter electrode (Fig. 1, col. 7, lines 45-62; the conductive paint, which has carbon and a resin as a binding medium is on the electrode).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Nishino’s conductive paint in order to make the conductive layer and the conditions of electrolyte, casing, etc., about the same capacitor value as that of the example, while the impedances of the present embodiment show larger values in comparison, because the metal conductive layer has stronger bonding to the polarizable electrode body and because of having difference of resistance values of the conductive body per se, as suggested by Nishino at col. 7, lines 45-62.
Regarding claim 73, Park in view of Reynov and Nishino discloses the claimed invention as applied to claim 72, above.
Park does not disclose the limitations of claim 73.
Nishino discloses 73. The method of claim 72 wherein said conductive paint comprises at least one of a carbon filled resin or a metal filled resin (Fig. 1, col. 7, lines 45-62; the conductive paint, which has carbon and a resin as a binding medium is on the electrode).
Claims 75-78 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Reynov and “Salcedo” (US 2006/0151836).
Regarding claim 75, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park does not disclose the limitations of claim 75.
Salcedo discloses 75. The method of claim 59 further comprising a cathode isolation region (claim 14, the electrostatic discharge (ESD) device comprises a cathode comprising a cathode isolation region).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Salcedo’s isolation region in order to provide for an electrostatic discharge protection device for applications with input/output bipolar voltage higher than the core circuit power supply, as suggested by Salcedo at Abstract.
Regarding claim 76, Park in view of Reynov and Salcedo discloses the claimed invention as applied to claim 75, above.
Park does not disclose the limitations of claim 76.
Salcedo discloses 76. The method of claim 75 further wherein said cathode isolation region comprises an isolation material (claim 14, the electrostatic discharge (ESD) device comprises a cathode comprising a cathode isolation region having an isolation material of a length of L1).
Regarding claim 77, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park does not disclose the limitations of claim 77.
Salcedo discloses 77. The method of claim 59 further comprising an anode isolation region (claim 17, the electrostatic discharge (ESD) device comprises an anode comprising an anode isolation region).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Salcedo’s isolation region in order to provide for an electrostatic discharge protection device for applications with input/output bipolar voltage higher than the core circuit power supply, as suggested by Salcedo at Abstract.
Regarding claim 78, Park in view of Reynov and Salcedo discloses the claimed invention as applied to claim 77, above.
Park does not disclose the limitations of claim 78.
Salcedo discloses 78. The method of claim 77 further wherein said anode isolation region comprises an isolation material (claim 17, the electrostatic discharge (ESD) device comprises an anode comprising an anode isolation region having an isolation material of a length of L2).
Claims 80-81 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Reynov and “Hahn” (US 2018/0211790).
Regarding claim 80, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park does not disclose the limitations of claim 80.
Hahn discloses 80. The method of claim 59 further comprising a conductive node (Figs. 2-3, [0021]; the conductive node, 28, is in electrical contact with the anode lead, 14).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Hahn’s anode conductive node in order to provide a preferred conductive path due to a resistance which is lower than the resistance of the current path through the dielectric 16, as suggested by Hahn at [0021].
Regarding claim 81, Park in view of Reynov and Hahn discloses the claimed invention as applied to claim 80, above.
Park does not disclose the limitations of claim 81.
Hahn discloses 81. The method of claim 80 wherein said conductive node is an anode conductive node (Figs. 2-3, [0021]; the conductive node, 28, is in electrical contact with the anode lead, 14).
Claims 83-84 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Reynov and “Naito” (US 2017/0169957).
Regarding claim 83, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park does not disclose the limitations of claim 83.
Naito discloses 83. The method of claim 59 further comprising forming at least one clad bonding layer (Figs. 3-4, [0102]; the conductive adhesive layer 410 is between the adjacent external terminal 400 and the counter electrode 20).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Naito’s bonding layer in order to obtain a high capacitance even with a small number of times of polymerization treatments, as suggested by Naito at Abstract.
Regarding claim 84, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park does not disclose the limitations of claim 84.
Naito discloses 84. The method of claim 59 further comprising forming at least one electrical connection layer between adjacent clad layer (Figs. 3-4, [0102]; the conductive adhesive layer 410 is between the adjacent external terminal 400 and the counter electrode 20).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Naito’s bonding layer in order to obtain a high capacitance even with a small number of times of polymerization treatments, as suggested by Naito at Abstract.
Claim 86 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Reynov and “Kim” (US 9,664,842).
Regarding claim 86, Park in view of Reynov discloses the claimed invention as applied to claim 59, above.
Park does not disclose the limitations of claim 86.
Kim discloses 86. The method of claim 59 further comprising etching said first clad layer (Fig. 11, col. 10, lines 25-32; the clad layer 130a is etched).
It would have been obvious to a person having ordinary skill in the art, before the effective filing date of the claimed invention, to have constructed Park’s structure, as modified by Reynov, with Kim’s etching in order to form a circuit portion based on a designed pattern form, as suggested by Kim at col. 10, lines 25-32.
Conclusion
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/STANLEY TSO/Primary Examiner, Art Unit 2847
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