Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the species where the interface insulating film comprises silicon oxide in the reply filed on 01/09/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2020/0212068 in view of Yoo, U.S. Patent 10,720,437.
Lee et al. shows the invention substantially as claimed including a semiconductor memory device, comprising:
A conductive layer on a substrate (see, for example, paragraph 0025);
An insulating isolation layer 105 on the conductive layer;
A stack structure on the insulating isolation layer, the stack structure comprising a plurality of source/drain contact layers 150a-150d and a plurality of gate electrode layers 160a-160d alternately provided along a first direction, perpendicular to an upper surface of the substrate;
A vertical channel layer 230 extending through the stack structure and the insulating isolation layer, wherein the vertical channel layer is in contact with each of the plurality of source/drain contact layers; and
A gate insulating layer 161-162 between each of the plurality of gate electrode layers and the vertical channel layer (see paragraphs 0021-0035, 0045-0055 and figs. 2, 5, and 7, for example).
Lee et al. does not expressly disclose the vertical channel layer being connected to the conductive layer. Yoo discloses a ferroelectric memory cell including a vertical channel 150 that is directly connected to a conductive layer 105 overlying the substrate (see col. 6-lines 45-50, col. 8-lines 47-55 and fig. 2, for example). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Lee et al. so as to comprise the channel/conductive layer configuration of Yoo because in such a way the channel can be used as a path of charge conduction between the conductive layer and drain electrode.
Concerning dependent claims 2 and 15, note that Lee et al. also discloses wherein the gate insulating layer comprises a ferroelectric film 162 and an interface insulating film 161 between the ferroelectric film and the vertical channel layer.
Regarding dependent claims 3-4, note that in Lee et al. the ferroelectric film can be zirconium oxide (see paragraph 0031) and the interface insulating film can comprise silicon oxide (see paragraph 0028).
With respect to dependent claim 5, note that Lee et al. further discloses wherein the gate insulating layer comprises a horizontal insulating portion between the plurality of source/drain contact layers and the plurality of gate electrode layers.
Concerning dependent claim 6, note that Lee et al. discloses the vertical channel comprises polysilicon doped with a first conductivity type impurity (see paragraph 0040).
Regarding dependent claim 7, note that Lee et al. also discloses that the vertical channel comprises source/drain regions 135 that are doped with a second conductivity type and are in contact with the plurality of source/drain contact layers (for example, 150---see paragraph 0068).
With respect to dependent claims 8-9, the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the conductive layer of polysilicon doped with a first conductivity type impurity and the insulating isolation layer comprising aluminum oxide because the claimed polysilicon is a well-known conductive layer and aluminum oxide is a well-known insulating isolation layer commonly used in semiconductor device manufacturing.
Concerning dependent claim 10, when giving the claim its broadest reasonable interpretation the vertical channel comprises a plurality of vertical channel layers since the vertical channel of Lee et al. can be arbitrarily divided into an infinite number of small layers.
As to dependent claim 11, Lee et al. discloses an isolation structure 240 extending in a second direction, parallel to the upper surface of the substrate, to separate the stack structure into a plurality of device regions, wherein at least one vertical channel layer of the plurality of vertical channel layers 230 is provided in each of the plurality of device regions.
Regarding dependent claim 12, note that Lee et al. discloses the vertical channel has a cylindrical structure and the stack structure surrounds a side surface of the vertical channel layer (see figs. 1-2 of Lee et al.) .
With respect to dependent claim 13, note that Lee et al. discloses a core insulating portion 140 extending through the vertical channel layer 130 in the first direction, wherein the vertical channel layer surrounds a side surface of the core insulating portion (see fig. 2).
As to independent claim 14, Lee et al. shows the invention substantially as claimed including a semiconductor memory device, comprising:
A conductive layer on a substrate and doped with an impurity (see, for example, paragraph 0025 and note that inherently the active devices will inherently contain impurity doping);
An insulating isolation layer 105 on the conductive layer;
A plurality of source/drain contact layers (150a-150d) on the insulating isolation layer, and spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate;
A plurality of gate electrode layers 160a-160d respectively disposed between the plurality of source/drain contact layers;
A vertical channel layer 230 extending through the plurality of source/drain contact layers, the plurality of gate electrode layers, and the insulating isolation layer, and doped with a first conductivity type impurity in a first concentration;
Source/drain regions (for example, 235---see fig. 5) of the vertical channel layer that are doped with a second conductivity type impurity and are in contact with the plurality of source/drain contact layers; and a plurality of gate insulating layers (161,162) between side surfaces of the plurality of gate electrode layers and the vertical channel layer, and between the plurality of gate electrode layers and the plurality of source/drain contact layers (see paragraphs 0021-0035, 0045-0055 and figs. 2, 5, and 7, for example).
Lee et al. does not expressly disclose the vertical channel layer being connected to the conductive layer. Yoo discloses a ferroelectric memory cell including a vertical channel 150 that is directly connected to a conductive layer 105 overlying the substrate (see col. 6-lines 45-50, col. 8-lines 47-55 and fig. 2, for example). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Lee et al. so as to comprise the channel/conductive layer configuration of Yoo because in such a way the channel can be used as a path of charge conduction between the conductive layer and drain electrode.
With respect to dependent claim 16, note that in the memory device of Lee et al. modified by Yoo the vertical channel layer comprises an end portion in the conductive layer since it will be connected to the conductive layer.
Concerning dependent claim 17, the examiner takes official notice that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to form the channel layer and conductive layer comprising polysilicon with a first conductivity type impurity because doped polysilicon is well known for a conductive layer due to its high conductivity and as a channel layer due to its high mobility.
Regarding dependent claim 18, note that Lee et al. discloses a ground line connected to source contact layers (see paragraph 0036), word lines connected to gate electrode layers (see paragraph 0033), and a bit line connected to drain contact layers (see claim 3).
As to dependent claim 19, Lee et al. and Yoo are applied as above but do not expressly disclose a channel bias line connected to the conductive layer. However, official notice is taken that it would have been obvious to one of ordinary skill in the art at the time the invention was filed to connect a channel bias line to the channel/conductive layer in order to provide increased control over the memory device operation.
Regarding independent claim 20, Lee et al. shows the invention substantially as claimed including a semiconductor memory device, comprising:
A conductive layer on a substrate;
An insulating isolation layer 105 on the conductive layer;
A first stack structure 3a on the insulating isolation layer 105, the first stack structure comprising a plurality of first source/drain contact layers 250a-250c arranged to be spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate, and at least one first gate electrode layer 260a-260b respectively between the plurality of first source/drain contact layers;
A second stack structure 3b on the first stack structure, the second stack structure comprising a plurality of second source/drain contact layers 250d-250f arranged to be spaced apart from each other in the first direction, and at least one second gate electrode layer 260c-260d respectively between the plurality of second source/drain contact layers;
A device isolation film 370 between the first stack structure and the second stack structure;
A vertical channel layer 230 extending through the first stack structure, the second stack structure, the device isolation film, in contact with each of the plurality of first and second source/drain contact layers; and
A gate insulating layer (261,262) between each of the at least one first gate electrode layer and the vertical channel layer, and between each of the at least one second gate electrode layer and the vertical channel layer (see paragraphs 0021-0035, 0045-0055 and figs. 2 and 5 and particularly fig. 7 and its description).
Lee et al. does not expressly disclose the vertical channel layer being connected to the conductive layer. Yoo discloses a ferroelectric memory cell including a vertical channel 150 that is directly connected to a conductive layer 105 overlying the substrate (see col. 6-lines 45-50, col. 8-lines 47-55 and fig. 2, for example). In view of this disclosure, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the device of Lee et al. so as to comprise the channel/conductive layer configuration of Yoo because in such a way the channel can be used as a path of charge conduction between the conductive layer and drain electrode.
Conclusion
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/RICHARD A BOOTH/ Primary Examiner, Art Unit 2812
March 1, 2026