DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-20 in the reply filed on 12/02/2025 is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, claim 1 subject matter that the that first bonding pads electrically connected to the pixel regions must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 11-15,18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US Pub No. 20150255495).
With respect to claim 11, Park discloses a substrate (110,Fig.1b) having a frontside surface (FS) and a backside surface (BS) ;pixel regions formed in the substrate (121); light isolation patterns formed among the pixel regions (130); and bonding pads electrically connected to the pixel regions (like FE),wherein the light isolation patterns are electrically connected to at least one of the bonding pads (Fig.1b).
With respect to claim 12, Park discloses wherein the substrate has trenches formed among the pixel regions (Fig.5K) from the backside surface of the substrate toward the frontside surface of the substrate (Fig.5K), and the light isolation patterns are formed in the trenches (Fig.1b).
With respect to claim 13, Park discloses wherein the trenches are connected with one another and arranged in a lattice form (Fig.1A).
With respect to claim 14, Park discloses wherein the light isolation patterns are connected with one another and arranged in a lattice form (Fig.1A-B).
With respect to claim 15, Park discloses an anti-reflective layer (170) formed on the backside surface of the substrate and inner surfaces of the trenches.
With respect to claim 18, Park discloses a light blocking pattern layer (FE and horizontal portion of the 141b) having openings corresponding to the pixel regions (Fig.1b) and formed on the light isolation patterns (Fig.1b), wherein the light isolation patterns are connected to the at least one of the bonding pads through the light blocking pattern layer (Fig.1b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US Pub No. 20150255495), in view of Lin et al (US Pub No. 20210225918).
With respect to claim 1, Park discloses a substrate (110,Fig.1b) having a frontside surface (next to 155) and a backside surface (next to 170) ;pixel regions (121) formed in the substrate ; light isolation patterns formed among the pixel regions (133); first bonding pads (150, Fig.1A); and at least one second bonding pad electrically connected to the light isolation patterns (140). However, Park does not explicitly disclose first bonding pads electrically connected to the pixel regions. On the other hand, Lin et al discloses first bonding pads (BB,CP, Fig.10) electrically connected to the pixel regions (through 150). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Park according to the teachings of the Lin et al such that bonding pads are connected to the pixel regions, in order to be able turn on the transistors in the pixel region for processing the light captured by the pixel regions.
With respect to claim 2, Park discloses wherein the substrate has trenches formed among the pixel regions (130) from the backside surface of the substrate toward the frontside surface of the substrate (Fig.1B), and the light isolation patterns are formed in the trenches (131,-133).
With respect to claim 3, Park discloses wherein the trenches are connected with one another and arranged in a lattice form (Fig.1A-B).
With respect to claim 4, Park discloses wherein the light isolation patterns are connected with one another and arranged in a lattice form (Fig.1A-B).
With respect to claim 5, Park discloses an anti-reflective layer (170, 130T, para 53) formed on the backside surface of the substrate (170 portion) and inner surfaces of the trenches (Fig.1B).
With respect to claim 6, Park in view of Lin et al discloses further comprising: an insulating layer (155) formed on the frontside surface of the substrate (Fig.1A); and electrode pads formed on the insulating layer (BB,CP on 140) and electrically connected to the pixel regions (Fig.10),wherein the first bonding pads are connected to the electrode pads through via holes penetrating the substrate and the insulating layer (Fig.10).
With respect to claim 7, Park discloses: an anti-reflective layer formed on the backside surface of the substrate (170); and a backside insulating layer formed on the anti-reflective layer (175), inner side surfaces of the via holes (151H,Fig.5J) and surface portions of the electrode pads (161b) exposed by the via holes (Fig.5J), wherein the first bonding pads are formed on the backside insulating layer and connected to the electrode pads through the backside insulating layer (Fig.5B).
With respect to claim 8, Park discloses a light blocking pattern layer having openings corresponding to the pixel regions (FE portion, Fig.1b) and formed on the light isolation patterns (Fig.1b) ,wherein the light isolation patterns are connected to the at least one second bonding pad through the light blocking pattern layer (from the right most one, Fig.1b).
With respect to claim 9, Park discloses wherein the light isolation patterns are made of a same material as the light blocking pattern layer (Fig.1b).
With respect to claim 16, Park discloses an insulating layer formed on the frontside surface of the substrate (155); and electrode pads (161). However, wherein the bonding pads are connected to the electrode pads through via holes (150) penetrating the substrate and the insulating layer (Fig.1B). However, Park does not explicitly disclose and electrode pads are electrically connected to the pixel regions. On the other hand, Lin et al discloses and electrode pads formed on the insulating layer (BB,CP on 140) and electrically connected to the pixel regions (Fig.10).
With respect to claim 17, Park discloses an anti-reflective layer (top portion of FE protruding from the trench) formed on the backside surface of the substrate; and a backside insulating layer formed on the anti-reflective layer (175), inner side surfaces of the via holes and surface portions of the electrode pads exposed by the via holes (Fig.1B), wherein the bonding pads are formed on the backside insulating layer (Fig.1b) and connected to the electrode pads through the backside insulating layer (Fig.1b). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Park according to the teachings of the Lin et al such that bonding pads are connected to the pixel regions, in order to be able turn on the transistors in the pixel region for processing the light captured by the pixel regions.
Claim(s) 10,19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park (US Pub No. 20150255495), in view of Lin et al (US Pub No. 20210225918), in view of Takemmura et al (US Pub No. 20180159059).
With respect to claim 10, Park discloses further comprising: a backside insulating layer formed on the light blocking pattern layer (175),wherein the at least one second bonding pad is formed on the backside insulating layer (Fig.1B). However, the arts cited above do not explicitly disclose and connected to the light blocking pattern layer through the backside insulating layer. On the other hand, Takemura et al discloses wiring layer (15b2) is connected to a plug (120b2), through insulating layer (14). It would have been obvious to one of ordinary skill in the art at the time of the fling of the invention to modify the arts cited above according to the teachings of the Takemura et al such that the bonding pad is connected to the light blocking pattern layer through the backside insulating layer, in order to decrease the width of the device, thereby the manufacturing cost is lessened.
With respect to claim 19, Park discloses a backside insulating layer (175) formed on the light blocking pattern layer (fig1b), wherein the bonding pads are formed on the backside insulating layer (Fig.1b). However, Park does not explicitly disclose and the at least one of the bonding pads is connected to the light blocking pattern layer through the backside insulating layer. On the other hand, Takemura et al discloses wiring layer (15b2) is connected to a plug (120b2), through insulating layer (14). It would have been obvious to one of ordinary skill in the art at the time of the fling of the invention to modify the arts cited above according to the teachings of the Takemura et al such that the bonding pad is connected to the light blocking pattern layer through the backside insulating layer, in order to decrease the width of the device, thereby the manufacturing cost is lessened.
With respect to claim 20, Park discloses a passivation layer (180) formed on the bonding pads and the backside insulating layer (Fig.1b).
Conclusion
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/ALI NARAGHI/Primary Examiner, Art Unit 2817