DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 12/22/2025, in which claims 1, 11, 17 were amended, claims 6-7, 13-15 were withdrawn, has been entered.
Drawings
The drawings were received on 12/22/2025. These drawings are acceptable.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application KR10-20220102924 filed on 08/17/2022. The foreign application is not in English. The certified copy of the foreign priority application KR10-20220102924 and an English translation of the non-English language foreign application KR10-20220102924 and a statement that the translation is accurate in accordance with 37 CFR 1.55 have been received.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 8-11, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US Pub. 20180286314) in view of Wu et al. (US Pub. 20200185416).
Regarding claims 1-3, Cho et al. discloses in Fig. 1, Fig. 3-Fig. 6, Fig. 11, paragraph [0004], [0007]-[0008], [0012], [0020], [0021], [0022], [0055], [0075]-[0076], [0079], [0080], [0117] a display device comprising:
a substrate [110]; and
a plurality of pixels on the substrate [110], each pixel of plurality of pixels comprising:
a light-emitting diode [OLED] disposed on the substrate [100];
a driving transistor [T1] disposed on the substrate [100], electrically connected to the light- emitting diode [OLED], the driving transistor [T1] being singular and comprising:
a plurality of channel areas [131a1, 131a2 and 131a’];
a gate electrode [155a];
a first terminal [136a] configured to receive a driving power supply voltage; and
a second terminal [137a] configured to transmit the driving power supply voltage to the light-emitting diode in response to a voltage of the gate electrode [155a];
wherein the plurality of channel areas [131a1, 131a2 and 131a’] comprises a first channel area [131a’] and a second channel area [131a1 or 131a2].
Cho et al. fails to disclose
a plurality of lower metal layers arranged between the substrate and the driving transistor and overlapping the plurality of channel areas, respectively;
wherein the plurality of lower metal layers is spaced apart from each other;
the plurality of lower metal layers comprises:
a first lower metal layer, which overlaps the first channel area and to which a first voltage is applied; and
a second lower metal layer, which overlaps the second channel area and to which a second voltage having a different magnitude from a magnitude of the first voltage is applied.
Wu et al. discloses in Fig. 1, Fig. 22, paragraph [0050], [0052], [0059]
a plurality of lower metal layers [11 left and 11 right] or [17 and 11] arranged between the substrate [10] and the driving transistor and overlapping the plurality of channel areas, respectively;
wherein the plurality of lower metal layers [11 left and 11 right] or [17 and 11] is spaced apart from each other;
the plurality of lower metal layers [11 left and 11 right] or [17 and 11] comprises:
a first lower metal layer [11 right][Fig. 1] or [11][Fig. 22], which overlaps the first channel area [13 right] and to which a first voltage is applied; and
a second lower metal layer [11 left] [Fig. 1] or [17][Fig. 22], which overlaps the second channel area [13 left] and to which a second voltage having a different magnitude from a magnitude of the first voltage is applied.
It is noted that the limitation “configured to receive a driving power supply voltage”, “configured to transmit the driving power supply voltage to the light-emitting diode in response to a voltage of the gate electrode”, “to which a first voltage is applied” and “to which a second voltage having a different magnitude from a magnitude of the first voltage is applied” direct to manner of operation of the device and intended use of the claimed features. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 (II). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this case, Wu et al. discloses all the structural limitations of the claimed metal layers and the metal layers disclosed by Wu et al. capable of performing the intended use, then it meets the claim.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Wu et al. into the method of Cho et al. to include a plurality of lower metal layers arranged between the substrate and the driving transistor and overlapping the plurality of channel areas, respectively; wherein the plurality of lower metal layers is spaced apart from each other; the plurality of lower metal layers comprises: a first lower metal layer, which overlaps the first channel area and to which a first voltage is applied; and a second lower metal layer, which overlaps the second channel area and to which a second voltage having a different magnitude from a magnitude of the first voltage is applied. The ordinary artisan would have been motivated to modify Cho et al. in the above manner for the purpose of providing a light shielding structure to shield the channel areas from the external light. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 8 and 19, Cho et al. discloses in Fig. 11, paragraph [0117]
wherein a ratio of a width of the second channel area [131a1] to a length [L2] of the second channel area [131a1] is greater than a ratio of a width of the first channel area [131a’] to a length [L1] of the first channel area [131a’].
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Regarding claim 9, Cho et al. discloses in Fig. 4, Fig. 5
a gate conductive layer [155a-f] disposed on the driving transistor [TR1-1, TR1-2], wherein the gate conductive layer [155a] overlaps the plurality of channel areas [131a1, 131a2].
Regarding claim 10, Cho et al. discloses in Fig. 5, paragraph [0072] wherein the driving transistor comprises a silicon semiconductor layer [130].
Regarding claims 11 and 20, Fig. 1, Fig. 3-Fig. 6, Fig. 11, paragraph [0004], [0007]-[0008], [0012], [0020], [0021], [0022], [0055], [0072], [0075]-[0076], [0079], [0080], [0117] a display device comprising:
a substrate [110]; and
a plurality of pixels on the substrate [110], each pixel of plurality of pixels comprising:
a driving transistor [T1] disposed on the substrate [100] and comprising a silicon semiconductor layer [130], the driving transistor [T1] being singular and comprising:
a first channel area [131a2 or 131a’][Fig. 3, Fig. 4, Fig. 11];
a second channel areas [131a1][Fig. 3, Fig. 4, Fig. 11];
a gate electrode [155a];
a first terminal [136a] configured to receive a driving power supply voltage; and
a second terminal [137a] configured to transmit the driving power supply voltage to the light-emitting diode in response to a voltage of the gate electrode [155a];
a gate conductive layer [155a-f] including the gate electrode [155a] disposed on the silicon semiconductor layer [130].
Cho et al. fails to disclose
a first lower metal layer disposed on the substrate;
a second lower metal layer disposed on the substrate and spaced apart from the first lower metal layer;
the driving transistor disposed on the first lower metal layer and the second lower metal layer;
wherein the first channel area overlapping the first lower metal layer and the second channel area overlapping the second lower metal layer;
wherein the first lower metal layer and the second lower metal layer comprise a same material.
Wu et al. discloses in Fig. 1, Fig. 22, paragraph [0050], [0052], [0059]
a first lower metal layer [11 right][Fig. 1] or [11][Fig. 22] disposed on the substrate [10];
a second lower metal layer [11 left][Fig. 1] or [17][Fig. 22] disposed on the substrate [10] and spaced apart from the first lower metal layer [11 right][Fig. 1] or [11][Fig. 22];
the driving transistor disposed on the first lower metal layer [11 right][Fig. 1] or [11][Fig. 22] and the second lower metal layer [11 left] [Fig. 1] or [17][Fig. 22];
wherein the first channel area [13 right] overlapping the first lower metal layer [11 right][Fig. 1] or [11][Fig. 22], and the second channel area [13 left] overlapping the second lower metal layer [11 left] [Fig. 1] or [17][Fig. 22];
wherein the first lower metal layer [11 right][Fig. 1] or [11][Fig. 22] and the second lower metal layer [11 left][Fig. 1] or [17][Fig. 22] comprise a same material [paragraph [0059]].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Wu et al. into the method of Cho et al. to include a first lower metal layer disposed on the substrate; a second lower metal layer disposed on the substrate and spaced apart from the first lower metal layer; the driving transistor disposed on the first lower metal layer and the second lower metal layer; wherein the first channel area overlapping the first lower metal layer and the second channel area overlapping the second lower metal layer; wherein the first lower metal layer and the second lower metal layer comprise a same material. The ordinary artisan would have been motivated to modify Cho et al. in the above manner for the purpose of providing a light shielding structure to shield the channel areas from the external light. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 16, Cho et al. discloses in Fig. 8
the gate conductive layer [105 and/or 130] overlaps the first channel area [150] and the second channel area [170].
Regarding claim 17, the limitation of claim 17 “configured to receive a first voltage”, “configured to receive a second voltage greater than the first voltage” direct to manner of operation of the device and intended use of the claimed features. A claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP 2114 (II). A recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
In this case, Wu et al. discloses all the structural limitations of the claimed metal layers and the metal layers disclosed by Wu et al. capable of performing the intended use, then it meets the claim.
Regarding claim 18, Cho et al. discloses in paragraph [0072]-[0073]
wherein the driving transistor [T1] is a p-channel metal oxide semiconductor [“The semiconductor 130 may include a polycrystalline semiconductor such as polysilicon, or an oxide semiconductor” and “The semiconductor 130 includes a channel doped with an N-type impurity or a P-type impurity”].
Claims 4-5 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. (US Pub. 20180286314) in view of Wu et al. (US Pub. 20200185416) as applied to claim 3 and claim 11 above and further in view of Zhang (US Pub. 20210408194) and Kwak et al. (US Pub. 20210175311).
Regarding claims 4, 5, and 12 Cho et al. and Wu et al. fails to disclose
wherein the first lower metal layer and the second lower metal layer are arranged in different layers;
wherein the first lower metal layer and the second lower metal layer overlap each other.
Zhang discloses in Fig. 17-Fig. 18, paragraph [0071]
wherein the first lower metal layer [11] and the second lower metal layer [18] are arranged in different layers [the third light-shielding layer 18 and a first light-shielding layer 11 are disposed in a same layer… In other embodiments, the third light-shielding layer 18 may also be provided in a different layer from a first light-shielding layer 11];
wherein the first lower metal layer [110] and the second lower metal layer [18 and 111] overlap each other.
For further providing support for an arrangement of metal layers, Kwak et al. is cited.
Kwak discloses in Fig. 7D, paragraph [0113], [0121]
a first metal layer [SHL1] and the second metal layer [SHL2] are arranged in different layers;
the first metal layer [SHL1] and the second metal layer [SHL2] overlap each other.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Zhang and Kwak into the method of Cho et al. and Wu et al. to include wherein the first lower metal layer and the second lower metal layer are arranged in different layers; wherein the first lower metal layer and the second lower metal layer overlap each other. The ordinary artisan would have been motivated to modify Cho et al. and Wu et al. in the above manner for the purpose of providing suitable alternative arrangement of the first lower metal layer and the second lower metal layer. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 8-12, 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
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/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
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