DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/13/2026 has been entered.
Claims 1-20 are pending and have been examined.
Response to Amendments
Applicant's response of 01/23/2026 has been acknowledged. Claims 1 and 11 have been amended. No new matter has been added.
This office action considers claims 1-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 01/23/2026 with respect to the rejections of claims have
been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-3, 6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20130270526 A1 – hereinafter Kim) in view of Jung et al. (US 20200098795 A1 – hereinafter Jung).
Regarding independent claim 1, Kim teaches
(Currently Amended) A display apparatus (1 – [0028] – “display
apparatus 1”) comprising:
a substrate (10 – Fig. 2 – [0029] – “substrate 10”) including a trench substrate
(Fig. 2 annotated, see below – hereinafter ‘TR’);
a capacitor (Cst1 – Fig. 2 – [0041] – “capacitor Cst1”) disposed on the
substrate (10) in the trench (10a – Fig. 2 – [0041] – “first trench 10a”);
a bottom metal layer disposed on the substrate and spaced apart from the
capacitor, wherein the bottom metal layer is a metal layer including at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu)
a thin-film transistor comprising an active layer on the bottom metal layer, wherein the thin-film transistor is spaced apart from the bottom metal layer in a thickness direction of the substrate,
wherein the capacitor (Cst1) includes a first metal layer (31a - Fig. 6 – [0043] – “first capacitor lower electrode 31a”), a second metal layer (35a - Fig. 6 – [0043] – “second electrode units 33a and 35a”), and an inorganic insulating layer (12 – Fig. 6 – [0054] – “gate insulating layer 12 may be formed by vapor depositing an inorganic insulating layer”),
the first metal layer is disposed in a same layer as the bottom metal layer,
the first metal layer (ML1) is the metal layer including the at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu)
the second metal layer disposed on the first metal layer, and
the inorganic insulating layer is disposed between the first metal layer and the second metal layer and between the bottom metal layer and the active layer of the thin-film transistor, and
the second metal layer is disposed in a same layer as the active layer of the thin-film transistor.
Kim does not expressly disclose the limitations of claim 1.
However, in an analogous art, Jung teaches
a bottom metal layer (110 – Fig. 9E – [0133] – “a first metal layer” – this
corresponds to a bottom metal layer) disposed on the substrate (101 – Fig. 9E – [0063] – “substrate 101”) and spaced apart from the capacitor (Cap – Fig. 9E – [0132] – “storage capacitor area Cap”), wherein the bottom metal layer (110) is a metal layer including at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) ([0133] – “a first metal layer, which has a double-layer structure including a Mo metal layer 1201a and a Cu metal layer 1201b, is deposited on the substrate 101 and is selectively removed, with the result that a pad electrode of the first-layer line 114 is formed in the pad portion, a light-shielding layer 110 is formed in the thin-film transistor area)
a thin-film transistor ( TFT – Fig. 9E – [0148] – “thin-film transistor area TFT”) comprising an active layer (152a – Fig. 9E – [0136] – “active layer 152a”) on the bottom metal layer (110), wherein the thin-film transistor (TFT – Fig. 9E – [0148] – “thin-film transistor area TFT”) is spaced apart from the bottom metal layer (110) in a thickness direction of the substrate (101),
the first metal layer (Fig. 9E annotated, see below – [0133] – “a first metal layer, which has a double-layer structure including a Mo metal layer 1201a and a Cu metal layer 1201b … a first storage electrode 111 is formed in the storage capacitor area Cap … The Cu metal layer 1201b may be substituted by aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), or neodymium (Nd)” – hereinafter ‘FML’) is disposed in a same layer (FML contains 1201a and 1201b which is also contained in 110, thus they are disposed in the a same layer (151) – Fig. 9E shows this) as the bottom metal layer (110),
the first metal layer (ML1) is the metal layer including the at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) ([0133] – “a first metal layer, which has a double-layer structure including a Mo metal layer 1201a and a Cu metal layer 1201b … a first storage electrode 111 is formed in the storage capacitor area Cap … The Cu metal layer 1201b may be substituted by aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), or neodymium (Nd)” – hereinafter ‘FML’),
the second metal layer (152c – Fig. 9E – [0136] – “a semiconductor material layer, such as an oxide semiconductor, a polysilicon, or an amorphous silicon, which includes at least one metal selected from the group consisting of Zn, Cd, Ga, In, Sn, Hf, and Zr, is deposited on the light-shielding layer 110, and is then selectively removed, with the result that a first active layer 152a and 152b and a second active layer 152c are formed on a predetermined portion above the light-shielding layer 110 and on a predetermined portion above the first storage electrode 111”) disposed on the first metal layer (FML), and
the inorganic insulating layer (151 – Fig. 9E – [0137] – “buffer layer 151”) is disposed between the first metal layer (FML) and the second metal layer (152c) and between the bottom metal layer (110) and the active layer (152a) of the thin-film transistor (TFT), and
the second metal layer (152c) is disposed in a same layer (154 – Fig. 9E – [0140] – “interlayer insulation film 154”) as the active layer (152a) of the thin-film transistor (TFT).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by Jung into Kim.
An ordinary artisan would have been motivated to use the known technique of Jung in the manner set forth above to produce the predictable result to [0090] – “prevent adverse effects attributable to leakage of light to the side portion of the exposure boundary region and consequently may prevent loss of the first overlapping patterns 1400 in the exposure boundary region (the region near the scribing line), which is influenced by multiple exposure shots.”
Regarding claim 2, Kim, as modified by Jung, teaches claim 1 from which claim 2 depends. Kim further teaches
(Original) The display apparatus of claim 1, wherein a portion of the
capacitor (Cst1) has a shape corresponding to a shape of the trench (10a – Fig. 2 shows this).
Regarding claim 3, Kim, as modified by Jung, teaches claim 1 from which claim 3 depends. Kim further teaches
(Original) The display apparatus of claim 1, wherein the second metal
layer (35a) includes titanium (Ti) (25a – Fig. 5 – [0056] – “second conduction layer 25a may include one or more materials selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, MoW, and Cu” – 35a is layer 25a after removal).
Regarding claim 6, Kim, as modified by Jung, teaches claim 1 from which claim 6 depends. Kim further teaches
(Original) The display apparatus of claim 1, wherein the trench (10a –
Fig 2) is provided in plural (Fig. 2 shows this with trenches 10a and 10b, these are plural trenches).
Regarding claim 10, Kim, as modified by Jung, teaches claim 1 from which claim 10 depends. Kim does not expressly disclose the limitations of claim 10.
However, in an analogous art, Jung teaches
(Original) The display apparatus of claim 1, wherein the thin-film transistor
(TFT) includes an oxide semiconductor ([0136] – “a semiconductor material layer, such as an oxide semiconductor, a polysilicon, or an amorphous silicon, which includes at least one metal selected from the group consisting of Zn, Cd, Ga, In, Sn, Hf, and Zr, is deposited on the light-shielding layer 110, and is then selectively removed, with the result that a first active layer 152a and 152b and a second active layer 152c are formed on a predetermined portion above the light-shielding layer 110 and on a predetermined portion above the first storage electrode 111”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the oxide semiconductor TFT structure as taught by Jung into Kim.
An ordinary artisan would have been motivated to use the known technique of Jung in the manner set forth above to produce the predictable result of a smaller, faster, and more efficient transistor.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 4, 11-15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung and Wang et al. (US 20210336046 A1 – hereinafter Wang).
Regarding claim 4, Kim, as modified by Jung, teaches claim 1 from which claim 4 depends. Kim further teaches
the second metal layer (35a),
corresponding to the trench (10a).
Kim and Jung do not expressly disclose the other limitations of claim 4.
However, in an analogous art, Wang teaches
(Original) The display apparatus of claim 1, further comprising:
a filling layer (200 – Fig. 8 – [0064] – “a fill layer 200 can be formed in the
trenches 180”) disposed on the second metal layer and filling a region on the
second metal layer corresponding to the trench,
wherein the filling layer (200) includes a spin-on-glass (SOG) material
([0064] – “fill layer 200 can be formed by a blanket deposition (e.g., CVD, PECVD, spin-on)” – therefore 200 is a spin-on material).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the spin-on material structure as taught by Wang into Kim and Jung.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable result deposition the material in the trenches only.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding independent claim 11, Kim teaches
(Currently Amended) A display apparatus (1 – [0028] – “display
apparatus 1”) comprising:
a substrate (10 – Fig. 2 – [0029] – “substrate 10”) including a trench (10a – fig.
2 – [0041] – “first trench 10a”);
a capacitor (Cst1 – Fig. 2 – [0041] – “capacitor Cst1”) on the substrate (10),
wherein the capacitor (Cst1) includes a first metal layer (31a - Fig. 6 – [0043] – “first capacitor lower electrode 31a”), an inorganic insulating layer (12 – Fig. 6 – [0054] – “gate insulating layer 12 may be formed by vapor depositing an inorganic insulating layer”), and a second metal layer (35a - Fig. 6 – [0043] – “second electrode units 33a and 35a”) sequentially disposed on the substrate (10) along a shape of the trench (10a – Fig. 6 shows this), wherein the first metal layer is a metal layer including at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu)
a thin-film transistor comprising an active layer on the substrate; and
a filling layer disposed on the second metal layer (35a) and filling a region
on the second metal layer (35a) corresponding to the trench (10a),
wherein the filling layer includes a spin-on-glass (SOG) material, and
the second metal layer is disposed in a same layer as the active layer of the thin-film transistor.
Kim does not expressly disclose the other limitations of claim 11.
However, in an analogous art, Jung teaches
the first metal layer ([0133] – “a first metal layer – hereinafter ‘FML’) is a metal layer including at least one selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) ([0133] – “a first metal layer, which has a double-layer structure including a Mo metal layer 1201a and a Cu metal layer 1201b … a first storage electrode 111 is formed in the storage capacitor area Cap … The Cu metal layer 1201b may be substituted by aluminum (Al), chrome (Cr), gold (Au), nickel (Ni), or neodymium (Nd)” – hereinafter ‘FML’);
a thin-film transistor ( TFT – Fig. 9E – [0148] – “thin-film transistor area TFT”) comprising an active layer (152a – Fig. 9E – [0136] – “active layer 152a”) on the substrate (101 – Fig. 9E – [0063] – “substrate 101”),
the second metal layer (152c) is disposed in a same layer (154 – Fig. 9E – [0140] – “interlayer insulation film 154”) as the active layer (152a) of the thin-film transistor (TFT).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the metal layer structure as taught by Jung into Kim.
An ordinary artisan would have been motivated to use the known technique of Jung in the manner set forth above to produce the predictable result as stated above in claim 1.
Kim and Jung do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Wang teaches
a filling layer (200 – Fig. 8 – [0064] – “a fill layer 200 can be formed in the
trenches 180”),
wherein the filling layer (200) includes a spin-on-glass (SOG) material ([0064] – “fill layer 200 can be formed by a blanket deposition (e.g., CVD, PECVD, spin-on)” – therefore 200 is a spin-on material).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the filling layer structure and SOG technique as taught by Wang into Kim and Jung.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable result of deposition the material in the trenches only.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 12, Kim, as modified by Jung and Wang, teaches claim 11 from which claim 12 depends. Kim and Wang do not expressly disclose the limitations of claim 12.
However, in an analogous art, Jung teaches
(Original) The display apparatus of claim 11, further comprising:
a thin-film transistor (TFT) disposed on the substrate (101).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the transistor structure and as taught by Jung into Kim and Wang.
An ordinary artisan would have been motivated to use the known technique of Wang in the manner set forth above to produce the predictable result of creating a transistor for a display apparatus.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Regarding claim 13, Kim, as modified by Jung and Wang, teaches claim 12 from which claim 13 depends. Kim and Wang do not expressly disclose the limitations of claim 13.
However, in an analogous art, Jung teaches
(Original) The display apparatus of claim 12, wherein the thin-film transistor
(TFT) includes an oxide semiconductor ([0136] – “a semiconductor material layer, such as an oxide semiconductor, a polysilicon, or an amorphous silicon, which includes at least one metal selected from the group consisting of Zn, Cd, Ga, In, Sn, Hf, and Zr, is deposited on the light-shielding layer 110, and is then selectively removed, with the result that a first active layer 152a and 152b and a second active layer 152c are formed on a predetermined portion above the light-shielding layer 110 and on a predetermined portion above the first storage electrode 111”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the oxide semiconductor TFT structure as taught by Jung into Kim.
An ordinary artisan would have been motivated to use the known technique of Jung in the manner set forth above to produce the predictable result as stated above in claim 10.
Regarding claim 14, Kim, as modified by Jung and Wang, teaches claim 13 from which claim 14 depends. Kim and Wang do not expressly disclose the other limitations of claim 14.
However, in an analogous art, Jung teaches
(Original) The display apparatus of claim 13, further comprising:
a bottom metal layer (110 – Fig. 9E – [0133] – “a first metal layer” – this corresponds to a bottom metal layer) between the substrate (101) and the thin-film transistor (101 – Fig. 9E shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the bottom metal layer positioning as taught by Jung into Kim and Wang.
An ordinary artisan would have been motivated to use the known technique of Jung in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 15, Kim, as modified by Jung, and Wang, teaches claim 14 from which claim 15 depends. Kim and Wang do not expressly disclose the limitations of claim 15.
However, in an analogous art, Jung teaches
(Original) The display apparatus of claim 14, wherein the first metal layer
(FML) is disposed in a same layer (154 – Fig. 9E – [0140] – “interlayer insulation film 154”) as the bottom metal layer (110 – Fig. 9E annotated, see below, shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first metal and bottom metal layers structure as taught by Jung into Kim and Wang.
An ordinary artisan would have been motivated to use the known technique of Jung in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 18, Kim, as modified by Jung and Wang, teaches claim 11 from which claim 18 depends. Kim further teaches
(Original) The display apparatus of claim 11, wherein the trench (10a
– Fig 2) is provided in plural (Fig. 2 shows this with trenches 10a and 10b, these are plural trenches).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung and Cho (US 20150236080 A1 – hereinafter Cho).
Regarding claim 5, Kim, as modified by Jung, teaches claim 1 from which claim 5 depends. Kim further teaches
the trench (10a).
Kim and Jung do not expressly disclose the other limitations of claim 5.
However, in an analogous art, Cho teaches
(Original) The display apparatus of claim 1, wherein the trench has an
elliptical shape in a plan view (363 – Fig. 5 – [0087] – “the trench 363 can be formed in a polygonal shape substantially the same as that of the contact region CA, a circular shape or an elliptical shape” – hereinafter ‘TES’).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the trench shape as taught by Cho into Kim and Jung.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result of [0008] – “where the trench can deform a path of an external light” therefor resulting in [0007] – “display panel having an improved visibility.”
Regarding claim 7, Kim, as modified by Jung, teaches claim 6 from which claim 7 depends. Kim further teaches
(Original) The display apparatus of claim 6, wherein each of a plurality of trenches (10a) has an elliptical shape in a plan view, and the trenches are apart from each other (Fig. 2 shows trenches 10a and 10b apart from each other) in the plan view (Fig. 1 shows this with Cst1 and Cst2).
Kim and Jung do not expressly disclose the other limitations of claim 7.
However, in an analogous art, Cho teaches
an elliptical shape in a plan view (TES).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the trench shape as taught by Cho into Kim and Jung.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 5.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung and Tian et al. (US 20160358949 A1 – hereinafter Tian).
Regarding claim 8, Kim, as modified by Jung, teaches claim 1 from which claim 8 depends. Kim and Jung do not expressly disclose the limitations of claim 8.
However, in an analogous art, Tian teaches
(Original) The display apparatus of claim 1, wherein the second metal layer
(23 – Fig. 2 – [0040] – “second metal layer 23”) is connected to a connection electrode layer (24 – Fig. 2 – [0044] – “connection electrode 24” – this is in the connection electrode layer) disposed on the thin-film transistor (10 – Fig. 2 – [0036] – “a TFT structure 10”) through a contact hole ([0025] – “the second metal layer is electrically connected to the connection electrode layer through a via hole”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second metal layer structure as taught by Tian into Kim and Jung.
An ordinary artisan would have been motivated to use the known technique of Tian in the manner set forth above to produce the predictable result of [0028] – “to obtain such a capacitor structure of the GOA circuit in which the insulation layer arranged between the two metal layers functioning as two electrodes of the capacitor is of a small thickness and the areas of the two metal layers are reduced, while the capacitance value of the capacitor is unaffected. Therefore, the area of the GOA circuit may be reduced, and the flat panel display with the narrower bezel may be obtained.”
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung, Tian, An (US 20200409496 A1 – hereinafter An), and Su et al. (US 20160126300 A1 – hereinafter Su).
Regarding claim 9, Kim, as modified by Jung, and Tian, teaches claim 8 from which claim 9 depends. Kim, Jung, and Tian do not expressly disclose the limitations of claim 9.
However, in an analogous art, An teaches
(Original) The display apparatus of claim 8, wherein
the connection electrode layer (70 – Fig. 1a – [0028] – “planarization layer 70”
– this corresponds to a connection electrode layer) includes a data line (61 – Fig. 2 – [0032] – “data lines 61”), and
the second metal layer is electrically connected to the data.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection electrode and data line structure as taught by An into Kim, Jung, and Tian.
An ordinary artisan would have been motivated to use the known technique of An in the manner set forth above to produce the predictable result of [0006] – “to provide a touch display panel capable of solving the problem that a short circuit is easily generated when touch lines and data lines are simultaneously formed in a touch display panel in the prior art.”
Kim, Jung, Tian, and An do not expressly disclose the other limitations of claim 9.
However, in an analogous art, Su teaches
the second metal layer is electrically connected to the data line ([Claim 13] –
“the second metal layer fills into the contact opening and is electrically connected to the data line”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the connection electrode and data line connection as taught by Su into Kim, Jung, Tian, and An.
An ordinary artisan would have been motivated to use the known technique of Su in the manner set forth above to produce the predictable result of preventing [0006] – “an insulating layer formed overlying the metal traces in the peripheral region may be too thin to effectively isolate two metal traces underlying and overlying the insulating layer, respectively. Thus, a short may occur between the two metal traces, negatively and seriously affecting the operation of the display panel. Moreover, because the metal traces in the peripheral region have a relatively large area, high stress may be generated in the metal traces.”
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung, Wang, and Tian.
Regarding claim 16, Kim, as modified by Jung and Wang, teaches claim 12 from which claim 16 depends. Kim, Jung, and Wang do not expressly disclose the limitations of claim 16.
However, in an analogous art, Tian teaches
(Original) The display apparatus of claim 12, further comprising:
a connection electrode layer (24 – Fig. 2 – [0044] – “connection electrode 24” –
this is in the connection electrode layer) disposed on the second metal layer (23 – Fig. 2 – [0040] – “second metal layer 23”) and the thin-film transistor (10 – Fig. 2 – [0036] – “a TFT structure 10”), wherein the connection electrode layer (24) is electrically connected to the second metal layer ([0025] – “the second metal layer is electrically connected to the connection electrode layer through a via hole”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second metal layer structure as taught by Tian into Kim, Jung, and Wang.
An ordinary artisan would have been motivated to use the known technique of Tian in the manner set forth above to produce the predictable result of [0028] – “to obtain such a capacitor structure of the GOA circuit in which the insulation layer arranged between the two metal layers functioning as two electrodes of the capacitor is of a small thickness and the areas of the two metal layers are reduced, while the capacitance value of the capacitor is unaffected. Therefore, the area of the GOA circuit may be reduced, and the flat panel display with the narrower bezel may be obtained.”
Regarding claim 17, Kim, as modified by Jung and Wang, teaches claim 16 from which claim 17 depends. Kim further teaches
(Original) The display apparatus of claim 16, wherein the second
metal layer includes a same material as a material of the connection electrode layer ( ([0008] – “first capacitor upper electrode and the second capacitor upper electrode may include the same material forming the pixel electrode” – the capacitor upper electrode corresponds to the second metal layer and the pixel electrode corresponds to the connection electrode).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung, Wang, and Cho.
Regarding claim 19, Kim, as modified by Jung and Wang, teaches claim 18 from which claim 19 depends. Kim further teaches
(Original) The display apparatus of claim 18, wherein
each of a plurality of trenches (10a) has an elliptical shape in a plan view , and the trenches are apart from each other (Fig. 2 shows trenches 10a and 10b apart from each other) in the plan view (Fig. 1 shows this with Cst1 and Cst2).
Kim, Jung and Wang do not expressly disclose the other limitations of claim 19.
However, in an analogous art, Cho teaches
each of a plurality of trenches has an elliptical shape in a plan view (363 – Fig.
5 – [0087] – “the trench 363 can be formed in a polygonal shape substantially the same as that of the contact region CA, a circular shape or an elliptical shape” – hereinafter ‘TES’).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the trench shape as taught by Cho into Kim, Jung and Wang.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 5.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jung, Wang, Tian, Cho, and Yamazaki et al. (US 20110058116 A1 – hereinafter Yamazaki).
Regarding claim 20, Kim, as modified by Jung, Wang, and Tian, teaches claim 16 from which claim 20 depends. Kim, Jung, Wang, and Tian do not expressly disclose the limitations of claim 20.
However, in an analogous art, Cho teaches
(Original) The display apparatus of claim 16, further comprising:
a pixel electrode (171 – Fig. 2 – [0069] – “first electrode 171” – this corresponds
to a pixel electrode) disposed on the connection electrode layer;
a pixel-defining layer (167 – Fig. 2 – [0070] – “pixel definition portion 167”)
disposed on the pixel electrode (171), wherein an opening (DA – Fig. 2 – [0071] – “pixel region DA” – this defines an opening) is defined through the pixel-defining layer (167) to expose a portion of the pixel electrode (171);
an intermediate layer filling (173 – Fig. 2 – [0067] – “light-emitting layer 173”) the opening (DA); and
an opposite electrode (175 – fig. 2 – [0067] – “second electrode 175”) disposed on the intermediate layer (173).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel structure as taught by Cho into Kim, Jung, Wang, and Tian.
An ordinary artisan would have been motivated to use the known technique of Cho in the manner set forth above to produce the predictable result as stated above in claim 5.
Kim, Jung, Wang, Tian, and Cho do not expressly disclose the other limitations of claim 20.
However, in an analogous art, Yamazaki teaches
disposed on the connection electrode layer (9c – Fig. 1D – {[0122] – “connection electrode layer 9c”)}, {[0018] – “connection electrode layer may be provided between the pixel electrode layer and the drain electrode layer”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel structure as taught by Yamazaki into Kim, Jung, Wang, Tian, and Cho.
An ordinary artisan would have been motivated to use the known technique of Yamazaki in the manner set forth above to produce the predictable result [0005] – “excellent switching characteristics (e.g., a high on-off ratio) are required for a thin film transistor in the pixel portion, and a high operation speed is required for a thin film transistor in the driver circuit. The thin film transistor in the driver circuit preferably operates at high speed as the definition of a display device is increased, because writing time of a display image is reduced particularly.”
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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