Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/31/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election of claims 1-8 and 16-20 with traverse in the reply filed on 07/21/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP 818.01 (a)).
The traversal is on the ground(s) that there is no examination burden.
The Examiner finds that this argument is not persuasive. This is because the Examiner’s argument pertaining to the mutual exclusivity of Species 1 and Species 2 is not addressed by a statement that there is no examination burden.
Therefore, the Examiner will examine claims 1-8 and 16-20.
The requirement is still deemed proper and is therefore made FINAL.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4 recites the limitation, “along a bottom surface of the first gate structure and second gate structure”. The Examiner believes the limitation should recite, “along a bottom surface of the first gate structure and the second gate structure”. This is so that the limitation is grammatically correct.
. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 2,
Claim 2 recites the limitation, “the dielectric wall comprises a second dielectric layer along one or more edges of the dielectric wall”. The Examiner finds that this limitation is indefinite because a portion of the dielectric wall cannot be along one or more edges of the entire dielectric wall. The Examiner interprets claim 2 as meaning, “the dielectric wall comprises a second dielectric layer and a dielectric fill; wherein the second dielectric layer is along one or more edges of the dielectric fill”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al US 20200098681 A1. Kim et al will be referenced to as Kim henceforth.
Regarding Claim 1,
Kim teaches:
“An integrated circuit (FIGs. 11-13) comprising:
a first semiconductor region extending in a first direction (channel layers CP (leftmost), [0060], [0059], FIG. 13: A first direction is in the X-direction. One of ordinary skill in the art would understand that a channel has source/drain regions on its ends. This is necessary for the function of a transistor. FIGs. 12 and 13 are spaced apart along the X-direction.) from a first source or drain region (source/drain layers SG’ (leftmost), [0059], FIG. 12);
a second semiconductor region extending in the first direction (channel layers CP (rightmost), [0060], [0059], FIG. 13: A first direction is in the X-direction. One of ordinary skill in the art would understand that a channel has source/drain regions on its ends. This is necessary for the function of a transistor. FIGs. 12 and 13 are spaced apart along the X-direction.) from a second source or drain region (source/drain layers SG’ (leftmost), [0059], FIG. 12), the second source or drain region spaced from the first source or drain region in a second direction different from the first direction (FIG. 12: The SG’ regions are spaced apart in the Y-direction.);
a first gate structure around the first semiconductor region and a second gate structure around the second semiconductor region (gate structures GSP’, [0064], FIG. 13: The left GSP’ is a first gate structure. The right GSP’ is a second gate structure.);
a dielectric layer beneath the first gate structure and the second gate structure (device isolation layer 15, [0031], FIG 13);
a dielectric wall between the first semiconductor region and the second semiconductor region and extending in the first direction (gate isolation pattern 80, etch stop layer 58, [0044], [0059], FIGs. 11-13: 80 extends in the X direction in FIG. 11.) such that the dielectric wall extends between the first gate structure and the second gate structure (FIG. 11, FIG. 13: 80 extends in the X direction while being between the first and the second gate structures.);
a first contact on a top surface of the first source or drain region (contact plug 92a (the contact pad portion), [0065], annotated FIG. 12 #1) and a second contact on a top surface of the second source or drain region (contact plug 92b, [0065], FIG. 12); and
a conductive structure extending through an entire thickness of the dielectric layer and along an entire thickness of the first source or drain region and the second source or drain region to contact one or both of the first contact and the second contact (contact plug 92a (the conductive structure portion), buried conductive layer 13, [0042], annotated FIG. 12 #1),
wherein a portion of the conductive structure also extends in the first direction between the first gate structure and the second gate structure (FIG. 11, FIG. 13: The buried conductive structure lies underneath 80.).”
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Regarding Claim 2,
Kim teaches:
“The integrated circuit of claim 1, wherein the dielectric layer is a first dielectric layer (15 may also be considered a first dielectric layer.), and the dielectric wall comprises a second dielectric layer along one or more edges of the dielectric wall (etch stop layer 58, [0044], FIG. 12: 58 is along the bottom edge of 80.) and a dielectric fill in a remaining volume of the dielectric wall (80 is the rest of the dielectric wall).”
Regarding Claim 4,
Kim teaches:
“The integrated circuit of claim 1, wherein the first gate structure and the second gate structure each include a gate dielectric around the first semiconductor region (gate insulation layer GI’, [0064], FIG. 13) and the second semiconductor region and along a bottom surface of the first gate structure and second gate structure (FIG. 13: GI’ is on a bottom of GP’.).”
Claims 1, 3, and 6-7 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mignot et al US 20240332182 A1. Mignot et al will be referenced to as Mignot henceforth.
Regarding Claim 1,
Mignot teaches:
“An integrated circuit comprising:
a first semiconductor region extending in a first direction (nanosheet channels 209 (leftmost in FIG. 6), [0018], [0021], FIGs. 3-8: The first direction is along line 6.) from a first source or drain region (source/drain structures 206.2, [0047], FIG. 6);
a second semiconductor region extending in the first direction (nanosheet channels 209 (rightmost in FIG. 6), [0018], [0021], FIGs. 3-8: The first direction is along line 6.) from a second source or drain region (source/drain structures 506, [0047], FIGs. 3-8), the second source or drain region spaced from the first source or drain region in a second direction different from the first direction ([0018], FIG. 5: lines 6 and 5 are orthogonal. 206.2 and 506 are spaced apart along line 5.);
a first gate structure around the first semiconductor region and a second gate structure around the second semiconductor region (gate 208, [0013], FIG. 4: The first gate structure is on the left side. The second gate structure is on the right side.);
a dielectric layer beneath the first gate structure and the second gate structure (shallow trench isolation 414, [0021], FIG. 4);
a dielectric wall between the first semiconductor region and the second semiconductor region and extending in the first direction (dielectric spacer 416, [0024], FIGs. 3-4: 416 extends along the same direction as line 6 in FIG. 3.) such that the dielectric wall extends between the first gate structure and the second gate structure (FIGs. 3-6: 416 extends along the direction of line 6 in a region between the first gate structure and the second gate structure. This region is between lines 4 and 5 in FIG. 3.);
a first contact on a top surface of the first source or drain region (source/drain contacts 2CA2, [0027], FIGs. 3-6) and a second contact on a top surface of the second source or drain region (contact 5CA, [0017], FIG. 5); and
a conductive structure extending through an entire thickness of the dielectric layer and along an entire thickness of the first source or drain region and the second source or drain region to contact one or both of the first contact and the second contact (backside power rail 408, recessed via RV, [0054], FIGs. 3-6: The conductive structure directly contacts the first contact.),
wherein a portion of the conductive structure also extends in the first direction between the first gate structure and the second gate structure (FIGs. 3-6: 408 and RV extend with 416.).”
Regarding Claim 3,
Mignot teaches:
“The integrated circuit of claim 1, wherein the first semiconductor region comprises a plurality of first semiconductor nanoribbons (209 is a nanosheet. Nanosheets are the same as nanoribbons.) and the second semiconductor region comprises a plurality of second semiconductor nanoribbons (209 is a nanosheet. Nanosheets are the same as nanoribbons.).”
Regarding Claim 6,
Mignot teaches:
“The integrated circuit of claim 1, wherein the conductive structure comprises a same conductive material as both the first contact and the second contact ([0017], [0027]: RV may comprise W. 2CA1 and 5CA may comprise W.)”
Regarding Claim 7,
Mignot teaches:
“The integrated circuit of claim 1, wherein the conductive structure contacts a surface of the dielectric wall between the first gate structure and second gate structure (FIGs. 3-6).”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claims 1, 2 and 4 above, and further in view of Wei US 20230067354 A1.
Regarding Claim 8,
Kim teaches:
“the integrated circuit of claim 1”
Kim doesn’t substantially teach:
“A printed circuit board”
However, Wei teaches:
“A printed circuit board (Wei: motherboard 502, [0073-0074]: An integrated circuit is incorporated into a PCB.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Kim is modifiable in view of Wei by incorporating the integrated circuit of Kim into the PCB of Wei.
This is because one of ordinary skill in the art would be motivated to find a way of incorporating an integrated circuit into a larger device usable by people. Wei teaches that an integrated circuit may be incorporated into a PCB of a computing system which is usable by people.
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 5,
Kim fails to explicitly teach:
“wherein the conductive structure contacts the gate dielectric beneath the first gate structure and second gate structure” In view of the rest of the limitations of claim 1.
Kim fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because the buried conductive structure does not contact the gate dielectric beneath the first gate structure. Contact plug 92a is not in contact with the gate structure.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Kim to reach all of the limitations of the claim.
Claims 16-20 are allowed. The following is the Examiner’s reasoning for allowance
Regarding Claim 16,
Kim/Mignot fails to explicitly teach:
“a conductive structure extending from the first and second contacts and a bottom surface of the third dielectric wall” together with the limitation, “a second source or drain region laterally adjacent to the second dielectric wall” In view of the rest of the limitations of claim 16.
Kim/Mignot fails to explicitly teach the above limitation because the limitation cannot be found in the prior art of record.
This is because Kim/Mignot do not have enough dielectric walls to meet the limitations of claim 16
The art closest to meeting claim 16 that the Examiner found is Kim #2 et al US 20240339453 A1. Kim # 2 et al will be referenced as Kim #2 henceforth.
Kim #2 does not meet the above limitations because the conductive structure of Kim extending from the second contact of Kim cannot be construed as being adjacent to the second dielectric wall of Kim. The source/drain contact adjacent to the second dielectric wall does not have a conductive structure. Mignot does not remedy these deficiencies.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Kim/Mignot to reach all of the limitations of the claim.
Regarding Claims 17-20, these claims depend on claim 16 and are allowable for the same reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Prosecution Insights