DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 19, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0341447 A1 to Siemieniec et al. (hereinafter “Siemieniec ‘447” – previously cited reference) in further view of US 2008/0135931 A1 to Challa et al. (hereinafter “Challa” – previously cited reference).
Regarding claim 1, Siemieniec ‘447 discloses a wide band gap semiconductor device, comprising:
a semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction (SiC semiconductor body 100 having first and second opposing horizontal surfaces 101, 102; Fig. 6; paragraph [0047]);
a plurality of trench gate structures extending into the semiconductor body from the first surface, the plurality of trench gate structures including a gate electrode structure and a gate dielectric structure arranged between the gate electrode structure and the semiconductor body (gate structure 150 formed into trench extending from surface 101 and having gate electrode 155 separated from body 100 by gate dielectric 159; Fig. 6; paragraph [0046]);
a plurality of mesa regions, wherein a first sidewall of a trench gate structure of the plurality of trench gate structures adjoins a first mesa region of the plurality of mesa regions, and a second sidewall of the trench gate structure adjoins a second mesa region of the plurality of mesa regions (first mesa 181 adjacent left sidewall 151 of gate structure 150 and second mesa 182 adjacent right sidewall 152 of gate structure 150; Fig. 6; paragraphs [0067]-[0068]), wherein the first mesa region includes a body region of a first conductivity type adjoining the first sidewall, wherein the second mesa region includes a shielding region of the first conductivity type (mesa 181 comprises p-type body region 120 adjacent left sidewall and mesa 182 having shielding area 161; Fig. 6; paragraph [0053]), wherein a bottom side of the shielding region has a larger first vertical distance to the first surface than a bottom side of the body region in the first mesa region (shielding area 161 disposed further away from surface 101 than body region 120; Fig. 6), wherein the gate dielectric structure is arranged between the gate electrode structure and the body region (gate dielectric 159 disposed between gate electrode 155 and body region 120; Fig. 6).
Siemieniec ‘447 fails to disclose the gate dielectric structure including a high-k dielectric layer, wherein the high-k dielectric layer is arranged between the gate electrode structure and the body region; wherein the dielectric structure further includes a first dielectric layer arranged between the high-k dielectric layer and the body region, the first dielectric layer having a dielectric constant that is smaller than the dielectric constant of the high-k dielectric layer and is equal to or larger than the dielectric constant of SiO2.
However, Challa discloses the gate dielectric structure including a high-k dielectric layer, wherein the high-k dielectric layer is arranged between the gate electrode structure and the body region (gate dielectric layer 226 may utilize high-k material and may be disposed between gate electrode 210 and each of body region 204, n+ source 212, and p+ shield region 218; Fig. 2A; paragraphs [0118]-[0120], [0204]); wherein the dielectric structure further includes a first dielectric layer arranged between the high-k dielectric layer and the body region, the first dielectric layer having a dielectric constant that is smaller than the dielectric constant of the high-k dielectric layer and is equal to or larger than the dielectric constant of SiO2 (dielectric layer 222 disposed between high-k gate dielectric layer 226 and portion of body region 204, where dielectric materials for the layers 222, 226 may have higher dielectric constant than silicon dioxide; Fig. 2A; paragraphs [0118]-[0120], [0204]).
Siemieniec ‘447 and Challa are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Challa in order to potentially provide higher gate capacitance and better channel control for a given dielectric thickness, reduced gate leakage and improved long-term stability under high-voltage blocking, better field distribution across interfaces with nearby semiconductor structures and regions, improved interface quality, complementary dielectric properties to high-k dielectric materials, and thermal oxidation compatibility.
Regarding claim 22, Siemieniec ‘447 in view Challa discloses the transistor device of claim 1. Siemieniec ‘447 further discloses wherein the shielding region adjoins at least part of the second sidewall (shielding area 161 may adjoin second sidewall 152 of gate structure 150; paragraph [0066]), and wherein the gate dielectric structure is arranged between the gate electrode structure and the shielding region (gate dielectric 159 disposed between gate electrode 155 and body region 120; Fig. 6).
Siemieniec ‘447 fails to disclose wherein the high-k dielectric layer is arranged between the gate electrode structure and the shielding region.
However, Challa discloses wherein the high-k dielectric layer is arranged between the gate electrode structure and the shielding region (gate dielectric layer 226 may utilize high-k material and may be disposed between gate electrode 210 and each of body region 204, n+ source 212, and p+ shield region 218; Fig. 2A; paragraphs [0118]-[0120], [0204]).
Siemieniec ‘447 and Challa are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Challa in order to potentially provide higher gate capacitance and better channel control for a given dielectric thickness, reduced gate leakage and improved long-term stability under high-voltage blocking, better field distribution across interfaces with nearby semiconductor structures and regions.
Regarding claim 23, Siemieniec ‘447 in view Challa discloses the transistor device of claim 1. Siemieniec ‘447 further discloses wherein the first mesa region further includes a source region of a second conductivity type adjoining the first sidewall (first mesa 181 comprises n+ source region 110 adjoining first sidewall of gate structure 150; paragraph [0103]), and wherein the gate dielectric structure is arranged between the gate electrode structure and the source region (gate dielectric 159 disposed between gate electrode 155 and body region 120; Fig. 6).
Siemieniec ‘447 fails to disclose wherein the high-k dielectric layer is arranged between the gate electrode structure and the source region.
However, Challa discloses wherein the high-k dielectric layer is arranged between the gate electrode structure and the source region (gate dielectric layer 226 may utilize high-k material and may be disposed between gate electrode 210 and each of body region 204, n+ source 212, and p+ shield region 218; Fig. 2A; paragraphs [0118]-[0120], [0204]).
Siemieniec ‘447 and Challa are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Challa in order to potentially provide higher gate capacitance and better channel control for a given dielectric thickness, reduced gate leakage and improved long-term stability under high-voltage blocking, better field distribution across interfaces with nearby semiconductor structures and regions.
Claims 1-2, 4, 10-11, 14-16, and 18-23 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec ‘447 in further view of US 2014/0027812 A1 to Schulze et al. (hereinafter “Schulze” – previously cited reference).
Regarding claim 1, Siemieniec ‘447 discloses a wide band gap semiconductor device, comprising:
a semiconductor body having a first surface and a second surface opposite to the first surface along a vertical direction (SiC semiconductor body 100 having first and second opposing horizontal surfaces 101, 102; Fig. 6; paragraph [0047]);
a plurality of trench gate structures extending into the semiconductor body from the first surface, the plurality of trench gate structures including a gate electrode structure and a gate dielectric structure arranged between the gate electrode structure and the semiconductor body (gate structure 150 formed into trench extending from surface 101 and having gate electrode 155 separated from body 100 by gate dielectric 159; Fig. 6; paragraph [0046]);
a plurality of mesa regions, wherein a first sidewall of a trench gate structure of the plurality of trench gate structures adjoins a first mesa region of the plurality of mesa regions, and a second sidewall of the trench gate structure adjoins a second mesa region of the plurality of mesa regions (first mesa 181 adjacent left sidewall 151 of gate structure 150 and second mesa 182 adjacent right sidewall 152 of gate structure 150; Fig. 6; paragraphs [0067]-[0068]), wherein the first mesa region includes a body region of a first conductivity type adjoining the first sidewall, wherein the second mesa region includes a shielding region of the first conductivity type (mesa 181 comprises p-type body region 120 adjacent left sidewall and mesa 182 having shielding area 161; Fig. 6; paragraph [0053]), wherein a bottom side of the shielding region has a larger first vertical distance to the first surface than a bottom side of the body region in the first mesa region (shielding area 161 disposed further away from surface 101 than body region 120; Fig. 6), wherein the gate dielectric structure is arranged between the gate electrode structure and the body region (gate dielectric 159 disposed between gate electrode 155 and body region 120; Fig. 6).
Siemieniec ‘447 fails to disclose the gate dielectric structure including a high-k dielectric layer; wherein the dielectric structure further includes a first dielectric layer arranged between the high-k dielectric layer and the body region, the first dielectric layer having a dielectric constant that is smaller than the dielectric constant of the high-k dielectric layer and is equal to or larger than the dielectric constant of SiO2.
However, Schulze discloses the gate dielectric structure including a high-k dielectric layer (gate dielectric structure 322 having Al2O3 high-k dielectric 336 layer; Fig. 3; paragraphs [0030], [0048]); wherein the dielectric structure further includes a first dielectric layer arranged between the high-k dielectric layer and the body region (gate dielectric structure 322 includes first dielectric 130 between the high-k dielectric 336 and the body region 116; Fig. 3; paragraph [0044]), the first dielectric layer having a dielectric constant that is smaller than the dielectric constant of the high-k dielectric layer and is equal to or larger than the dielectric constant of SiO2 (dielectric 130 may be made of SiO2 and high-k dielectric 336 may be made of a material with a dielectric constant higher than that of SiO2; paragraphs [0027], [0029], [0048]).
Siemieniec ‘447 and Schulze are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Schulze in order to potentially provide thicker physical layers while maintaining high capacitance, reduced quantum tunneling leakage, improved drive current, improved interface quality, complementary dielectric properties to high-k dielectric materials, and thermal oxidation compatibility.
Regarding claim 2, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 fails to disclose wherein the high-k dielectric layer includes at least one of Al203, ZrO2, HfO2, AIN, alumisilicate AISiOx, silicon doped HfO2, TiO2, Y203 or Si3N4.
However, Schulze discloses wherein the high-k dielectric layer includes at least one of Al203, ZrO2, HfO2, AIN, alumisilicate AISiOx, silicon doped HfO2, TiO2, Y203 or Si3N4 (gate dielectric structure 322 having Al2O3 high-k dielectric 336 layer; Fig. 3; paragraphs [0030], [0048]).
Siemieniec ‘447 and Schulze are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Schulze in order to potentially provide a material with a high dielectric constant, a high breakdown field, high thermal and chemical stability, and low interface trap density.
Regarding claim 4, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein a thickness of an additional dielectric layer is, by a factor ranging from 2 to 200, larger than a first thickness of the first dielectric layer (additional dielectric layer may have different thickness relative gate dielectric 159; paragraph [0052]).
Siemieniec ‘447 fails to disclose wherein the first dielectric layer is a first SiO2 layer and the additional dielectric layer is a high-k dielectric layer.
However, Schulze discloses wherein the first dielectric layer is a first SiO2 layer (dielectric 130 may be made of SiO2; paragraph [0029]), and a thickness of a high-k dielectric layer (high-k dielectric 136 may have a thickness of between 50 nm and 1 micron; paragraph [0030]).
Siemieniec ‘447 and Schulze are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Schulze in order to potentially provide improved interface quality, complementary dielectric properties to high-k dielectric materials, and thermal oxidation compatibility.
Regarding claim 10, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein the shielding region adjoins at least part of the second sidewall and part of a bottom side of the trench gate structure (shielding area 161 comprises contact area 168 and may adjoin right side 152 and lower edge of gate structure 150; paragraphs [0066], [0110]), and wherein the first vertical distance ranges from 101% to 150% of a second vertical distance from a bottom side of the trench gate structure to the first surface (distance from bottom of shielding area 161 to surface 101 is over 100% than that of bottom of gate structure 150; Fig. 6).
Regarding claim 11, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 10. Siemieniec ‘447 further discloses wherein at a vertical level of a bottom side of a source region of the second conductivity type, a width of the shielding region ranges from 60% to 90% of a width of the second mesa region (shielding area 161 has a width slightly less than that of portions of mesa 182 at source area 110; Fig. 6).
Regarding claim 14, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein the second mesa region includes the body region adjoining the second sidewall of the trench gate structure (mesa 182 includes body region 120 adjoining right side 152 of gate structure 150; Fig. 6).
Regarding claim 15, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 14. Siemieniec ‘447 further discloses wherein the shielding region is laterally confined by parts of the body region (shielding region 161 terminates laterally at portions of body region 120; Fig. 6).
Regarding claim 16, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 14. Siemieniec ‘447 further discloses wherein the first vertical distance ranges from 101% to 110% of a second vertical distance from a bottom side of the trench gate structure to the first surface (distance from bottom of shielding area 161 to surface 101 is over 100% than that of bottom of gate structure 150; Fig. 6).
Regarding claim 18, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein the trench gate structures extend in parallel along a longitudinal direction, and wherein the shielding region has a plurality of sub-regions spaced from each other along the longitudinal direction (gate structures 130 disposed periodically along a direction with shielding areas 161, 162, 165 disposed periodically along same direction; Fig. 6; paragraph [0077]).
Regarding claim 19, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein the semiconductor body is a 4H-SiC semiconductor body (SiC body 100 may be 4H polytype; paragraph [0074]).
Regarding claim 20, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein a vertical doping profile of the shielding region is configured to set a peak of an electric field strength at 99% of an electric breakdown voltage between load electrodes of the wide band gap semiconductor device at or close to an interface between the trench dielectric structure and the semiconductor body at a bottom side of the trench gate structure (shielding area 161 capable of having a doping profile setting a peak of an electric field strength at 99% of an electric breakdown voltage between load electrodes 310 of the semiconductor device 500 at or close to an interface between the gate dielectric 159 and the SiC body 100 at a bottom side of the gate structure 150; Fig. 6; paragraphs [0077], [0084]).
Regarding claim 21, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein the trench gate electrode structure includes a metal or a metal compound (gate structure 150 may utilize a metallic gate electrode 155; paragraph [0043]).
Regarding claim 22, Siemieniec ‘447 in view Schulze discloses the transistor device of claim 1. Siemieniec ‘447 further discloses wherein the shielding region adjoins at least part of the second sidewall (shielding area 161 may adjoin second sidewall 152 of gate structure 150; paragraph [0066]), and wherein the gate dielectric structure is arranged between the gate electrode structure and the shielding region (gate dielectric 159 disposed between gate electrode 155 and body region 120; Fig. 6).
Siemieniec ‘447 fails to disclose the gate dielectric structure including a high-k dielectric layer.
However, Schulze discloses the gate dielectric structure including a high-k dielectric layer (gate dielectric structure 322 having Al2O3 high-k dielectric 336 layer; Fig. 3; paragraphs [0030], [0048]).
Siemieniec ‘447 and Schulze are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Schulze in order to potentially provide thicker physical layers while maintaining high capacitance, reduced quantum tunneling leakage, and improved drive current.
Regarding claim 23, Siemieniec ‘447 in view Schulze discloses the transistor device of claim 1. Siemieniec ‘447 further discloses wherein the first mesa region further includes a source region of a second conductivity type adjoining the first sidewall (first mesa 181 comprises n+ source region 110 adjoining first sidewall of gate structure 150; paragraph [0103]), and wherein the gate dielectric structure is arranged between the gate electrode structure and the source region (gate dielectric 159 disposed between gate electrode 155 and body region 120; Fig. 6).
Siemieniec ‘447 fails to disclose the gate dielectric structure including a high-k dielectric layer.
However, Schulze discloses the gate dielectric structure including a high-k dielectric layer (gate dielectric structure 322 having Al2O3 high-k dielectric 336 layer; Fig. 3; paragraphs [0030], [0048]).
Siemieniec ‘447 and Schulze are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Schulze in order to potentially provide thicker physical layers while maintaining high capacitance, reduced quantum tunneling leakage, and improved drive current.
Claims 5 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec ‘447 as modified by Schulze in further view of US 2004/0101625 A1 to Das et al. (hereinafter “Das” – previously cited reference).
Regarding claim 5, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 4. Siemieniec ‘447 fails to disclose wherein an interface between the first SiO2 layer and the semiconductor body is passivated by nitrogen.
However, Das discloses wherein an interface between the first SiO2 layer and the semiconductor body is passivated by nitrogen (nitrogen passivation of interface 14 between SiO2 layer 12 and SiC substrate 10; abstract; Fig. 3; paragraph [0033]).
Siemieniec ‘447 and Das are both considered to be analogous to the claimed invention because they are in the same field of semiconductor transistor devices having particular dielectric layer parameters. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Das in order to potentially provide reduced interface trap density, improved channel mobility, and enhanced threshold voltage stability.
Regarding claim 8, Siemieniec ‘447 in view of Schulze and Das discloses the wide band gap semiconductor device of claim 5. Siemieniec ‘447 fails to disclose wherein the dielectric structure further includes a second dielectric layer arranged between the high-k dielectric layer and the gate electrode structure, the second dielectric layer having a dielectric constant that is smaller than the dielectric constant of the high-k dielectric layer and is equal to or larger than the dielectric constant of SiO2.
However, Schulze discloses wherein the dielectric structure further includes a second dielectric layer arranged between the high-k dielectric layer and the gate electrode structure (second dielectric 142 may be disposed between high-k dielectric 336 and gate electrode 124; Fig. 3; paragraph [0049]), the second dielectric layer having a dielectric constant that is smaller than the dielectric constant of the high-k dielectric layer and is equal to or larger than the dielectric constant of SiO2 (second dielectric 142 may be paired with SiO2 first dielectric 130 and may also be an oxide dielectric, where high-k dielectric 336 may be made of a material with a dielectric constant higher than that of SiO2; paragraphs [0027], [0029], [0048]).
Siemieniec ‘447 and Schulze are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Schulze in order to potentially provide improved interface quality, complementary dielectric properties to high-k dielectric materials, and thermal oxidation compatibility.
Regarding claim 9, Siemieniec ‘447 in view of Schulze and Das discloses the wide band gap semiconductor device of claim 8. Siemieniec ‘447 further discloses wherein a thickness of an additional dielectric layer is, by a factor ranging from 2 to 200, larger than a first thickness of the first dielectric layer (additional dielectric layer may have different thickness relative gate dielectric 159; paragraph [0052]).
Siemieniec ‘447 fails to disclose wherein the first dielectric layer is a first SiO2 layer and the additional dielectric layer is a high-k dielectric layer.
However, Schulze discloses wherein the first dielectric layer is a first SiO2 layer (dielectric 130 may be made of SiO2; paragraph [0029]), and a thickness of a high-k dielectric layer (high-k dielectric 136 may have a thickness of between 50 nm and 1 micron; paragraph [0030]).
Siemieniec ‘447 and Schulze are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Schulze in order to potentially provide improved interface quality, complementary dielectric properties to high-k dielectric materials, and thermal oxidation compatibility.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec ‘447 as modified by Schulze and Das in further view of US 2017/0345905 A1 to Siemieniec et al. (hereinafter “Siemieniec ‘905” – previously cited reference).
Regarding claim 6, Siemieniec ‘447 in view of Schulze and Das discloses the wide band gap semiconductor device of claim 5.
Siemieniec ‘447 fails to disclose wherein the first thickness ranges from 1 nm to 10 nm.
However, Siemieniec ‘905 discloses a total thickness of body 100 may be hundreds of nanometers which provides a much smaller possible dielectric 151 thickness that could be in the range of 1 to 10 nanometers (see Siemieniec ‘905, Fig. 2B and paragraph [0033]). Therefore, Siemieniec ‘905 suggests wherein the first thickness ranges from 1 nm to 10 nm.
Siemieniec ‘447 and Siemieniec ‘905 are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Siemieniec ‘905 in order to potentially provide minimized interface degradation, enhanced gate capacitance, and reduced leakage current. Further, since the figures of Siemieniec ‘905 illustrate a workable embodiment of the disclosed invention and the claimed range overlaps with or is close to the range suggested by Siemieniec ‘905, a prima facie case of obviousness exists (see In re Wertheim, 541 F.2d 257 (CCPA 1976) and MPEP 2144.05).
Regarding claim 7, Siemieniec ‘447 in view of Schulze and Das discloses the wide band gap semiconductor device of claim 5. Siemieniec ‘447 fails to disclose wherein the first thickness is smaller than 1 nm.
However, Siemieniec ‘905 discloses a total thickness of body 100 may be hundreds of nanometers which provides a much smaller possible dielectric 151 thickness that could be in the range of less than 1 nanometer (see Siemieniec ‘905, Fig. 2B and paragraph [0033]). Therefore, Siemieniec ‘905 suggests wherein the first thickness is smaller than 1 nm.
Siemieniec ‘447 and Siemieniec ‘905 are both considered to be analogous to the claimed invention because they are in the same field of trench gate semiconductor devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 to incorporate the teaching of Siemieniec ‘905 in order to potentially provide minimized interface degradation, enhanced gate capacitance, and reduced leakage current. Further, since the figures of Siemieniec ‘905 illustrate a workable embodiment of the disclosed invention and the claimed range overlaps with or is close to the range suggested by Siemieniec ‘905, a prima facie case of obviousness exists (see In re Wertheim, 541 F.2d 257 (CCPA 1976) and MPEP 2144.05).
Claims 12-13 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec ‘447.
Regarding claim 12, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses wherein the shielding region adjoins at least part of the second sidewall (shielding area 161 comprises contact area 168 and may adjoin right side 152 of gate structure 150; paragraph [0066]), and wherein the first vertical distance is slightly over 100% of a second vertical distance from a bottom side of the trench gate structure to the first surface (distance from bottom of shielding area 161 to surface 101 is over 100% than that of bottom of gate structure 150; Fig. 6).
Siemieniec ‘447 fails to disclose wherein the first vertical distance ranges from 60% to 100% of a second vertical distance from a bottom side of the trench gate structure to the first surface. However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 in this manner which is merely a slight change in structural dimensions already disclosed in order to potentially provide enhanced electric field protection, improved breakdown voltage, and reduced gate oxide degradation. Further, since the figures of Siemieniec ‘447 illustrate a workable embodiment of the disclosed invention and the claimed range overlaps with or is close to the range suggested by Siemieniec ‘447, a prima facie case of obviousness exists (see In re Wertheim, 541 F.2d 257 (CCPA 1976) and MPEP 2144.05).
Regarding claim 13, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 12. Siemieniec ‘447 further discloses wherein at a vertical level of a bottom side of a source region of the second conductivity type, a width of the shielding region ranges from 60% to 90% of a width of the second mesa region (shielding area 161 has a width slightly less than that of portions of mesa 182 at source area 110; Fig. 6).
Regarding claim 17, Siemieniec ‘447 in view of Schulze discloses the wide band gap semiconductor device of claim 1. Siemieniec ‘447 further discloses further comprising: a drift region of a second conductivity type (n-type drift zone 131; Fig. 6; paragraph [0049]); and a current spread region of the second conductivity type, wherein the current spread region is arranged between the drift region and the body region and has a doping concentration, averaged along a vertical extent of the current spread region, that is larger than a doping concentration averaged along a part of the drift region (current distribution areas arranged between drift zone 131 and surface 101 and having a higher doping concentration than drift zone 131; Fig. 6; paragraph [0050]), wherein the part of the drift region adjoins the current spread region and has a vertical extent corresponding to the vertical extent of the current spread region (drift zone 131 contacts current distribution areas which each correspond to vertical extent of drift structure 130; Fig. 6; paragraph [0050]).
Siemieniec ‘447 fails to disclose the current spread region has a doping concentration larger, by a factor ranging from 10 to 1000, than a doping concentration averaged along a part of the drift region.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Siemieniec ‘447 in this manner which is a more specific relative doping parameter that is already generally disclosed in order to potentially provide reduced on-resistance, improved current distribution, and support for high-voltage operation. Further, since the text and figures of Siemieniec ‘447 illustrate a workable embodiment of the disclosed invention and the claimed range overlaps with or is close to the range suggested by Siemieniec ‘447, a prima facie case of obviousness exists (see MPEP 2144.05).
Response to Arguments
Applicant's arguments filed July 30, 2026 have been fully considered. Applicant presented substantive amendments to claim 1 and corresponding arguments. Applicant asserts that Siemieniec ‘447 in view of Schulze does not disclose canceled claim 3 which has been amended into claim 1. Specifically, Applicant asserts that dielectric layer 130 is not arranged between high-k dielectric layer 336 and body region 116. However, Examiner points to cited Fig. 3 where it is clearly visible that a straight line may be drawn that begins within layer 336, passes through layer 130 and ends in region 116, which, using broadest reasonable interpretation, satisfies the limitation at issue of "a first dielectric layer arranged between the high-k dielectric layer and the body region." Further, Examiner notes that this is not a novel feature in the art as evidenced by US 6,693,004 B1 to Halliyal et al., US 2005/0059259 A1 to O’Meara et al., US 2014/0151819 A1 to Cheng et al., and US 2020/0135475 A1 to Cheng et al., which each disclose the limitation amended into claim 1.
Conclusion
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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