DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Acknowledgement is made of the amendment received on 12/10/2025. Claims 1-4 are 6-20 are pending in this application. Claims 1, 3-4, 6-17, and 20 are amended. Claim 5 is canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 2016/0111513; hereinafter ‘Liu’) in view of Kobelev et al. (Journal of Physics: Conference Series 586 (2015), 012013; hereinafter ‘Kobelev’).
Regarding claim 1, Liu teaches a method of manufacturing an integrated circuit device (170. Fig. 3, [0031]), the method comprising:
Forming alternately stacked (172, Fig. 4, [0040]) sacrificial semiconductor layers (185 and 189) and channel layers (187 and 190) on a substrate (183) to obtain a stack structure (a stack structure including 185, 189, 187, and 190; hereinafter ‘SS’);
forming (178, Fig. 7A-7C, [0044]) source regions (213a) and drain regions (213b) on two sides of the stack structure (two sides of SS); and
forming (180, Fig. 9A-9C, [0046]) a gate space (a gate space by removing 185 and 189) between the channel layers (initially 187 and 190, which subsequently form 235 and 237 after removal of 185 and 189) by removing the sacrificial semiconductor layers (185 and 189), wherein the channel layers (235 and 237) are spaced apart from each other in a perpendicular direction to a surface of the substrate (shown in Figs. 9A-9C).
Liu does not teach the method comprising: performing a plasma treatment of boron trichloride (BCl3) on the channel layers, wherein the performing of the plasma treatment of BCl3 on the channel layers includes forming layers of radicals of BCl2, BCl, or B on surfaces of the channel layers.
Kobelev teaches a method (Abstract) comprising: performing a plasma treatment of BCl3 on the semiconductor layers (BCl3 plasma treatment carried out on a GaN semiconductor surface using an ICP RIE system), wherein the performing of the plasma treatment of BCl3 on the channel layers includes forming layers of radicals of BCl2, BCl, or B on surfaces of the semiconductor layers (deposition of BClx radicals on the semiconductor surface and subsequent formation of a Bx-Cly layer covering the semiconductor surface after the BCl3 plasma treatment).
As taught by Kobelev, one of ordinary skill in the art would utilize and modify the above teaching into Liu to obtain and achieve the method comprising: performing a plasma treatment of BCl3 on the semiconductor layers, wherein the performing of the plasma treatment of BCl3 on the channel layers includes forming layers of radicals of BCl2, BCl, or B on surfaces of the semiconductor layers as claimed, because BCl3 the plasma treatment is a surface modification technique without any recess etching of the substrate implemented for modifying semiconductor surfaces during device fabrication (Abstract and 1. Introduction).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kobelev in combination with Liu due to above reason.
Regarding claim 7, Liu in view of Kobelev teaches the method of claim 1, Liu does not teach the method wherein the performing of the plasma treatment of BCl3 on the channel layers is performed in a chamber having a pressure of about 1 mtorr to about 100 mtorr.
Kobelev teaches the method wherein the performing of the plasma treatment of BCl3 on the channel layers is performed in a chamber having a pressure of about 1 mtorr to about 100 mtorr (BCl3 plasma treatment under 10 mTorr, 2. Experimental setup).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Kobelev to obtain and achieve the method wherein the performing of the plasma treatment of BCl3 on the channel layers is performed in a chamber having a pressure of about 1 mtorr to about 100 mtorr as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In reWertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP § 2144.05.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2016/0111513) in view of Kobelev (Journal of Physics: Conference Series 586 (2015), 012013), and further in view of Reed et al. (US 2016/0181516; hereinafter ‘Reed’).
Regarding claim 2, Liu in view of Kobelev teaches the method of claim 1, but does not teach the method wherein the channel layers include a two-dimensional (2D) semiconductor material.
Reed teaches a method [0006] wherein the channel layers include a 2D semiconductor material (a channel is formed from one or more phase change materials TMDs, [0004, 0096]).
As taught by Reed, one of ordinary skill in the art would utilize and modify the above teaching into Liu in view of Kobelev to obtain and achieve the method wherein the channel layers include a 2D semiconductor material as claimed, because TMD is a well-known material and widely used as a channel material in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Reed in combination with Liu in view of Kobelev due to above reason.
Regarding claim 3, Liu in view of Kobelev and Reed teaches the method of claim 2, Liu in view of Kobelev does not teach the method wherein the 2D semiconductor material includes graphene, a transition metal dichalcogenide, h-BN, or a combination of two or more thereof.
Reed teaches the method wherein the 2D semiconductor material includes graphene, a transition metal dichalcogenide, h-BN, or a combination of two or more thereof (2D semiconductor material includes TMDs, [0004, 0096]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Reed to include the method the method wherein the 2D semiconductor material includes graphene, a transition metal dichalcogenide, h-BN, or a combination of two or more thereof as claimed, because TMD is a well-known material and widely used as a channel material in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Regarding claim 4, Liu in view of Kobelev and Reed teaches the method of claim 3, Liu in view of Kobelev does not teach the method wherein the 2D semiconductor material includes the transition metal dichalcogenide, and wherein the transition metal dichalcogenide includes at least one of MoS2, WS2, TaS2, HfS2, ReS2, TiS2, NbS2, SnS2, MOSe2, WSe2, TaSe2, HfSe2, ReSe2, TiSe2, NbSe2, SnSe2, MoTe2, WTe2, TaTe2, HfTe2, ReTe2, TiTe2, NbTe2, or SnTe2.
Reed teaches the method wherein the 2D semiconductor material includes the transition metal dichalcogenide, and wherein the transition metal dichalcogenide includes at least one of MoS2, WS2, TaS2, HfS2, ReS2, TiS2, NbS2, SnS2, MOSe2, WSe2, TaSe2, HfSe2, ReSe2, TiSe2, NbSe2, SnSe2, MoTe2, WTe2, TaTe2, HfTe2, ReTe2, TiTe2, NbTe2, or SnTe2 (TMDs include MoS2, WS2, MOSe2, WSe2, MoTe2, WTe2, [0096]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Reed to include the method the method wherein the 2D semiconductor material includes the transition metal dichalcogenide, and wherein the transition metal dichalcogenide includes at least one of MoS2, WS2, TaS2, HfS2, ReS2, TiS2, NbS2, SnS2, MOSe2, WSe2, TaSe2, HfSe2, ReSe2, TiSe2, NbSe2, SnSe2, MoTe2, WTe2, TaTe2, HfTe2, ReTe2, TiTe2, NbTe2, or SnTe2 as claimed, because MoS2, WS2, MOSe2, WSe2, MoTe2, WTe2 are well-known materials and widely used as channel materials in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2016/0111513) in view of Kobelev (Journal of Physics: Conference Series 586 (2015), 012013), and further in view of Lin et al. (US 2009/0219605; hereinafter ‘Lin’).
Regarding claim 6, Liu in view of Kobelev teaches the method of claim 1, but does not teach the method wherein the performing of the plasma treatment of BCl3 on the channel layers is performed by remote plasma treatment processing of BCl3.
Lin teaches a method [0015] wherein the performing of the plasma treatment of BCl3 on the channel layers is performed by remote plasma treatment processing of BCl3 (BCl3 plasma process uses a remote plasma process, [0024]).
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Liu in view of Kobelev to obtain and achieve the method wherein the performing of the plasma treatment of BCl3 on the channel layers is performed by remote plasma treatment processing of BCl3 as claimed, because it minimizes damage to the target structure during plasma treatment by avoiding direct plasma exposure [0012, 0025-0026].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Liu in view of Kobelev due to above reason.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2016/0111513) in view of Kobelev (Journal of Physics: Conference Series 586 (2015), 012013), and further in view of Williams et al. (US 2012/0328523; hereinafter ‘Williams’).
Regarding claim 8, Liu in view of Kobelev teaches the method of claim 1, but does not teach the method wherein the performing of the plasma treatment of BCl3 on the channel layers is performed on all exposed surfaces of the channel layers.
Williams teaches a method [0051] wherein the performing of the plasma treatment of BCl3 on the channel layers is performed on all exposed surfaces of the channel layers (the plasma treatment affects all exposed surface, [0052]).
As taught by Williams, one of ordinary skill in the art would utilize and modify the above teaching into Liu in view of Kobelev to obtain and achieve the method wherein the performing of the plasma treatment of BCl3 on the channel layers is performed on all exposed surfaces of the channel layers as claimed, because the plasma treatment relies on reactive species generated in the gas phase, which diffuse and contact all exposed surfaces of the treated structure, [0044, 0052].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Williams in combination with Liu in view of Kobelev due to above reason.
Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2016/0111513) in view of Kobelev (Journal of Physics: Conference Series 586 (2015), 012013), and further in view of Bader et al. (US 2020/0144407; hereinafter ‘Bader’).
Regarding claim 9, Liu teaches a method of manufacturing an integrated circuit device (170. Fig. 3, [0031]), the method comprising:
forming alternately stacked (172, Fig. 4, [0040]) sacrificial semiconductor layers (185 and 189) and channel layers (187 and 190) on a substrate (183) to obtain a stack structure (a stack structure including 185, 189, 187, and 190; hereinafter ‘SS’);
forming (178, Fig. 7A-7C, [0044]) source regions (213a) and drain regions (213b) on two sides of the stack structure (two sides of SS);
forming (180, Fig. 9A-9C, [0046]) a gate space (a gate space by removing 185 and 189) between the channel layers (initially 187 and 190, which subsequently form 235 and 237 after removal of 185 and 189) by removing the sacrificial semiconductor layers (185 and 189), wherein the channel layers (235 and 237) are spaced apart from each other in a perpendicular direction to a surface of the substrate (shown in Figs. 9A-9C);
forming (181, Fig. 10A-10C, [0048]) gate dielectric layers (239) on the surfaces of the channel layers (shown in Fig. 10A-10B); and
forming (181, Fig. 10A-10C, [0048]) gate layers (241) covering the gate dielectric layers (239) in the gate space (shown in Fig. 10A-10B).
Liu does not teach the method comprising: performing a plasma treatment of boron trichloride (BCl3) on the channel layers, wherein the performing of the plasma treatment of BCl3 on the channel layers includes forming layers of radicals of BCl2, BCl, or B on surfaces of the channel layers; and forming gate dielectric layers on the BCl3 plasma treated surfaces of the channel layer.
Kobelev teaches a method (Abstract) comprising: performing a plasma treatment of BCl3 on the semiconductor layers (BCl3 plasma treatment carried out on a GaN semiconductor surface using an ICP RIE system), wherein the performing of the plasma treatment of BCl3 on the channel layers includes forming layers of radicals of BCl2, BCl, or B on surfaces of the semiconductor layers (deposition of BClx radicals on the semiconductor surface and subsequent formation of a Bx-Cly layer covering the semiconductor surface after the BCl3 plasma treatment).
As taught by Kobelev, one of ordinary skill in the art would utilize and modify the above teaching into Liu to obtain and achieve the method comprising: performing a plasma treatment of BCl3 on the semiconductor layers, wherein the performing of the plasma treatment of BCl3 on the channel layers includes forming layers of radicals of BCl2, BCl, or B on surfaces of the semiconductor layers as claimed, because BCl3 the plasma treatment is a surface modification technique without any recess etching of the substrate implemented for modifying semiconductor surfaces during device fabrication (Abstract and 1. Introduction).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kobelev in combination with Liu due to above reason.
Liu in view of Kobelev does not teach the method comprising: forming gate dielectric layers on the BCl3 plasma treated surfaces of the channel layer.
Bader teaches a method (FIG. 9, [0104]) comprising: forming gate dielectric layers on the BCl3 plasma treated surfaces of the channel layer (ALD SiO2 dielectric is deposited after the BCl3 plasma treatment, [0096]).
As taught by Bader, one of ordinary skill in the art would utilize and modify the above teaching into Liu in view of Kobelev to obtain and achieve method comprising: forming gate dielectric layers on the plasma treated surfaces of the channel layer as claimed, because surface treatments such as oxidation or chemical preparation prior to gate deposition affect the diode characteristics and reduce off-currents, the dielectric is deposited after the plasma treatment [0106].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Bader in combination with Liu in view of Kobelev due to above reason.
Regarding claim 10, Liu in view of Kobelev and Bader teaches the method of claim 9, Liu in view of Kobelev does not teach the method wherein the forming of the gate dielectric layers on the surface of the channel layers on which the plasma treatment of BCl3 was performed is performed by atomic layer deposition.
Bader teaches the method wherein the forming of the gate dielectric layers on the surface of the channel layers on which the plasma treatment of BCl3 was performed is performed by atomic layer deposition (after the BCl3 plasma treatment, SiO2 dielectric is deposited by ALD, [0096]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Bader to include the method wherein the forming of the gate dielectric layers on the surface of the channel layers on which the plasma treatment of BCl3 was performed is performed by atomic layer deposition as claimed, because ALD process allows the formation of a highly conformal dielectric layer with uniform thickness over recessed regions and sidewall, thereby ensuring proper dielectric coverage and reliable gate insulation [0096].
Regarding claim 11, Liu in view of Kobelev and Bader teaches the method of claim 9, wherein the forming of the gate dielectric layers is performed on all exposed surfaces of the channel layers (Liu: 239 forms on all exposed surfaces of 235 and 237, Fig. 10B).
Regarding claim 12, Liu in view of Kobelev and Bader teaches the method of claim 9, wherein the gate dielectric layers include AI2O3, HfO2, ZrO2, or a combination of two or more thereof (Liu: 239 is HfO2, [0048]).
Regarding claim 13, Liu in view of Kobelev and Bader teaches the method of claim 9, Liu in view of Kobelev does not teach the method wherein the gate dielectric layers directly contact the source region and the drain region.
Bader teaches the method wherein the gate dielectric layers directly contact the source region and the drain region (SiO2 insulating layer 70 is disposed on sidewalls of the first and second slabs 40 corresponding to the source and drain regions, Figs. 4B and 7d, [0071]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Bader to include the method wherein the gate dielectric layers directly contact the source region and the drain region as claimed, because it enables full pinch-off and electrostatic control of the channel and adjacent source and drain edge regions [0102, 0104].
Regarding claim 14, Liu in view of Kobelev and Bader teaches the method of claim 9, wherein the gate layers include a metal, a metal nitride, a metal carbide, or a combination of two or more thereof (Liu: 241 is a metal, [0048]).
Regarding claim 15, Liu in view of Kobelev and Bader teaches the method of claim 14, wherein the gate layers include the metal, and wherein the metal includes at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd.
Bader teaches the method wherein the gate layers include the metal, and wherein the metal includes at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd (gate layer includes Ti, Fig. 7d, [0096]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Bader to include the method wherein the gate layers include the metal, and wherein the metal includes at least one of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd as claimed, because Ti is a well-known material and widely used as a gate layer in the art. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claims 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2016/0111513) in view of Ha et al. (Surf. Coat. Technol., 136 (2001), pp. 157-161) and Bader (US 2020/0144407).
Regarding claim 16, Liu teaches a method of manufacturing an integrated circuit device (170. Fig. 3, [0031]), the method comprising:
forming (172, Fig. 4, [0040]) alternately stacked sacrificial semiconductor layers (185 and 189) and channel layers (187 and 190) on a substrate (183) to form a stack structure (a stack structure including 185, 189, 187, and 190; hereinafter ‘SS’);
forming (178, Fig. 7A-7C, [0044]) source regions (213a) and drain regions (213b) on two sides of the stack structure (two sides of SS);
forming (180, Fig. 9A-9C, [0046-0047]) a gate space (a gate space by removing 185 and 189) between the channel layers by removing the sacrificial semiconductor layers (shown in Fig. 9B), wherein the channel layers (initially 187 and 190, which subsequently form 235 and 237 after removal of 185 and 189) are spaced apart from each other in a perpendicular direction to a surface of the substrate (shown in Figs. 9A-9C);
forming (181, Fig. 10A-10C, [0048]) gate dielectric layers (239) on surfaces of the channel layers (shown in Fig. 10A-10B); and
forming (181, Fig. 10A-10C, [0048]) gate layers (241) covering the gate dielectric layers (329) in the gate space (shown in Fig. 10A-10B).
Liu does not teach the method comprising: performing a plasma treatment on the channel layers; forming gate dielectric layers on the plasma treated surfaces of the channel layer; and wherein the plasma treatment comprises a plasma treatment of BF3, BBr3 or BI3.
Ha teaches a method (Fig. 1, 2.2. Fabrication of pMOSFETs) comprising: performing a plasma treatment on the channel layers (plasma treatment for a surface channel, abstract) and wherein the plasma treatment comprises a plasma treatment of BF3, BBr3 or BI3 (plasma treatment was carried out using BF3, 2.1. PLAD system).
As taught by Ha, one of ordinary skill in the art would utilize and modify the above teaching into Liu to obtain and achieve the method comprising: performing a plasma treatment on the channel layers, wherein the plasma treatment comprises a plasma treatment of BF3, BBr3 or BI3 as claimed, because BF3 the plasma treatment improves device performance by increasing the drive current due to the lower sheet resistance and abrupt boron depth-profile (4. Conclusion).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ha in combination with Liu due to above reason.
Liu in view of Ha does not teach the method comprising: forming gate dielectric layers on the plasma treated surfaces of the channel layer.
Bader teaches a method (FIG. 9, [0104]) comprising: forming gate dielectric layers on the plasma treated surfaces of the channel layer (ALD SiO2 dielectric is deposited after the plasma treatment, [0096]).
As taught by Bader, one of ordinary skill in the art would utilize and modify the above teaching into Liu in view of Ha to obtain and achieve method comprising: forming gate dielectric layers on the plasma treated surfaces of the channel layer as claimed, because surface treatments such as oxidation or chemical preparation prior to gate deposition affect the diode characteristics and reduce off-currents, the dielectric is deposited after the plasma treatment [0106].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Bader in combination with Liu in view of Ha due to above reason.
Regarding claim 17, Liu in view of Ha and Bader teaches the method of claim 16, Liu in view of Bader does not teach the method wherein the performing of the plasma treatment on the channel layers includes forming layers of radicals of BF2, BF, BBr2, BBr, BI2, BI, and B on the surfaces of the channel layers on which the plasma treatment was performed.
Ha teaches the method wherein the performing of the plasma treatment on the channel layers includes forming layers of radicals of BF2, BF, BBr2, BBr, BI2, BI, and B on the surfaces of the channel layers on which the plasma treatment was performed (forming layer of BF2+, 2.2. Fabrication of pMOSFETs).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Ha to include the method wherein the performing of the plasma treatment on the channel layers includes forming layers of radicals of BF2, BF, BBr2, BBr, BI2, BI, and B on surfaces of the channel layers as claimed, because various ions such as BF3+, BF2+, BF+, and B+ are inherently generated from the pure BF3 source gas due to the large electronegativity of fluorine (2.1. PLAD system).
Regarding claim 20, Liu in view of Ha and Bader teaches the method of claim 16, Liu teaches the method wherein the forming of the gate dielectric layers is performed on all exposed surfaces of the channel layers (239 forms on all exposed surfaces of 235 and 237, Fig. 10B).
Liu in view of Ha does not teach the method wherein the forming of the gate dielectric layers is performed on the channel layers by atomic layer deposition.
Bader teaches the method wherein the forming of the gate dielectric layers is performed on channel layers by atomic layer deposition (after the plasma treatment, SiO2 dielectric is deposited by ALD, [0096]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that in Bader to include the method wherein the forming of the gate dielectric layers is performed on the channel layers by atomic layer deposition as claimed, because ALD process allows the formation of a highly conformal dielectric layer with uniform thickness over recessed regions and sidewall, thereby ensuring proper dielectric coverage and reliable gate insulation [0096].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2016/0111513) in view of Ha (Surf. Coat. Technol., 2001) and Bader (US 2020/0144407), and further in view of Lin (US 2009/0219605).
Regarding claim 18, Liu in view of Ha and Bader teaches the method of claim 16, but does not teach the method wherein the performing of the plasma treatment on the channel layers is performed by remote plasma treatment processing.
Lin teaches a method [0015] wherein the performing of the plasma treatment on the channel layers is performed by remote plasma treatment processing (plasma process uses a remote plasma process, [0024]).
As taught by Lin, one of ordinary skill in the art would utilize and modify the above teaching into Liu in view of Ha and Bader to obtain and achieve the method wherein the performing of the plasma treatment on the channel layers is performed by remote plasma treatment processing as claimed, because it minimizes damage to the target structure during plasma treatment by avoiding direct plasma exposure [0012, 0025-0026].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Lin in combination with Liu in view of Ha and Bader due to above reason.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Liu (US 2016/0111513) in view of Ha (Surf. Coat. Technol., 2001) and Bader (US 2020/0144407), and further in view of Kobelev (Journal of Physics: Conference Series 586 (2015), 012013).
Regarding claim 19, Liu in view of Ha and Bader teaches the method of claim 16, but does not teach the method wherein the performing of the plasma treatment on the channel layers is performed in a chamber having a pressure of about 1 mtorr to about 100 mtorr.
Kobelev teaches a method (Abstract) wherein the performing of the plasma treatment on the channel layers is performed in a chamber having a pressure of about 1 mtorr to about 100 mtorr (plasma treatment under 10 mTorr, 2. Experimental setup).
As taught by Kobelev, teaches a method (Abstract) wherein the performing of the plasma treatment on the c, one of ordinary skill in the art would utilize and modify the above teaching into Liu in view of Ha and Bader to obtain and achieve the method wherein the performing of the plasma treatment on the channel layers is performed in a chamber having a pressure of about 1 mtorr to about 100 mtorr as claimed, because it has been held that where the criticality of the claimed range is not shown and the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In reWertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); MPEP § 2144.05.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Kobelev in combination with Liu in view of Ha and Bader due to above reason.
Response to Arguments
Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/24/26