Prosecution Insights
Last updated: October 02, 2026
Application No. 18/138,203

DISPLAY DEVICE

Non-Final OA §103§112
Filed
Apr 24, 2023
Priority
Nov 29, 2022 — RE 10-2022-0162844
Examiner
NADAV, ORI
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
3 (Non-Final)
60%
Grant Probability
Moderate
3-4
OA Rounds
4m
Est. Remaining
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allowance Rate
426 granted / 710 resolved
-8.0% vs TC avg
Strong +21% interview lift
Without
With
+21.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
52 currently pending
Career history
778
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.5%
+15.5% vs TC avg
§102
9.8%
-30.2% vs TC avg
§112
30.9%
-9.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 710 resolved cases

Office Action

§103 §112
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-13 and 16-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitation of “wherein the light emitting element includes a first semiconductor layer that is integral”, as recited in claims 1 and 21 is unclear as to which element the semiconductor layer is integral with. The claimed limitation of “wherein the light emitting element includes a first semiconductor layer that is integral and overlaps each of the at least two sub-pixels in the same pixel”, as recited in claims 1 and 21 is unclear because the semiconductor layer is located below each of the at least two sub-pixels in the same pixel. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-6, 9-13 and 16-21, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (12,446,424) in view of Chen (2007/001181). Regarding claim 1, Park et al. teach in figure 14 and related text a display device comprising: a plurality of pixels (see figure 13) disposed on a substrate; at least two sub-pixels 230R, 230G disposed in a same pixel among of the plurality of pixels; a light emitting diode LED disposed in the same pixel; and a plurality of color conversion members 230R, 230G disposed in the at least two sub-pixels, each of the plurality of color conversion members overlapping with at least a portion of the light emitting element (e.g. element CE), wherein the light emitting element is shared by the at least two sub-pixels in the same pixel. Park et al. do not teach that the light emitting element includes a first semiconductor layer that is integral and overlaps each of the at least two sub-pixels in the same pixel. Regarding claim 21, Park et al. teach in figure 14 and related text a display device comprising: a first sub-pixel 230R configured to emit a first color light; a second sub-pixel 230G configured to emit a second color light different than the first color light; and one light emitting element LED overlapping with at least a portion of the first sub-pixel and at least a portion of the second sub-pixel. Park et al. do not teach that the light emitting element includes a first semiconductor layer that is integral and overlaps each of the at least two sub-pixels in the same pixel. Chen teaches in figure 2 and related text a light emitting element 200 includes a first semiconductor layer 220 that is integral. Chen and Park et al. are analogous art because they are directed to light emitting semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park et al. because they are from the same field of endeavor. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the light emitting element in Park et al.’s device to include a first semiconductor layer that is integral, as taught by Chen, sch that said first semiconductor layer overlaps each of the at least two sub-pixels in the same pixel, in order to simplify the processing steps of making the device by using conventional light emitting structure. Regarding claim 2, the modified device of Park et al. teaches that the inorganic light emitting element includes: a plurality of light emitting layers (of the combined device as part of the LED) disposed on the first semiconductor layer and overlapping with at least a portion of one of the at least two sub-pixels in the same pixel; a plurality of second semiconductor layers (as inherently present in an LED diode) respectively disposed on the plurality of inorganic light emitting layers in the same pixel; a plurality of first electrodes DE/LB disposed in the same pixel, each of the plurality of first electrodes being disposed on a side surface and a lower surface of the first semiconductor layer and overlapping with at least a portion of one of the at least two sub-pixels in the same pixel; and a plurality of second electrodes CE respectively disposed on the plurality of second semiconductor layers in the same pixel and overlapping with at least a portion of one of the at least two sub-pixels in the same pixel. Regarding claim 3, in the modified device of Park et al. the light emitting element further includes a groove (inside element 391) disposed in the plurality of light emitting layers and the plurality of second semiconductor layers (of LED), the groove extending along a boundary between the at least two sub-pixels, and wherein the plurality of light emitting layers are separated from each other by the groove, and the plurality of second semiconductor layers are separated from each other by the groove. Regarding claim 4, in the modified device of Park et al. a first bank 391 disposed in the groove and extending along the boundary between the at least two sub-pixels. Regarding claim 5, in the modified device of Park et al. the plurality of color conversion members include: a plurality of color conversion layers 230R, 230G disposed on the first bank 391 in the plurality of sub-pixels, each of the plurality of color conversion layers including a color conversion material configured to absorb light emitted from one of the plurality of light emitting layers and emit light of a different color than the light emitting from the corresponding one of the plurality of light emitting layers; and a plurality of color filters (not depicted but located on upper substrate 210) disposed on the plurality of color conversion layers. Regarding claim 6, in the modified device of Park et al. at least a portion of each of the plurality of color conversion members overlaps with at least a portion of the light emitting element. Park et al. do not explicitly state that each of the plurality of color conversion members in the same pixel is larger than the light emitting element, and wherein each of the plurality of color conversion members includes a non-overlapping portion that does not overlap the light emitting element. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form each of the plurality of color conversion members in the same pixel larger than the light emitting element, and to include a non-overlapping portion that does not overlap the light emitting element, in Park et al. device, in order to reduce the size of the device by accommodating the structure to smaller chips. See In re Boesch, 617 F.2d 272, 276 (CCPA 1980) (“[Djiscovery of an optimum value of a result effective variable in a known process is ordinarily within the skill of the art.”); In re Aller, 220 F.2d 454, 456 (CCPA 1955) (“where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.”). Regarding claim 9, Park et al. teach in figure 14 and related text a second bank (adjacent to the first bank) disposed along a boundary between at least two pixels among the plurality of pixels. Regarding claim 10, Park et al. teach in figure 14 and related text that the second bank is connected to a portion of the first bank in a plan view. Regarding claim 11, Park et al. teach in figure 14 and related text a second reflective layer CE disposed on a side surface of the first bank and configured to reflect light irradiated towards the side surface of the first bank from the light emitting element. Regarding claim 12, Park et al. teach in figure 14 and related text a third reflective layer CE disposed on a side surface of the second bank and configured to reflect light irradiated towards the side surface of the second bank from the light emitting element. Regarding claim 13, Park et al. teach in figure 14 and related text a driving transistor TR disposed in each of the at least two sub-pixels in an area between the substrate and the light emitting element, wherein the driving transistor sub is electrically connected to the first semiconductor layer through one of the plurality of first electrodes. Regarding claim 16, Park et al. teach in figures 3, 14 and related text a high potential power supply line ELvdd electrically connected to each of the plurality of second electrodes; and a low potential power supply line ELvss electrically connected to the driving transistor, wherein the high potential power supply line, the light emitting element, the driving transistor, and the low potential power supply line are connected in series in each of the at least two sub-pixels. Regarding claim 17, Park et al. teach in figures 3, 14 and related text that the at least two sub-pixels include a first sub-pixel 230R, a second sub-pixel 230G, and a third sub-pixel 230B, wherein the low potential power supply line includes: a first low potential power supply line electrically connected to the driving transistor of the first sub-pixel; a second low potential power supply line electrically connected to the driving transistor of the second sub-pixel; and a third low potential power supply line electrically connected to the driving transistor of the third sub-pixel. Regarding claim 18, Park et al. teach in figures 3, 14 and related text that when only the first sub-pixel among the first, second and third sub-pixels emits light (specific light), a voltage ELvdd having a level higher than that of a voltage applied to the first low potential power supply line ELvss is applied to the second low potential power supply line and the third low potential power supply line. Regarding claim 19, Park et al. teach in figure 14 and related text that the light emitting element LED further includes a groove (inside 391) disposed in a central portion of the light emitting element, and wherein the plurality of inorganic light emitting layers for the at least two sub-pixels are separated from each other by the groove. Regarding claim 20, Park et al. teach in figures 3, 14 and related text that a same high potential power supply voltage ELvdd is supplied to all of the plurality of sub-pixels, and wherein low potential power supply voltages ELvss are supplied to each of the at least two sub-pixels in the same pixel. Park et al. do not teach that the low potential power supply voltages of different levels are supplied to each of the at least two sub-pixels in the same pixel. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to supply low potential power supply voltages of different levels are supplied to each of the at least two sub-pixels in the same pixel, in Park et al. device, in order to provide the sub-pixels with different T-V characteristics such that transmittance at bright pixels starts increasing at relatively low applied voltages, and transmittance at darker pixels starts increasing at higher applied voltages. Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (12,446,424) and Chen (2007/001181), as applied to the claims above, and further in view of Akagawa et al. (10,468,462). Regarding claim 7, the modified device of Park et al. teaches substantially he entire structure, as applied to claim1 above, except forming a first reflective layer disposed between the first bank and at least one of the plurality of color conversion members, wherein the first reflective layer is configured to reflect light emitted from the light emitting element toward the non-overlapping portion of at least one of the plurality of color conversion members. Akagawa et al. teach in figure 7 and related text a first reflective layer 34b or 37 disposed between the first bank (i.e. the light emitting element 30) and at least one of the plurality of color conversion members 36B, wherein the first reflective layer is configured to reflect light emitted from the light emitting element toward the non- overlapping portion (in the modified device) of at least one of the plurality of color conversion members. Chen, Park et al. and Akagawa et al. are analogous art because they are directed to light emitting semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park et al. because they are from the same field of endeavor. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a first reflective layer disposed between the first bank and at least one of the plurality of color conversion members, wherein the first reflective layer is configured to reflect light emitted from the light emitting element toward the non-overlapping portion of at least one of the plurality of color conversion members, as taught by Akagawa et al., in prior art’s device, in order to improve the device characteristics. Regarding claim 8, in the combined device, the first reflective layer has a shape (at least part thereof) corresponding to a planar shape of the light emitting element. Allowable Subject Matter Claim 22 is allowed. Claims 14 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 5/4/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

Apr 24, 2023
Application Filed
Aug 27, 2025
Non-Final Rejection mailed — §103, §112
Nov 28, 2025
Response Filed
Dec 18, 2025
Final Rejection mailed — §103, §112
Feb 27, 2026
Request for Continued Examination
Mar 10, 2026
Response after Non-Final Action
Sep 10, 2026
Non-Final Rejection mailed — §103, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12733260
DISPLAY APPARATUS
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Patent 12726559
DISPLAY DEVICE
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Patent 12727154
SEMICONDUCTOR DEVICE
3y 10m to grant Granted Sep 01, 2026
Patent 12720969
ORGANIC LIGHT EMITTING PANEL AND ORGANIC LIGHT EMITTING DISPLAY DEVICE
4y 9m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+21.2%)
3y 9m (~4m remaining)
Median Time to Grant
High
PTA Risk
Based on 710 resolved cases by this examiner. Grant probability derived from career allowance rate.

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