DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Invention I (claims 1-6) in the reply filed on December 30th, 2025 is acknowledged.
Claim Objections
Claim 2 is objected to because of the following informalities:
Claim 2 recites “the doping process” in line 1 which refers back to “a partial doping process in lines 5-6 of claim 1 and should be amended to “the partial doping process” for avoiding confusion. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by MORIYA (Pub. No.: US 2022/0320268 A1).
Regarding claim 1, MORIYA discloses a method for forming a semiconductor structure in Figs. 1-2 and 7, comprising: providing a substrate (combination of layers 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10) comprising a device region (active area 101) and a guard ring region (outer-edge area 102) surrounding the device region (see Figs. 1-2 and [0031-0034]); and forming a power device (forming a trench-gate MOSFET in active area 101) in the device region and forming a guard ring (guard ring 44 and current spreading layer 42a in outer-edge area 102) in the guard ring region (see Fig. 2 and [0031-0036], [0038]), wherein the guard ring is doped with a first dopant ion (p-type impurity ion forming guard ring 44) that is formed by a partial doping process used in forming the power device (both guard ring 44 and p+ region 4 of the trench-gate MOSFET are formed by the implantation process of p+ type impurity ion in Fig. 7 using oxide mask 140), and a conductivity type of the first dopant ion (p-type conductivity of guard ring 44) in the guard ring is different from a device type of the power device (n-type channel device of the trench-gate MOSFET in region 101 being determined by n+ source 9, p-type base, n-type drift 2 and n+ drain region 1) (see Figs. 2, 7 and [0049-0051]).
Regarding claim 2, MORIYA discloses the method according to claim 1, wherein the doping process comprises an ion implantation doping process (see Fig. 7 and [0051]).
Regarding claim 3, MORIYA discloses the method according to claim 1, wherein the guard ring is doped with a second dopant ion (nitrogen are selectively implanted as n+ impurity ion forming n+ type current spreading layers 42a in area 102) having a conductivity type (n+ conductivity type of current spreading layers 42a) different from the conductivity type of the first dopant ion (p+ conductivity type of guard rings 44), and a top surface of the guard ring (top surface of guard rings 44) is lower than a top surface of the substrate (a top surface of layers 8-10 in region 101) (see Fig. 2 and [0051-0052]).
Regarding claim 4, MORIYA discloses the method according to claim 1, wherein a top surface of the guard ring (top surface of guard rings 44) is flush with a top surface of the substrate (flush with top surface of drift layer 2 in region 102) (see Fig. 2).
Regarding claim 6, MORIYA discloses the method according to claim 1, wherein when the power device is an N-type power device (n-type channel device of the trench-gate MOSFET in region 101 being determined by n+ source 9, p-type base, n-type drift 2 and n+ drain region 1), the first dopant ion in the guard ring is P-type ion (p+ impurity ion of guard rings 44) (see Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over MORIYA (Pub. No.: US 2022/0320268 A1), as applied to claim 1 and further in view of MIMURA et al. (Pub. No.: US 2024/0290616 A1), hereinafter as Mimura.
Regarding claim 5, MORIYA discloses the method according to claim 1, but fails to disclose wherein when the power device is a P-type power device, the first dopant ion in the guard ring is N-type ion.
Mimura discloses a method of forming a semiconductor device in Fig. 1 wherein a power device (trench gate MOSFET) can be either N-type power device or P-type power device (see [0075]).
Modifying the method of MORIYA for forming N-type power device having all one conductivity type convert to the opposite conductivity type as same as the method of Mimura for disclosing a P-type power device and the first dopant ion in the guard ring is N-type ion as recited in claim 6.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the N-type power device and P-type ion of the first dopant of MORIYA to P-type power device and N-type ion of the first dopant because it is conventional to form both N-type and/or P-type power device by switching the conductivity of layers for forming complementary of integrated circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818