DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-15 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the phrase “extends outwardly from the same bottom side” coupled with “perpendicular” and “along an identical direction” is unclear. Does “same bottom side” refer to the encapsulation material, the first metal surface, the entire module, or each pin individually? If the pins are attached to the metal surface, how can they be perpendicular to the metal surface? The phrase “an identical direction” is relative to what reference frame, exactly parallel, substantially parallel, same vector orientation? Does each pin face the same direction? How are the first side and the second side “connected” to the bottom side?
The other claims are rejected as being dependent on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 14, 15 is/are, to the extent taught and understood, rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2021/0287978 (Yamada).
Yamada discloses (at least Fig. 1)
1. (Currently Amended) A power module, comprising:
a substrate 20, comprising a first metal surface 22;
a plurality of semiconductor devices 3, disposed on the first metal surface 10A;
a plurality of pins 40, 41 wherein an extending direction of each of the plurality of pins 40, 41 is perpendicular to a bottom side of the first metal surface 22; and
an encapsulation material 12, wherein the encapsulation material 12 is configured to seal the first metal surface 22 and the plurality of semiconductor devices 3 and to seal each (of the plurality of) pin(s) 40, 41 partially, and each of the plurality of pins 40, 41 extends outwardly from the same bottom side of the encapsulation material 12 along an identical direction,
wherein the plurality of pins 40, 41 comprise a positive voltage pin 40 and a negative voltage pin 41, an end of the positive voltage pin 40 is attached to a middle position (along x-direction) of a first side (left) of the first metal surface 22, an end of the negative voltage pin 41 is attached to a middle position (along x-direction) of a second side (right) of the first metal surface 22, wherein the first side (left) and the second side (right) are spatially opposite to each other, and the first side (left) and the second side (right) are connected to the bottom side of the first metal surface 22,
wherein the amount of the semiconductor devices 3 is even (2), and the semiconductor devices 3 are arranged on the first metal surface to form a matrix, wherein a center of the matrix (2 rows, 2 columns), the middle positions of the first side (left) and the second side (right) are spatially located on a horizontal line (x-direction).
Yamada discloses (at least Fig. 2)
14. The power module according to claim 1, wherein the substrate 20 further comprises a thermal-conductive insulation plate 20 / 21 and a second metal surface 10, wherein the first metal surface 22 is attached to a first surface of the thermal-conductive insulation plate 20 / 21, and the second metal surface 10 is attached to a second surface of the thermal-conductive insulation plate 20 / 21, the first surface and the second surface are opposite to each other, and the second metal surface 10 is exposed from the encapsulation material 12.
Yamada discloses
15. The power module according to claim 1, wherein the encapsulation material 12 is made of a molding compound, and a manufacturing material of the molding compound is epoxy resin. ([0042])
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 4, 7-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2017/0207213 (Sugimachi).
Yamada fails to disclose
3. (Currently Amended) The power module according to claim 1, wherein the plurality of pins further comprise a phase voltage pin, and the phase voltage pin is disposed between the positive voltage pin and the negative voltage pin, wherein an end of the phase voltage pin is attached to the first metal surface, and a position where the end of the phase voltage pin is attached to the first metal surface is closer to the bottom side relative to the horizontal line.
Sugimachi teaches (at least Fig. 5)
A power module comprising:
wherein the plurality of pins NM1 / ND1 / O1 / PD1 / PM1 further comprise a phase voltage pin O1, and the phase voltage pin O1 is disposed between the positive voltage pin PD 1 / PM1 and the negative voltage pin NM1 / ND1, wherein an end of the phase voltage pin is attached to the first metal surface, and a position where the end of the phase voltage pin is attached to the first metal surface is closer to the bottom side relative to the horizontal line.
As discussed above the arrangement / position of the pins would have been obvious since Wu teaches multiple pins.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a phase voltage pin in Yamada. The motivation would be they are well-known in the power module art as discussed in Sugimachi. ([0106])
Sugimachi teaches
4. The power module according to claim 3, wherein a first distance between the phase voltage pin and the positive voltage pin is equal to a second distance between the phase voltage pin and the negative voltage pin.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an optimum arrangement of parts. The motivation would be an obvious matter of engineering design considerations. See MPEP 2144.04.
Yamada discloses
7. (Currently Amended) The power module according to claim 3, wherein each of the plurality of semiconductor devices 3 is electrically connected to the first metal surface 22 through at least one power transmission wire 5 respectively, and a power supply current received by the positive voltage pin 40 flows through the semiconductor device 3 disposed above the horizontal line via the first metal surface 22 and the at least one power transmission wire 5 ([0038]).
Yamada discloses
8. (Currently Amended) The power module according to claim 7, wherein the power supply current flowing through the semiconductor device 3 disposed above the horizontal line flows
Yamada discloses
9. (Currently Amended) The power module according to claim 7, wherein the power supply current flowing through the semiconductor device 3 disposed above the horizontal line
Yamada discloses
10. (Currently Amended) The power module according to claim 7, wherein the power supply current received by the negative voltage pin 41 flows through the semiconductor device 3 disposed above the horizontal line via the first metal surface 22 and the at least one power transmission wire 5, and the power supply current flows
Yamada discloses
11. (Currently Amended) The power module according to claim 7, wherein the power supply current receive by the phase voltage pin 42 (Samaguchi) flows through the semiconductor device 3 disposed below the horizontal line via the first metal surface 22 and the at least one power transmission wire 5, and the power supply current flows
Yamada discloses pins 40, 41 are larger than pins 15
12. The power module according to claim 3, wherein the plurality of pins 40, 41 have a cross-sectional area, and the positive voltage pin 40, the negative voltage pin 41 20 and the phase voltage pin (a matter of routine engineering design considerationsm see MPEP 2144.04) have the largest cross-sectional area among the plurality of pins.
Sugimachi teaches (determining the number of pins would have only involved routine optimization, see MPEP 2144.05)
13. The power module according to claim 1, wherein the amount of the plurality of pins is odd, and the amount of the plurality of pins is greater than or equal to three.
Claim(s) 5, 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamada in view of Sugimachi as applied to claim 4 above, and further in view of U.S. Patent Application Publication No. 2023/0343755 (Hayashi).
The combination of references fails to teach
5. The power module according to claim 4, wherein the plurality of pins further comprises a first gate pin and a first source pin, and the first gate pin and the first source pin are disposed within the first distance, wherein an end of the first gate pin and an end of the first source pin are adjacent to the bottom side of the first metal surface, and the end of the first gate pin and the end of the first source pin are electrically connected to the first metal surface through at least one power transmission wire, wherein the encapsulation material seals the end of the first gate pin and the end of the first source pin.
Hayashi teaches
A power module comprising:
wherein the plurality of pins further comprises a first gate pin 11D and a first source pin 11E, and the first gate pin 11D and the first source pin 11E are disposed within the first distance, wherein an end of the first gate pin 11D and an end of the first source pin 11E are adjacent to the bottom side of the first metal surface 1A-1G, and the end of the first gate pin 11D and the end of the first source pin 11E are electrically connected to the first metal surface 1A-1G through at least one power transmission wire 5, 6, wherein the encapsulation material 7 seals the end of the first gate pin 11D and the end of the first source pin 11E.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a first gate pin and first source pin in the modified device of Yamada. The motivation would be they are well-known in the power module art as shown in Hayashi. See MPEP 2144.03.
Hayashi teaches (further pins would have been mere duplication of parts, see MPEP 2144.04)
6. The power module according to claim 4, wherein the plurality of pins further comprises a second gate pin 11F and a second source pin 11G, and the second gate pin 11F and the second source pin 11G are disposed within the second distance, wherein an end of the second gate pin 11F and an end of the second source pin 11G are adjacent to the bottom side of the first metal surface 1A-1G, and the end of the second gate pin 11F and the end of the second source pin 11G are electrically connected to the first metal surface 1A-1G through at least one power transmission wire 5, 6, wherein the encapsulation material 7 seals the end of the second gate pin 11F and the end of the second source pin 11G.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2023/0369163 (Yang), 2023/0369186 (Yang), 2019/0372063 (Xu), disclose a power module having pins.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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