Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/6/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claims 1-5, 8-10, 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 20190244947 A1) in view of Chen (US 20200118975 A1) and Wu (US 20230260945 A1).
Regarding claim 1, Yu discloses a semiconductor package (Fig. 12A) comprising:
a first semiconductor chip (101) including a first semiconductor substrate (105; [0025]: “bulk silicon”) having a first active surface and a first non-active surface, opposite to each other, a first interconnection structure disposed on the first active surface, through-electrodes (113) passing through the first semiconductor substrate and connected to the first interconnection structure, a redistribution structure disposed on the first non-active surface and connected to the through-electrodes, and first contact pads (111) disposed on the redistribution structure;
a second semiconductor chip (200) including a second semiconductor substrate (201; [0036]: “a semiconductor substrate”) having a second active surface (the surface with functional connections to at least 111, See annotated figure) and a second non-active surface (the opposing surface without any functional connections, See annotated figure), opposite to each other (vertically opposite), a second interconnection structure (collection of 203/205, See annotated figure) disposed on the second active surface (203/205 is on the annotated second active surface of chip 200, See annotated figure) and having a first region (annotated as First Region, between the dashed reference lines of the annotated figure) on which the first semiconductor chip is disposed (the first region overlaps with 101, thus “disposed”. Note: Fig. 2 shows the method step when the 1st chip is being disposed onto the 2nd chip.) and a second region (annotated as Second Region, outside the dashed reference lines of the annotated figure), different from the first region (“different” based on the dashed reference lines), and second contact pads (207) disposed on the first region of the second interconnection structure and respectively bonded to the first contact pads;
first conductive posts (portions of 113, See annotated figure) disposed on the first interconnection structure;
a first mold layer disposed on the first interconnection structure and surrounding each first conductive post of the first conductive posts;
second conductive posts (401) disposed on the second region of the second interconnection structure;
a second mold layer (501) disposed on the second region of the second interconnection structure (directly on) and surrounding the first semiconductor chip (horizontally surrounding), the first mold layer, and each second conductive post of the second conductive posts (horizontally surrounding);
a passivation layer (layer 1001 within structure 1000. This cited layer is enclosing and thereby protecting conductive features contained within structure 1000, thus it is “a passivation layer”) disposed on the first mold layer and the second mold layer (Fig. 10 shows the method step of disposing this layer);
first conductive connection structures (respective ones of 1003 within 1000) passing through the passivation layer and respectively connected to the first conductive posts (electrically connected); and
second conductive connection structures (respective ones of 1003 within 1000) passing through the passivation layer and respectively connected to the second conductive posts (electrically connected),
wherein side surfaces of the second mold layer (See annotated figure) are vertically below side surfaces of the second semiconductor chip (See annotated figure), and wherein the side surfaces of the second semiconductor chip are vertically coplanar with the side surfaces of the second mold layer (coplanar along dashed reference line).
Illustrated below is a marked and annotated figure of Fig. 12A of Yu.
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Yu teaches the first semiconductor substrate, through electrodes, first contact pads, and first conductive posts; however, fails to teach “a first semiconductor chip including a first semiconductor substrate having a first active surface and a first non-active surface, opposite to each other,
a first interconnection structure disposed on the first active surface, through-electrodes passing through the first semiconductor substrate and connected to the first interconnection structure,
a redistribution structure disposed on the first non-active surface and connected to the through-electrodes, and first contact pads disposed on the redistribution structure;” and
“first conductive posts disposed on the first interconnection structure;
a first mold layer disposed on the first interconnection structure and surrounding each first conductive post of the first conductive posts;”.
Chen discloses a first semiconductor chip in the same field of endeavor (Fig. 2: 103) including a first semiconductor substrate (103a) having a first active surface (103a-1; [0035]: “an active side”) and a first non-active surface, opposite to each other (103a-2; [0035]: “inactive side”),
a first interconnection structure (combination of 103g/103f) disposed on the first active surface (indirectly on, through intervening 103a), through-electrodes passing through the first semiconductor substrate and connected to the first interconnection structure (103h),
a redistribution structure (combination of 103b/103c) disposed on the first non-active surface (indirectly on, through intervening 103a) and connected to the through-electrodes (103h), and first contact pads (103c-1) disposed on the redistribution structure.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Yu, by including a first interconnection structure and a redistribution structure in the same way. Doing so would arrive at the claimed configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation an electrical path is formed vertically through the die and through-electrodes to opposing surfaces (Yu: Fig. 12A: surfaces A and B of 101; Chen: surfaces A and B of 103, See annotated figure). Chen teaches a design incentive of these structures is to provide electrical connections according to required circuitry configuration within the semiconductor package ([0038]: “configured to route a path of circuitry from the second die substrate 103a and redistribute I/O terminals of the second die substrate”; [0043]: “configured to electrically connect the second die 103 with a circuitry or conductive structure external to the second die”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first interconnection structure and redistribution structure because it would enable designing additional circuitry configurations, thereby enhancing design capabilities. MPEP 2144 (I). MPEP 2143 (I)(F).
Illustrated below is a marked and annotated figure of Fig. 2 of Chen.
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Yu in view of Chen fails to teach “a first mold layer disposed on the first interconnection structure and surrounding each first conductive post of the first conductive posts;” […]
“a second mold layer disposed on the second region of the second interconnection structure and surrounding the first semiconductor chip, the first mold layer, and each second conductive post of the second conductive posts;
a passivation layer disposed on the first mold layer and the second mold layer;”.
Wu discloses:
a first mold layer (Fig. 5: 125) disposed on the first interconnection structure (122) and surrounding (horizontally surrounding) each first conductive post (124) of the first conductive posts; […]
a second mold layer (130) disposed on the second region of the second interconnection structure (See dashed reference lines) and surrounding the first semiconductor chip (horizontally surrounding), the first mold layer (horizontally surrounding), and each second conductive post of the second conductive posts (horizontally surrounding posts 110);
a passivation layer (1412) disposed on the first mold layer (directly on) and the second mold layer (directly on).
Modifying the first semiconductor chip of Yu in view of Chen by including the first mold layer and first conductive post of Wu would arrive at the claimed first mold layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a conductive post is connecting a chip to external circuitry (Yu: post of 113, circuitry 1000; Wu: post 124, circuitry 140). Wu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the claimed mold and post configuration in that it would provide increased strength surrounding the posts ([0019]: “to increase its strength”). Therefore, it would have been obvious to have the claimed mold and post configuration because it would increase strength surrounding the posts. MPEP 2143 (I)(G).
Illustrated below is a marked and annotated figure of Fig. 5 of Wu.
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Regarding claim 2, Yu in view of Chen and Wu discloses the semiconductor package of claim 1 (Wu: Fig. 5), wherein the first mold layer has an upper surface (See annotated figure for direction designation) being coplanar (horizontally coplanar) with upper ends of the first conductive posts (See annotated figure for direction designation).
Regarding claim 3, Yu in view of Chen and Wu discloses the semiconductor package of claim 2 (Wu: Fig. 5), wherein the second mold layer has an upper surface (See annotated figure for direction designation) being coplanar (horizontally coplanar) with upper ends of the second conductive posts (See annotated figure for direction designation) and the upper surface of the first mold layer (See annotated figure for direction designation).
Regarding claim 4, Yu in view of Chen and Wu discloses the semiconductor package of claim 1, further comprising:
conductive bumps connecting the first contact pads to the second contact pads: and
a non-conductive film disposed between the first semiconductor chip and the second semiconductor chip and surrounding each conductive bump of the conductive bumps,
wherein an interface between the first and second mold layers is visually identified ([0035]: “a visible interface”),
wherein the visually-identified interface extends along a vertical direction (See annotated figure for direction designation) perpendicular to an upper surface of the passivation layer (See annotated figure for direction designation) and is coplanar with a side surface of the first interconnection structure (See dashed reference line in annotated figure):
wherein an interface between the non-conductive film and the second mold layer is visually identified, and
wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip.
The combination of Yu, Chen, and Wu as previously relied upon does not include: “conductive bumps connecting the first contact pads to the second contact pads: and
a non-conductive film disposed between the first semiconductor chip and the second semiconductor chip and surrounding each conductive bump of the conductive bumps, […]
wherein an interface between the non-conductive film and the second mold layer is visually identified, and
wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip.”
Nevertheless, these features are disclosed by Wu (Wu: Fig. 5):
conductive bumps (126) connecting the first contact pads (surfaces of 123) to the second contact pads (1511): and
a non-conductive film (109) disposed between (vertically between) the first semiconductor chip and the second semiconductor chip and surrounding (horizontally surrounding) each conductive bump of the conductive bumps, […]
wherein an interface between the non-conductive film and the second mold layer is visually identified (these materials 109 and 130 are separately formed and thus there is a visually identifiable interface between them), and
wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip (See annotated figure for direction designation).
Modifying the first contact pads of Yu by including the conductive bumps and non-conductive film of Wu in the same way would arrive at the claimed bump and film configuration. A person of ordinary skill in the art would have had a reasonable expectation of success including the bump and film configuration of Wu because in each situation the first semiconductor chip is vertically oriented in the same way and has the same vertical electrical connections (Wu: Fig. 5: chip 120, vertically connected to 1411 and 1511. Yu: Fig. 12A: chip 101, vertically connected to 1013 and 207.). Wu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed bump and film configuration in that it would protect the bumps during manufacture ([0032]: “reducing stress and protection”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed bump and film configuration because it would protect the connections during manufacturing. MPEP 2143 (I)(G). MPEP 2143 (I)(F).
Regarding claim 5, Yu in view of Chen and Wu discloses the semiconductor package of claim 1 (Wu: Fig. 5), wherein the first mold layer and the second mold layer comprise different materials (Wu: 1st mold 125 is [0019]: “may include any suitable insulating material…”; 2nd mold 130 is [0033]: “molding compound…encapsulating material…”. Similarly, Yu: Fig. 12A: 2nd mold 501 is [0050]: “a low temperature polyimide material, although any other suitable dielectric, such as PBO”. Note: each of these molds are separately disclosed with a finite selection of known suitable materials. Selecting different materials for each of these molds is expressly encompassed within teachings of Wu: [0035]: “different materials”, as well as the combination of Yu/Chen/Wu.).
Regarding claim 8, Yu in view of Chen and Wu discloses the semiconductor package of claim 1 (Yu: Fig. 12A), wherein each of the first semiconductor chip ([0024]: “a logic device”) and the second semiconductor chip ([0035]: “an application processor”) comprises a logic chip.
Regarding claim 9, Yu in view of Chen and Wu discloses the semiconductor package of claim 1, however fails to teach “a third semiconductor chip disposed on the first region of the second interconnection structure, wherein the first and third semiconductor chips are disposed side by side in a horizontal direction on the first region of the second interconnection structure”.
Chen teaches a first semiconductor chip (Fig. 2: 103) and teaches chip configurations may be modified by including a third semiconductor chip (Fig. 3: an additional 103) disposed on the first region of the second interconnection structure (of the combination of 101b/101c), wherein the first and third semiconductor chips are disposed side by side in a horizontal direction on the first region of the second interconnection structure (two 103 are illustrated horizontally aside each other). Modifying the semiconductor package of Yu in view of Chen and Wu by including a third semiconductor chip, by duplicating the first semiconductor chip of Yu, would arrive at the claimed chip configuration without any change in the respective chip function ([0056]: “configuration similar to the one described above or illustrated in FIG. 1 or 2” explains functions is similar as before). A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Chen teaches chip count within a given device is a design choice, varied according to device requirement ([0056]: “includes several second dies”). It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the semiconductor package because it is a duplication of parts without any change in function. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed third semiconductor chip configuration because it is a mere duplication of parts. MPEP 2144.04 (VI)(A).
Regarding claim 10, Yu in view of Chen and Wu discloses the semiconductor package of claim 9 (Chen: Fig. 3), wherein the first and third semiconductor chips have the same thickness (thicknesses appear matched, as measured in the direction of 101 to 105).
Regarding claim 14, Yu in view of Chen and Wu discloses the semiconductor package of claim 1 (Wu: Fig. 5), wherein the passivation layer contacts (directly contacts) each of the first and second mold layers.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Chen, and Wu as applied to claims 9 and 1 above, and further in view of Liu (US 20190393150 A1).
Regarding claim 11, Yu in view of Chen and Wu discloses the semiconductor package of claim 9, further comprising:
a third mold layer (Wu: Fig. 5: 125, similarly applied to the third chip) disposed in a space between (vertically between) the passivation layer and the third semiconductor chip,
wherein the first and third mold layers have different thicknesses,
wherein each of upper surfaces of the first and third mold layers (See annotated figure for direction designation) is coplanar (horizontally coplanar) with an upper surface of the second mold layer, and
wherein the passivation layer contacts (directly contacts) the upper surface of each of the first, second, and third mold layers.
Yu in view of Chen and Wu teaches the first and third mold layers, however, fails to teach “wherein the first and third mold layers have different thicknesses”.
Liu discloses a first semiconductor chip (Fig 2D: 208A-1), a first mold layer (208A-6), and a third semiconductor chip (208B-1) in the same field of endeavor, further comprising: a third mold layer (a portion of 212’, See annotated figure) disposed in a space between the passivation layer and the third semiconductor chip, wherein the first and third mold layers have different thicknesses (Height A and Height B as measured from the passivation layer, See annotated figure). Additionally, Liu teaches functional configuration of the first and third chips may differ from one another (“may be the same types of die or different type of dies” [0023]). Thus, Liu teaches it is reasonable to expect chips of different configuration may include differences in dimension and consequently include differences in the resultant mold layer thickness. Yu and Chen each also teach functional configurations of the first die may be varied (Yu: [0024]: “any suitable functionality may be utilized”; Chen: [0034]: “suitable for a particular application”). Thus, it is reasonable to expect at least some differences among chips within a semiconductor package. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have the first and third mold layers have different thicknesses because Liu teaches differences among chips that are performing varied functions may reasonably include changes in size/proportion of the chips and the resultant mold layer thickness. Therefore, the claimed mold layer thickness configuration would have been obvious to one of ordinary skill in the art before the effective filing date because it is a change in size/proportion without any difference in performance beyond the functional configurations encompassed within the prior art. MPEP 2144.04 (IV)(A).
Illustrated below is a marked and annotated figure of Fig. 2D of Liu.
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Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, Chen, and Wu as applied to claim 1 above, and further in view of Lin (US 20200161242 A1).
Regarding claim 12, Yu in view of Chen and Wu discloses the semiconductor package of claim 1, however, fails to teach “wherein the first semiconductor chip comprises a plurality of stacked semiconductor chips”.
Lin discloses a first semiconductor chip in the same field of endeavor (Fig. 18E: 159-2), wherein the first semiconductor chip comprises a plurality of stacked semiconductor chips (251-3). Modifying the first semiconductor chip of Yu in view of Chen and Wu to include a plurality of stacked semiconductor chips in the way disclosed by Lin would arrive at the claimed chip configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because Yu teaches a design incentive of varying first chip configuration being alternative device utility ([0024]: “designed to work in conjunction with other devices within the package. However, any suitable functionality may be utilized”). Lin provides a teaching to motivate one of ordinary skill in the art before the effective filing date to modify the first semiconductor chip in that it would enable increased integration density by pluralizing the number of chips ([0048] “density”; density is increased by the pluralization of the chips described in [0048]: “2, 4, 8, 16, 24, 32 HBM DRAM IC chips”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed chip configuration because it would enable increased integration density. MPEP 2143 (I)(G).
Illustrated below is Fig. 18E of Lin.
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Regarding claim 13, Yu in view of Chen, Wu, and Lin discloses the semiconductor package of claim 12 (Lin: Fig. 18E), wherein the plurality of stacked semiconductor chips comprise a memory chip (Lin: [0299]: “HBM IC chips”; similarly Fujishima: [0020]: “a memory die”), and the second semiconductor chip comprises a logic chip (Fujishima: [0020]: “a logic die”).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Yu, Chen, and Wu as applied to claim 1 above, and further in view of Fujishima (US 20200343184 A1).
Regarding claim 15, Yu in view of Chen and Wu discloses the semiconductor package of claim 1 (Yu: Fig. 12A), wherein the first contact pads and the second contact pads are arranged in a first pitch (a generic pitch is illustrated), and the second conductive posts are arranged in a second pitch ([0047]: “a pitch of about 70 μm. However, any suitable dimensions may be utilized”), greater than the first pitch.
Yu fails to teach explicit range endpoints for the first pitch, or dimensional relations between the second and first pitches. Thus, Yu in view of Chen and Wu fails to teach “wherein the first contact pads and the second contact pads are arranged in a first pitch, and the second conductive posts are arranged in a second pitch, greater than the first pitch.” Nevertheless, these dimensions and relations are known elsewhere in the art.
Fujishima discloses a semiconductor package in the same field of endeavor (Fig. 1H), wherein the first contact pads and the second contact pads are arranged in a first pitch (P1; [0022]: “a first pitch”), and the second conductive posts are arranged in a second pitch (P2), greater than the first pitch ([0022]: “P1… is finer than a second pitch P2”). Modifying the first pitch and its relation to the second pitch by incorporating the pitch configuration of Fujishima would arrive at the claimed pitch configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation the pitches pertain to pads (Yu: Fig. 12A: pads 111; Fujishima: Fig. 1H: pads 138) and posts (Yu: Fig. 12A: posts 401; Fujishima: Fig. 1H: posts 128). Doing so would have been prima facie obvious to one of ordinary skill in the art before the effective filing date because it is a recitation of relative dimensions disclosed elsewhere in the prior art for similar structures. MPEP 2144.04 (IV)(A).
Claims 16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Yu, in view of Chen, Chen (US 20220310499 A1, hereinafter Chen ‘499), and Wu.
Regarding independent claim 16, Yu discloses a semiconductor package (Fig. 12A) comprising:
a first semiconductor chip (101) including a first substrate (105; [0025]: “bulk silicon”) having a first surface (Surface A, See annotated figure) and a second surface (Surface B, See annotated figure), located opposite to each other (vertically opposite), and including a redistribution structure located on the first surface, a first interconnection structure disposed on the second surface, through-electrodes (113) passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads (111) disposed on the redistribution structure, wherein the first surface corresponds to an active surface of the first substrate, and the second surface corresponds to a non-active surface of the first substrate;
first conductive posts (portions of 113, See annotated figure) disposed on the first interconnection structure and electrically connected to the first interconnection structure;
a first mold layer disposed on the first interconnection structure and having an upper surface, coplanar with upper ends of the first conductive posts;
a second semiconductor chip (200) including a second interconnection structure (201; [0036]: “a semiconductor substrate”) having a first region (annotated as First Region, between the dashed reference lines of the annotated figure) on which the first semiconductor chip is disposed (the first region overlaps with 101, thus “disposed”. Note: Fig. 2 shows the method step when the 1st chip is being disposed onto the 2nd chip.) and a second region (annotated as Second Region, outside the dashed reference lines of the annotated figure), different from the first region (“different” based on the dashed reference lines), and second contact pads (207) disposed on the first region of the second interconnection structure and respectively connected to the first contact pads, wherein the first surface of the first semiconductor chip is disposed to face the second interconnection structure (these surfaces vertically face each other);
second conductive posts (401) disposed on the second region of the second interconnection structure and electrically connected to the second interconnection structure (connected to respective 207);
a second mold layer (501) disposed on the second region of the second interconnection structure (directly on), and having an upper surface (See annotated figure for direction designation), coplanar with upper ends of the second conductive posts (See annotated figure for direction designation) and the upper surface of the first mold layer;
a passivation layer (layer 1001 within structure 1000. This cited layer is enclosing and thereby protecting conductive features contained within structure 1000, thus it is “a passivation layer”) disposed on the first mold layer and the second mold layer (Fig. 10 shows the method step of disposing this layer); and
a plurality of conductive connection structures (respective ones of 1003 within 1000) passing through the passivation layer and respectively connected to the first conductive posts (electrically connected) and the second conductive posts (electrically connected);
conductive bumps connecting the first contact pads and the second contact pads: and
a non-conductive film disposed between the first semiconductor chip and the second semiconductor chip and surrounding each conductive bump of the conductive bumps,
wherein an interface between the first and second mold layers is visually identified,
wherein the visually-identified interface extends along a vertical direction perpendicular to an upper surface of the passivation layer and is coplanar with a side surface of the first interconnection structure,
wherein an interface between the non-conductive film and the second mold layer is visually identified, and
wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip.
Yu teaches the first surface, second surface, through-electrodes, first substrate, first contact pads, and first conductive posts, but fails to teach “including a redistribution structure located on the first surface, a first interconnection structure disposed on the second surface, through-electrodes passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads disposed on the redistribution structure, wherein the first surface corresponds to an active surface of the first substrate, and the second surface corresponds to a non-active surface of the first substrate;
first conductive posts disposed on the first interconnection structure and electrically connected to the first interconnection structure; a first mold layer disposed on the first interconnection structure and having an upper surface, coplanar with upper ends of the first conductive posts”.
Chen discloses a first semiconductor substrate in the same field of endeavor (Fig. 2: 103a)
including a redistribution structure (combination of 103g/103f) located on the first surface (surface 103a-2), a first interconnection structure (combination of 103b/103c) disposed on the second surface (surface 103a-1), through-electrodes (103h) passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads (surfaces of 103g where exposed to 105) disposed on the redistribution structure, wherein the first surface corresponds to an active surface of the first substrate, and the second surface corresponds to a non-active surface of the first substrate;
first conductive [connectors] (108) disposed on the first interconnection structure (directly on) and electrically connected to the first interconnection structure (directly connected);
a first mold layer (109) disposed on the first interconnection structure (directly on) and having an upper surface, coplanar with upper ends of the first conductive [connectors] (coplanar at interface with 101c).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Yu, by including a first interconnection structure and a redistribution structure with the first semiconductor substrate. Doing so would arrive at the claimed configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation an electrical path is formed vertically through the die and through-electrodes to opposing surfaces (Yu: Fig. 12A: surfaces A and B of 101; Chen: surfaces A and B of 103, See annotated figure). Chen teaches a design incentive of these structures is to provide electrical connections according to required circuitry configuration within the semiconductor package ([0038]: “configured to route a path of circuitry from the second die substrate 103a and redistribute I/O terminals of the second die substrate”; [0043]: “configured to electrically connect the second die 103 with a circuitry or conductive structure external to the second die”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first interconnection structure and redistribution structure because it would enable designing additional circuitry configurations, thereby enhancing design capabilities. MPEP 2144 (I). MPEP 2143 (I)(F).
Yu in view of Chen teaches the first and second surfaces, however, only teaches their functions reversed from the claim. Thus, the combination of references fails to teach “wherein the first surface corresponds to an active surface of the first substrate, and the second surface corresponds to a non-active surface of the first substrate”.
Chen ‘499 teaches a first semiconductor substrate (Fig. 17: 160s) wherein the first surface (160a) corresponds to an active surface of the first substrate ([0062]: “an active surface”), and the second surface (160f) corresponds to a non-active surface of the first substrate ([0062]: “a backside surface”). Chen ‘499 further teaches arrangement of the active and non-active surfaces may be reversed (Fig. 18 shows surface 160f arrangement is reversed from Fig. 17). Modifying the arrangement of the active and non-active surfaces of Yu in view of Chen, by reversing the orientation would arrive at the claimed surface configuration. A person of ordinary skill in the art before the effective filing date would have recognized doing so as an obvious variation in arrangement with predictable results because Chen ‘499 teaches surface arrangement may be reversed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed surface configuration because it is an arrangement of surfaces known in the prior art. MPEP 2144.04 (VI)(A).
Yu in view of Chen and Chen ‘499 fails to teach “a first mold layer disposed on the first interconnection structure and having an upper surface, coplanar with upper ends of the first conductive posts;” [and]
“a second mold layer disposed on the second region of the second interconnection structure, and having an upper surface, coplanar with upper ends of the second conductive posts and the upper surface of the first mold layer;
a passivation layer disposed on the first mold layer and the second mold layer;” [and]
“conductive bumps connecting the first contact pads and the second contact pads: and
a non-conductive film disposed between the first semiconductor chip and the second semiconductor chip and surrounding each conductive bump of the conductive bumps,
wherein an interface between the first and second mold layers is visually identified,
wherein the visually-identified interface extends along a vertical direction perpendicular to an upper surface of the passivation layer and is coplanar with a side surface of the first interconnection structure,
wherein an interface between the non-conductive film and the second mold layer is visually identified, and
wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip.”
Wu discloses:
a first mold layer (Fig. 5: 125) disposed on the first interconnection structure (122) and having an upper surface (See annotated figure for direction designation), coplanar (horizontally coplanar) with upper ends of the first conductive posts (See annotated figure for direction designation); [and]
a second mold layer (130) disposed on the second region of the second interconnection structure (See dashed reference lines), and having an upper surface (See annotated figure for direction designation), coplanar (horizontally coplanar) with upper ends of the second conductive posts (See annotated figure for direction designation) and the upper surface of the first mold layer (See annotated figure for direction designation);
a passivation layer (1412) disposed on the first mold layer (directly on) and the second mold layer (directly on); [and]
conductive bumps (126) connecting the first contact pads (exposed surfaces of 123) and the second contact pads (1511): and
a non-conductive film (109) disposed between (vertically between) the first semiconductor chip and the second semiconductor chip and surrounding (horizontally surrounding) each conductive bump of the conductive bumps,
wherein an interface between the first and second mold layers is visually identified ([0035]: “a visible interface”),
wherein the visually-identified interface extends along a vertical direction perpendicular to an upper surface of the passivation layer (See annotated figure for direction designation) and is coplanar (vertically coplanar along dashed reference line) with a side surface of the first interconnection structure,
wherein an interface between the non-conductive film and the second mold layer is visually identified (these materials 109 and 130 are separately formed and thus there is a visually identifiable interface between them), and
wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip (See annotated figure for direction designation).
Modifying the first contact pads of Yu by including the first mold layer, conductive bumps, and non-conductive film of Wu in the same way would arrive at the claimed bump and film configuration. A person of ordinary skill in the art would have had a reasonable expectation of success doing so because in each situation: 1) a conductive post is connecting a chip to external circuitry (Yu: post of 113, circuitry 1000; Wu: post 124, circuitry 140); and 2) the first semiconductor chip is vertically oriented in the same way and has the same vertical electrical connections (Wu: Fig. 5: chip 120, vertically connected to 1411 and 1511. Yu: Fig. 12A: chip 101, vertically connected to 1013 and 207.). Wu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to have the claimed mold, bump, and film configuration in that it would: 1) provide increased strength surrounding the posts ([0019]: “to increase its strength”); and 2) protect the bumps during manufacture ([0032]: “reducing stress and protection”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed mold, bump, and film configuration because it would protect the connections during manufacturing. MPEP 2143 (I)(G). MPEP 2143 (I)(F).
Regarding claim 18, Yu in view of Chen, Chen ‘499, and Wu discloses the semiconductor package of claim 16 (Yu: Fig. 12A), wherein the plurality of conductive connection structures comprise first conductive connection structures respectively connected to the first conductive posts (respective ones of 1003 within 1000), and second conductive connection structures respectively connected to the second conductive posts (respective ones of 1003 within 1000).
Regarding claim 19, Yu in view of Chen, Chen ‘499, and Wu discloses the semiconductor package of claim 16 (Yu: Fig. 12A), wherein the first interconnection structure and the second interconnection structure comprise a first interconnection layer (Chen: 103c; [0040]: “conductive member”) and a second interconnection layer (Yu: Fig. 12A: the collection of 207 are being defined here as a layer), respectively, and wherein the first conductive posts and the second conductive posts contact the first interconnection layer and the second interconnection layer, respectively.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chen, Chen ‘499, and Wu.
Regarding independent claim 20, Yu discloses a semiconductor package (Fig. 12A) comprising:
a first semiconductor chip (101) including a first substrate (105; [0025]: “bulk silicon”) having a first surface (Surface A, See annotated figure) and a second surface (Surface B, See annotated figure), located opposite to each other (vertically opposite), and including a redistribution structure disposed directly on the first surface, a first interconnection structure disposed directly on the second surface, through-electrodes (113) passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads (111) disposed on the first interconnection structure, wherein the second surface corresponds to an active surface of the first semiconductor chip, and the first surface corresponds to a non-active surface of the first semiconductor chip;
first conductive posts (portions of 113, See annotated figure) disposed on the redistribution structure and electrically connected to the redistribution structure;
a first mold layer disposed on the redistribution structure and having an upper surface, coplanar with upper ends of the first conductive posts;
a second semiconductor chip (200) including a second interconnection structure (201; [0036]: “a semiconductor substrate”) having a first region (annotated as First Region, between the dashed reference lines of the annotated figure) on which the first semiconductor chip is disposed (the first region overlaps with 101, thus “disposed”. Note: Fig. 2 shows the method step when the 1st chip is being disposed onto the 2nd chip.) and a second region (annotated as Second Region, outside the dashed reference lines of the annotated figure), different from the first region (“different” based on the dashed reference lines), and second contact pads (207) disposed on the first region of the second interconnection structure and respectively connected to the first contact pads, wherein the second surface of the first semiconductor chip is disposed to face the second interconnection structure (these surfaces vertically face each other);
second conductive posts (401) disposed on the second region of the second interconnection structure and electrically connected to the second interconnection structure (connected to respective 207);
a second mold layer (501) disposed on the second region of the second interconnection structure (directly on), and having an upper surface (See annotated figure for direction designation), coplanar with upper ends of the second conductive posts (See annotated figure for direction designation) and the upper surface of the first mold layer;
a passivation layer (layer 1001 within structure 1000. This cited layer is enclosing and thereby protecting conductive features contained within structure 1000, thus it is “a passivation layer”) disposed on the first mold layer and the second mold layer (Fig. 10 shows the method step of disposing this layer); and
a plurality of conductive connection structures (respective ones of 1003 within 1000) passing through the passivation layer and respectively connected to the first conductive posts (electrically connected) and the second conductive posts (electrically connected),
wherein side surfaces of the second mold layer (See annotated figure) are vertically below side surfaces of the second semiconductor chip (See annotated figure), and
wherein the side surfaces of the second semiconductor chip are vertically coplanar with the side surfaces of the second mold layer (coplanar along dashed reference line).
Yu teaches the first surface, second surface, through-electrodes, first substrate, first contact pads, and first conductive posts, but fails to teach “including a redistribution structure disposed directly on the first surface, a first interconnection structure disposed directly on the second surface, through-electrodes passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads disposed on the first interconnection structure, wherein the second surface corresponds to an active surface of the first semiconductor chip, and the first surface corresponds to a non-active surface of the first semiconductor chip;
first conductive posts disposed on the redistribution structure and electrically connected to the redistribution structure;
a first mold layer disposed on the redistribution structure and having an upper surface, coplanar with upper ends of the first conductive posts;”
Chen discloses a first semiconductor substrate in the same field of endeavor (Fig. 2: 103a)
including a redistribution structure (combination of 103g/103f) disposed directly on the first surface (surface 103a-2), a first interconnection structure (combination of 103b/103c) disposed directly on the second surface (surface 103a-1), through-electrodes (103h) passing through the first substrate and connecting the redistribution structure to the first interconnection structure, and first contact pads (surfaces of 103g where exposed to 105) disposed on the first interconnection structure, wherein the second surface corresponds to an active surface of the first semiconductor chip, and the first surface corresponds to a non-active surface of the first semiconductor chip;
first conductive [connectors] (108) disposed on the redistribution structure and electrically connected to the redistribution structure;
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Yu, by including a first interconnection structure and a redistribution structure with the first semiconductor substrate. Doing so would arrive at the claimed configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation an electrical path is formed vertically through the die and through-electrodes to opposing surfaces (Yu: Fig. 12A: surfaces A and B of 101; Chen: surfaces A and B of 103, See annotated figure). Chen teaches a design incentive of these structures is to provide electrical connections according to required circuitry configuration within the semiconductor package ([0038]: “configured to route a path of circuitry from the second die substrate 103a and redistribute I/O terminals of the second die substrate”; [0043]: “configured to electrically connect the second die 103 with a circuitry or conductive structure external to the second die”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed first interconnection structure and redistribution structure because it would enable designing additional circuitry configurations, thereby enhancing design capabilities. MPEP 2144 (I). MPEP 2143 (I)(F).
Yu in view of Chen teaches the first and second surfaces, however, only teaches their functions reversed from the claim. Thus, the combination of references fails to teach “wherein the second surface corresponds to an active surface of the first semiconductor chip, and the first surface corresponds to a non-active surface of the first semiconductor chip”.
Chen ‘499 teaches a first semiconductor substrate (Fig. 17: 160s) wherein the second surface (160a) corresponds to an active surface of the first semiconductor chip ([0062]: “an active surface”), and the first surface (160f) corresponds to a non-active surface of the first semiconductor chip ([0062]: “a backside surface”). Chen ‘499 further teaches arrangement of the active and non-active surfaces may be reversed (Fig. 18 shows surface 160f arrangement is reversed from Fig. 17). Modifying the arrangement of the active and non-active surfaces of Yu in view of Chen, by reversing the orientation would arrive at the claimed surface configuration. A person of ordinary skill in the art before the effective filing date would have recognized doing so as an obvious variation in arrangement because Chen ‘499 teaches surface arrangement may be reversed. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed surface configuration because it is an arrangement of surfaces known in the prior art. MPEP 2144.04 (VI)(A).
Yu in view of Chen and Chen ‘499 fails to teach “a first mold layer disposed on the redistribution structure and having an upper surface, coplanar with upper ends of the first conductive posts;” [and]
“a second mold layer disposed on the second region of the second interconnection structure, and having an upper surface, coplanar with upper ends of the second conductive posts and the upper surface of the first mold layer;
a passivation layer disposed on the first mold layer and the second mold layer;”.
Wu discloses:
a first mold layer (Fig. 5: 125) disposed on the redistribution structure (122) and having an upper surface (See annotated figure for direction designation), coplanar (horizontally coplanar) with upper ends of the first conductive posts (See annotated figure for direction designation); [and]
a second mold layer (130) disposed on the second region of the second interconnection structure (See dashed reference lines), and having an upper surface (See annotated figure for direction designation), coplanar (horizontally coplanar) with upper ends of the second conductive posts (See annotated figure for direction designation) and the upper surface of the first mold layer (See annotated figure for direction designation);
a passivation layer (1412) disposed on the first mold layer (directly on) and the second mold layer (directly on).
Modifying the first semiconductor chip of Yu in view of Chen and Chen ‘499 by including the first mold layer and first conductive post of Wu would arrive at the claimed first mold layer configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation a conductive post is connecting a chip to external circuitry (Yu: post of 113, circuitry 1000; Wu: post 124, circuitry 140). Wu provides a teaching to motivate one of ordinary skill in the art before the effective filing date to include the claimed mold and post configuration in that it would provide increased strength surrounding the posts ([0019]: “to increase its strength”). Therefore, it would have been obvious to have the claimed mold and post configuration because it would increase strength surrounding the posts. MPEP 2143 (I)(G).
Response to Arguments
Applicant's arguments filed 3/6/2026 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Fujishima does not disclose “wherein side surfaces of the second mold layer are vertically below side surfaces of the second semiconductor chip, and wherein the side surfaces of the second semiconductor chip are vertically coplanar with the side surfaces of the second mold layer,” as recited in claim 1. For example, as shown in FIG. 1, side surfaces of the second mold layer 360 are vertically below side surfaces of the second semiconductor chip 200, and the side surfaces of the second semiconductor chip 200 are vertically coplanar with the side surfaces of the second mold layer 360”. Remarks at pg. 5.
Examiner’s reply:
Applicant’s arguments, see pg. 5, filed 3/6/2026, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yu and Wu, as necessitated by claim amendment.
Applicant argues:
Applicant argues with respect to the combination of Fujishima and Chen that “This direct vertical connection is not incidental; it is central to Fujishima’s design. By eliminating additional interconnection layers, Fujishima minimizes parasitic resistance, capacitance, and signal delay between the bottom die 120 and the front-side RDL 160.
Introducing Chen’s additional interconnection and redistribution structures would therefore defeat the very purpose of Fujishima’s simplified, delay-minimizing TSV architecture. A generalized objective of “enhancing circuitry design capabilities” cannot justify modifying a reference in a manner that undermines its expressly configured one-to-one TSV routing scheme”. Remarks at pg. 9.
Applicant further articulates this argument “modifying Fujishima to incorporate Chen’s additional interconnection layers would undermine the very operational principle that Fujishima seeks to achieve. As recognized in MPEP § 2143.01(V), a proposed modification is improper where it would render the prior art device unsatisfactory for its intended purpose. Here, the modification would compromise Fujishima’s expressly configured direct TSV routing scheme, which is designed to minimize delay, and thus would not have been undertaken by a person of ordinary skill in the art”. Remarks at pg. 10.
Examiner’s reply:
Although the instant Office action relies upon Yu instead of Fujishima, the examiner is responding to Applicant’s remarks in full because Yu is relied upon in substantially the same way as Fujishima. The new combination of references (Yu and Chen) are combined in a way substantially similar to Fujishima and Chen. Accordingly, the examiner’s reply below applies in the same way to the combination to Yu and Chen.
The examiner does not find Applicant’s remarks persuasive because whether or not delay is introduced, it does not negate the design incentive cited in Chen. MPEP 2143.01 (I). Furthermore, the examiner does not find induced delay rendering the device inoperable because Chen’s device is operable in a similar way as Fujishima’s device, i.e., a functional circuit path. Applicant's arguments make no specific citation of the contended circuit delay amounts in the Fujishima reference (i.e., time values, or resistive, capacitive, inductive, or other losses).
Regarding Applicant’s assertion that “Fujishima’s one-to-one TSV configuration is specifically intended to eliminate unnecessary delay by avoiding additional interconnection layers”: the examiner does not find Fujishima teaching this motivation and does not find Applicant particularly pointing to this motivation beyond a mere conclusory statement. Accordingly, the examiner finds that we don't know Fujishima's motivation for including the TSV, because Fujishima makes no disclosure to this effect. For example: Fujishima might not have made any specific requirement for circuitry delay and may have instead considered the TSV for alternative reasons such as fine pitch electrical connections or small device footprint from vertically stacked electrical connections. Furthermore, and with respect to delay: we don't know how much delay would be added by combining the Chen reference; or if this delay would be outside the acceptable design requirements of Fujishima, because neither Fujishima nor Chen make any disclosure regarding delay related to the TSV.
Accordingly, the examiner maintains the rejection for the same reasons as before: i.e., to enhance circuitry design capabilities. MPEP 2141.02 (VI): “such disclosure does not criticize, discredit, or otherwise discourage the solution claimed”. MPEP 2144 (I): “The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art”. MPEP 2144 (IV): “One of ordinary skill in the art need not see the identical problem addressed in a prior art reference to be motivated to apply its teachings”.
Applicant argues:
Applicant argues with respect to amended claim 4 that “Fujishima does not disclose “wherein an interface between the non-conductive film and the second mold layer is visually identified,” and “wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip (100),” as recited in amended claim 4”. Remarks at pg. 12.
Examiner’s reply:
Applicant’s arguments, see pg. 12, filed 3/6/2026, with respect to the rejection(s) of claim(s) 4 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wu, as necessitated by claim amendment.
Applicant argues:
Applicant argues with respect to amended claim 16 that “the cited references, either alone or in combination, do not disclose “wherein an interface between the non-conductive film and the second mold layer is visually identified, and wherein the non-conductive film extends horizontally beyond side surfaces of the first semiconductor chip,” as recited in claim 16. These limitations are similar to those addressed with respect to claim 4, and at least for the reasons discussed regarding claim 4, claim 16 and its dependent claims are believed to be patentable over the cited references”. Remarks at pg. 18.
Examiner’s reply:
Applicant’s arguments, see pg. 18, filed 3/6/2026, with respect to the rejection(s) of claim(s) 16 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wu, as necessitated by claim amendment.
Applicant argues:
Applicant argues with respect to amended claim 20 that “the cited references, either alone or in combination, do not disclose “wherein side surfaces of the second mold layer are vertically below side surfaces of the second semiconductor chip, and wherein the side surfaces of the second semiconductor chip are vertically coplanar with the side surfaces of the second mold layer,” as recited in claim 20. These limitations are similar to those addressed with respect to claim 1, and at least for the reasons discussed regarding claim 1, claim 20 is believed to be patentable over the cited references”. Remarks at pg. 21.
Examiner’s reply:
Applicant’s arguments, see pg. 21, filed 3/6/2026, with respect to the rejection(s) of claim(s) 20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Wu, as necessitated by claim amendment.
Conclusion
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817