Prosecution Insights
Last updated: August 16, 2026
Application No. 18/138,665

SEMICONDUCTOR DEVICE

Final Rejection §102§103
Filed
Apr 24, 2023
Priority
Apr 26, 2022 — TW 111115765
Examiner
IQBAL, HAMNA FATHIMA
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Epistar Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
14 granted / 17 resolved
+14.4% vs TC avg
Strong +21% interview lift
Without
With
+21.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
45 currently pending
Career history
58
Total Applications
across all art units

Statute-Specific Performance

§103
62.8%
+22.8% vs TC avg
§102
23.3%
-16.7% vs TC avg
§112
14.0%
-26.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 17 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment An amendment filed on 12/26/2025 in response to the Office Action mailed on 10/01/2025 is being acknowledged and entered into the record. The present Final rejection is made by taking into fully consideration all the amendments. Response to Arguments Applicant’s arguments, see page 5 of the remarks, filed on 02/25/2026, with respect to the 112(b) rejection of Claim 17-19 have been fully considered and are persuasive. The 112(b) of Claims 17-19 has been withdrawn. Applicant’s arguments with respect to claims 1-9, 11, 13-15 and 17-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1, 2, 8, 11, 13 and 18-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Meng et al. (US 20240203956 A1) claiming priority to PCT CN2021/143830.. Regarding Claim 1, Meng et al. discloses a semiconductor device, comprising: a semiconductor epitaxial structure 106, 107, 108 comprising an active structure 108 and a semiconductor contact layer 105 located on the active structure 108 along a vertical direction (Fig. 7: 106, 107, 108, 105, paragraph 0026); a metal contact structure 104 overlapped with the semiconductor contact layer 105 in the vertical direction (Fig. 7: 104, 105, paragraph 0026); and a metal oxide layer 103b overlapped with the metal contact structure 104 in a horizontal direction perpendicular to the vertical direction and being devoid of directly contacting the semiconductor contact layer 105 (Fig. 7: 103b, 104, 105, paragraph 0033, 0035); an insulating layer 103a, 103c contacting the metal structure 104 (Fig. 7: 103a, 103c, 104, 105, paragraph 0033, 0035); wherein the semiconductor epitaxial structure 106, 107, 108 has a surface S1, S2 and the vertical direction is perpendicular to the surface S1, S2 (Fig. 1: S1, S2, 106, 107, 108). Regarding Claim 2, Meng et al. teaches the semiconductor device of claim 1, wherein the metal contact structure 104 comprises a plurality of metal pillars 104 separated with each other, one of the plurality of metal pillars 104 comprises a first surface A1, a second surface A2 and a side surface A3, in which the first surface A1 directly contacts the semiconductor contact layer 105, the second surface A2 is opposite to the first surface A1, and the side surface A3 connects the first surface A1 and the second surface A3 (see annotated Fig. 7: 104, A1, A2, A3). PNG media_image1.png 751 1114 media_image1.png Greyscale Annotated Fig. 7 of Meng et al. (US 20240203956 A1) Regarding Claim 8, Meng et al. teaches the semiconductor device of claim 1, wherein the insulating layer 103a has a first refractive index n1, the semiconductor contact layer 105 has a second refractive index n0, the metal oxide layer 103b has a third refractive index n2, and the first refractive n1 index is less than the second refractive index n0 and the first refractive index n1 is less than the third refractive index n2 (paragraph 0033, 0035). Regarding Claim 11, Meng et al. discloses the semiconductor device of claim 1, wherein a portion of the insulating layer 103a, 103c covers on the metal contact structure 104 (see Fig. 7: 103a, 103c, 104). Regarding Claim 13, Meng et al. teaches the semiconductor device of claim 1, further comprising a first electrode 109 located on the semiconductor epitaxial structure 108, 107, 106, wherein the first electrode 109 does not overlap with the metal contact structure 104 in the vertical direction Y (see annotated Fig. 7: 109, 104, Y). Regarding Claim 18, Weng et al. discloses the semiconductor device of claim 1, wherein the semiconductor contact layer 105 comprises a plurality of parts 105 separated from each other (see annotated Fig. 7: 105). Regarding Claim 19, Meng et al. discloses the semiconductor device of claim 18, wherein each of the plurality of parts 105 is overlapped with the metal contact structure 104 and directly contacts the metal contact structure 104 in the vertical direction Y (see annotated Fig. 7: 105, 104, Y). Regarding Claim 20, Meng et al. teaches the semiconductor device of claim 19, wherein the metal oxide layer 103b directly contacts the insulating layer 103a, 103c (Fig. 7: 103a, 103b, 103c). Regarding Claim 21, Meng et al. teaches the semiconductor device of claim 1, wherein the insulating layer 103a separates the metal oxide layer 103b and the semiconductor contact layer 105 (Fig. 7: 103a, 105, 103b). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Meng et al. (US 20240203956 A1), as applied to Claim 2 above, in view of Yamamoto et al. (US 20200381589 A1). Regarding Claim 3, Meng et al. fails to teach the semiconductor device of claim 2, wherein the first surface and the side surface form an acute angle in a sectional view of the semiconductor device. However, Yamamoto et al. teaches a semiconductor device comprising a metal contact structure 43 comprising a first surface S1, a second surface and a side surface S3, wherein the first surface S1 and the side surface S3 form an acute angle [Symbol font/0x71] in a sectional view of the semiconductor device (See annotated (see annotated Fig. 5: 43, S1, S2, [Symbol font/0x71], S3, paragraph 0082, 0084, 0085). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Meng et al. and Yamamoto et al. in order to have the first surface and the side surface form an acute angle in a sectional view of the semiconductor device. Doing so would further minimize the overlap in the vertical direction between the metal contact structure and the top electrode, thereby reducing the absorption of radiation by the electrode, as recognized by Wang et al. (paragraph 0041). PNG media_image2.png 1100 1066 media_image2.png Greyscale Annotated Fig. 5 of Yamamoto et al. (US 20200381589 A1) Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Meng et al. (US 20240203956 A1), as applied to Claim 2 above, further in view of Lin et al. (TW M520990 U). Regarding Claim 4, the Meng et al. fails to teach the semiconductor device of claim 2, wherein one of the plurality of metal pillars comprises a protrusion extended from the second surface. However, Lin et al. teaches a metal contact structure 10, comprising a protrusion 13 extended from the second surface 11 (see Fig. 2: 10, 11, 13, page 3, lines 19-20). Therefore, to a person of ordinary skill in the art would have combined the teachings of Meng et al. and Lin et al. in order for the plurality of metal pillars of Yamamoto et al. to comprise a protrusion extended from the second surface. Doing so would increase the contact area and therefore the adhesion between the metal contact structure and the semiconductor contact layer. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Meng et al. (US 20240203956 A1), as applied to Claim 2 above, further in view of Wang et al. (US 20190386174 A1). Regarding Claim 7, Meng et al. fails to disclose the semiconductor device of claim 1, wherein the insulating layer separates the metal oxide layer and the metal contact structure in the horizontal direction. However, Wang et al. discloses a semiconductor device, wherein the insulating layer 9 separates the metal oxide layer 8 and the metal contact structure 12 in the horizontal direction X (see annotated Fig. 3: 8, 9 ,12, X). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Meng et al. and Wang et al. in order to have the insulating layer separate the metal oxide layer and the metal contact structure in the horizontal direction. Doing so would electrically isolate the metal oxide layer from the metal contact structure, ensuring current only passes through the metal contact structure. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Meng et al. (US 20240203956 A1), as applied to Claim 1 above, further in view of Chang et al. (US 20200365769 A1). Regarding Claim 9, Meng et al. teaches the semiconductor device of claim 1, further comprising a reflective layer 102 directly contacts the insulating layer 103a, 103c and the metal contact structure 104 (Fig. 7: 102, 103a, 103c, paragraph 0032), but fails to teach the reflective layer 102 directly contacts the metal oxide layer 103b. However, Chang et al. teaches a semiconductor device, comprising a reflective layer 108b directly contacts the metal oxide layer 106 (Fig. 1H: 108b, 106, paragraph 0042). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Meng et al. and Chang et al. in order to have a reflective layer directly contact the metal oxide layer. Doing so would reflect the light emitted by the active structure toward the light-exiting surface of the epitaxial structure so as to facilitate the exit of light. Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Meng et al. (US 20240203956 A1), as applied to Claim 1 above, in view of Huang et al. (CN 112420891 A). Regarding Claim 14, Meng et al. fails to teach the semiconductor device of claim 1, wherein the metal contact structure comprises a main contact layer and a barrier layer connecting the main contact layer. However, Huang et al. teaches a semiconductor device, comprising a metal contact structure 134, 135, wherein the metal contact structure 134, 135 comprises a main contact layer 134 and a barrier layer 135 connecting the main contact layer 134 (Fig. 1: 134, 135, page 9, lines 15-16 in English Translation of Huang et al.). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Meng et al. and Huang et al. in order to have the metal contact structure comprise a main contact layer and a barrier layer connecting the main contact layer. Doing so would prevent the diffusion of unwanted material into the semiconductor contact layer, as recognized by Huang et al. (page 9, lines 15-16 in English Translation of Huang et al.). Regarding Claim 14, Huang et al. teaches the semiconductor device of claim 14, wherein the barrier layer comprises Ta, Ti, Pt or TiW (page 13, lines 17-18 in English Translation of Huang et al.). Claims 22 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Meng et al. (US 20240203956 A1), as applied to Claim 18 above, further in view of Yamamoto et al. (US 20200381589 A1). Regarding Claim 22, Meng et al. fails to teach the semiconductor device of claim 18, wherein one of the plurality of parts of the semiconductor contact layer comprises an inclined side surface. However, Yamamoto et al. teaches a semiconductor device comprising a semiconductor contact layer 41a comprising a plurality of parts 41a separated from each other, wherein one of the plurality of parts 41a of the semiconductor contact layer 41a comprises an inclined side surface (see annotated fig. 5: 41a, paragraph 0081, 0085). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Meng et al. and Yamamoto et al. in order to have one of the plurality of parts of the semiconductor contact layer comprises an inclined side surface. By doing so, a wider interface with the semiconductor active layer can promote uniform current injection. Regarding Claim 23, Yamamoto et al. teaches the semiconductor device of claim 22, wherein the one of the plurality of parts 41a of the semiconductor contact 41a comprises a first surface facing the semiconductor epitaxial structure 30 and a second surface away from the semiconductor epitaxial structure 30, the first surface comprises a width greater than that of the second surface (see above annotated Fig. 5: 41a, 30). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at 571-272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 05/09/2025 /NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Apr 24, 2023
Application Filed
Oct 01, 2025
Non-Final Rejection mailed — §102, §103
Dec 26, 2025
Response Filed
May 15, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+21.4%)
3y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 17 resolved cases by this examiner. Grant probability derived from career allowance rate.

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