DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 3 (fig. 3D), reflected in claims 1-3, 7-9 in the reply filed on 12/01/2025 is acknowledged. However, claim 1 includes limitataion (grounded P region) that is not present in elected species 3/fig. 3D. This feature along with all other limitations of the independent claim 1 are present in fig. 2 which is species 1. Thus, species 1 is being considered as elected instead of species 3. Claims 1-3 and 8 of species 1 will be examined below.
A phone call was made and voice mail was left for Attorney Schaffer @ 7036830500 on 01/07/2026 regarding this election issue. No response received.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over HOSSAIN; Zia et al. (US 20190115436 A1, hereinafter Hossain‘436) in view of KIMOTO; Shinichi et al. (US 20230080779 A1, hereinafter Kimoto‘779).
Regarding independent claim 1, Hossain‘436 teaches, “A SiC shielded gate trench (SGT) device (fig. 1-21; ¶ [0025] - ¶ [0076]) comprising a plurality of unit cells (fig. 1; ‘active cells’, ¶ [0025]) with each unit cell in an active area (101) comprising:
an epitaxial layer (14, fig. 1; ¶ [0027]) of a first conductivity type (N) on a substrate (12);
at least one stripe gate trench (23/22) surrounded by a source region (33) of said first conductivity type (N) encompassed in a body region (31) of a second conductivity type (P);
said stripe gate trench (23/22) having a first type gate trench (upper part of gate trench 23/22) and a second type gate trench (lower part of gate trench 23/22);
said first type gate trench is above said second type gate trench ((and has a trench width wider than a trench width of said second type gate trench));
said first type gate trench being filled with a gate electrode (28) and a shielded gate electrode (21);
said shielded gate electrode (21) being insulated from said epitaxial layer (14) by a first insulating film (24),
said gate electrode (28) being insulated from said epitaxial layer (14) by a gate oxide (26, ¶ [0033]),
said shielded gate electrode (21) and said gate electrode (28) being insulated from each other by an (Inter-polysilicon Oxide) IPO film (27, ¶ [0031] - ¶ [0033]),
said gate oxide (26) surrounding said gate electrode (28) and having a less thickness than a thickness of said first insulating film (24, ¶ [0033]);
((a P-shield region of said second conductivity type for gate oxide electric-field reduction surrounding said second type gate trench filled up with said first insulating film;
at least one grounded P region of said second conductivity type surrounding sidewalls and a bottom of said first type gate trench, connecting with said body regions and said P-shield region; and))
said body region (31) and said source region (33) being shorted to a source metal (54) through source contacts (53)”.
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But Hossain‘436 is silent upon the provision of wherein
said first type gate trench .. has a trench width wider than a trench width of said second type gate trench;
a P-shield region of said second conductivity type for gate oxide electric-field reduction surrounding said second type gate trench filled up with said first insulating film;
at least one grounded P region of said second conductivity type surrounding sidewalls and a bottom of said first type gate trench, connecting with said body regions and said P-shield region;
However, Kimoto‘779 teaches a similar vertical MOSFET device (fig. 1-5; ¶ [0059] - ¶ [0126]), wherein
said first type gate trench (upper part of trench 21, fig. 4) .. has a trench width wider than a trench width of said second type gate trench (lower part of trench 21);
a P-shield region (32, 34) of said second conductivity type (P) for gate oxide electric-field reduction surrounding said second type gate trench filled up with said first insulating film (18);
at least one grounded (¶ [0118], ¶ [0162]) P region (32, 34) of said second conductivity type (P) surrounding sidewalls and a bottom of said first type gate trench, connecting with said body regions (28) and said P-shield region (32, 34);
Hossain‘436 and Kimoto‘779 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hossain‘436 with the features of Kimoto‘779 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Hossain‘436 and Kimoto‘779 to include P regions surrounding the gate trench according to the teachings of Kimoto‘779 with a motivation of reducing the electric field applied to the gate insulating layer when the MOSFET is turned off (see Kimoto‘779, ¶ [0114]) and reducing switching loss by discharging holes when the MOSFET is turned off (see Kimoto‘779, ¶ [0162]).
Note: Kimoto‘779 can be replaced by any of the below prior arts:
HSIEH; Fu-Yuan (US 20220367636 A1),
XU, LIN (CN 115458591 A),
KINOSHITA; Koyo et al. (US 20230420555 A1),
Zeng; Jun et al. (US 20220052170 A1)
Regarding claim 2, Hossain‘436 modified with Kimoto‘779 further teaches, “The SiC SGT device of claim 1, wherein said gate electrode (28, fig. 1 of Hossain‘436) is disposed above said shielded gate electrode (21)”.
Regarding claim 3, Hossain‘436 modified with Kimoto‘779 further teaches, “The SiC SGT device of claim 1, wherein said epitaxial layer (14, fig. 1 of Hossain‘436) is a single epitaxial layer with an uniform doping concentration”.
Regarding claim 8, Hossain‘436 modified with Kimoto‘779 further teaches, “The SiC SGT device of claim 1, wherein said substrate (12, fig. 1; ¶ [0026], Hossain‘436) has said first conductivity type”.
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty and can also be used to reject the claims.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached on (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817