DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Saha et al., hereinafter Saha, US Publication No. 2024/0303401 in view of Dasasathyan et al., hereinafter Dasasathyan, US Patent No. 11,003,826.
Regarding Claim 1, Saha teaches a method comprising:
synthesizing a circuit design into a netlist by a design tool (Saha paragraphs [0020] and [0026], wherein logic synthesis is performed on an RTL description of a circuit design that produces a netlist);
identifying features from the netlist by the design tool (Saha paragraphs [0031], [0041]-[0042] and [0044], wherein the netlist is processed to extract path and node level features);
applying a congestion prediction model to the features by the design tool prior to placement, wherein application of the congestion prediction model generates a prediction value indicative of a congestion level likely to result from placement and routing of the netlist (Saha paragraph [0046], wherein a machine learning model is used to predict congestion values); and
in response to the prediction value indicating the congestion level is greater than a threshold:
determining an implementation-flow action by the design tool (Saha paragraphs [0026]-[0027] and [0031], wherein if target optimization goals and quality metrics thresholds are not satisfied, changes to the design parameters are implemented), and
performing the implementation-flow action to generate implementation data that is suitable for making an integrated circuit (IC) (Saha paragraph [0031], wherein the changes are implemented until a solution that meets optimization goals and quality metrics is achieved).
Saha does not explicitly teach the implementation-flow action including automatically selecting one or more directives for placement and routing to reduce routing congestion during at least one placement and routing phase of the implementation flow.
Dasasathyan teaches the implementation-flow action including automatically selecting one or more directives for placement and routing to reduce routing congestion during at least one placement and routing phase of the implementation flow (Dasasathyan Col. 6, Lines 32-61 and Col. 8, Lines 1-67, wherein strategies are automatically selected which contain directives for placement and routing, directives including routing directives to choose alternative routing algorithms that may reduce routing congestion).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saha and Dasasathyan to apply the known technique of automatically selecting routing strategies and directives to improve on a routing solution as taught by Dasasathyan to improve on the routing solutions at taught by Saha, yielding the predictable results of an improved routing solution to meet design specifications.
Regarding Claim 2, Saha further teaches wherein:
the determining includes determining parameter settings for a placement process or a routing process of the design tool (Saha paragraphs [0027], [0031] and [0046], wherein design parameters for the design process may be modified, the design process including physical synthesis which includes placement and routing); and
the performing includes executing by the design tool, the placement process and the routing process using the parameters settings (Saha paragraph [0031], wherein the settings are iteratively changed and input to the machine learning model to determine if the predicted values meet design specifications).
Regarding Claim 3, Saha further teaches bypassing determining the parameter settings and executing the placement process and the routing process of the design tool in response to the prediction value indicating the congestion level is less than a threshold (Saha paragraph [0031], wherein if optimization goals and quality metrics are achieved, the circuit solution is acceptable and does not need changes).
Regarding Claim 4, Saha further teaches wherein:
the determining includes determining modifications to make to the circuit design (Saha paragraphs [0026]-[0027] and [0031], wherein if target optimization goals and quality metrics thresholds are not satisfied, changes to the design parameters are implemented); and
the performing includes modifying the circuit design to include the modifications (Saha paragraph [0031], wherein the changes are implemented until a solution that meets optimization goals and quality metrics is achieved).
Regarding Claim 5, Saha further teaches selecting, in response to an input parameter to the design tool specifying one of a first type target integrated circuit (IC) device or a second-type target IC device, the congestion prediction model from a first congestion prediction model and a second congestion prediction model (Saha paragraphs [0038] and [0045], wherein multiple instances of design data corresponding to different types of circuit designs are provided and used to train different models based on user desired needs), wherein the first congestion prediction model is associated with the first type target IC device, and the second congestion prediction model is associated with the second type target IC device (Saha paragraph [0017], wherein there are a plurality of different target IC devices).
Regarding Claim 6, Saha further teaches wherein the first type target IC device is a single semiconductor die targeted to implement the circuit design, and the second type target IC device includes a package of two or more semiconductor dice targeted to implement the circuit design (Saha paragraphs [0017] and [0074], wherein target IC devices include devices with one or more chips).
Regarding Claim 7, Saha further teaches wherein:
the circuit design is targeted for implementation on a target integrated circuit (IC) device (Saha paragraphs [0017]-[0018], wherein the circuit design is targeted to be manufactured as an ASIC, FPGA, SOC, etc…); and
identifying the features includes determining one or more levels of utilization by the netlist of one or more types of circuit elements, respectively, of the target IC device (Saha paragraph [0059], wherein feature extraction includes determining the utilization of circuits).
Regarding Claim 8, Saha further teaches wherein:
the circuit design is targeted for implementation on a target integrated circuit (IC) device (Saha paragraphs [0017]-[0018], wherein the circuit design is targeted to be manufactured as an ASIC, FPGA, SOC, etc…); and
the features include an indicator that a count of high-fanout nets is greater than a first threshold, and a net having a count of fanouts greater than a second threshold is a high-fanout net (Saha paragraphs [0041] and [0058]-[0059], wherein features include counts of fan-out).
Regarding Claim 9, Saha further teaches wherein identifying the features includes estimating a worst negative slack and a worst hold slack from the netlist, and the features includes the worst negative slack and the worst hold slack (Saha paragraph [0041], wherein node features include worst slack).
Regarding Claim 10, Saha further teaches wherein:
the circuit design is targeted for implementation on a target integrated circuit (IC) device (Saha paragraphs [0017]-[0018], wherein the circuit design is targeted to be manufactured as an ASIC, FPGA, SOC, etc…); and
identifying the features includes indicating a number of programmable processors and a number of transceivers available on the target IC device (Saha paragraph [0118], wherein features of target devices include programmable processors and transceivers).
Regarding Claim 12, Saha teaches a method comprising:
synthesizing and performing logic optimization on circuit designs of a training set to generate respective netlists by a design tool (Saha paragraphs [0032] and [0036]-[0038], wherein RTL descriptions of a circuit design are synthesized into netlists based on multiple instances of input feature data sets corresponding to different types of circuit designs used to train a model);
determining respective feature sets of the netlists by the design tool (Saha paragraph [0044], wherein features of the netlist are extracted);
performing placement and routing on the netlists to generate placed-and-routed designs (Saha paragraphs [0037] and [0044], wherein the input feature data set includes full layout descriptions or outputs of physical synthesis stages, physical synthesis stages including performing placement and routing);
determining respective congestion levels from the placed-and-routed designs (Saha paragraphs [0037]-[0038], [0046] and [0059], wherein congestion is determined as labeled output data); and
training a classification model using the respective features sets and respective congestion levels (Saha paragraphs [0035]-[0036], wherein models are trained based on the input feature data set and the labeled output data).
Saha does not explicitly teach training a classification model using the respective features sets and respective congestion levels for automatically selecting one or more directives for placement and routing to reduce routing congestion during at least one placement and routing phase of an implementation flow.
Dasasathyan teaches training a classification model using the respective features sets and respective congestion levels for automatically selecting one or more directives for placement and routing to reduce routing congestion during at least one placement and routing phase of an implementation flow (Dasasathyan Col. 6, Lines 32-61 and Col. 8, Lines 1-67, wherein classification models are used to automatically select routing strategies and directives including directives for reducing congestion).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saha and Dasasathyan to apply the known technique of automatically selecting routing strategies and directives to improve on a routing solution as taught by Dasasathyan to improve on the routing solutions at taught by Saha, yielding the predictable results of an improved routing solution to meet design specifications.
Regarding Claim 13, Saha further teaches wherein:
the circuit designs are targeted for implementation on a target integrated circuit (IC) device (Saha paragraphs [0017]-[0018], wherein the circuit design is targeted to be manufactured as an ASIC, FPGA, SOC, etc…); and
determining the respective feature sets includes determining for each circuit design, one or more levels of utilization by the netlist of one or more types of circuit elements, respectively, of the target IC device (Saha paragraph [0059], wherein feature extraction includes determining the utilization of circuits).
Regarding Claim 14, Saha further teaches wherein:
the circuit designs are targeted for implementation on a target integrated circuit (IC) device (Saha paragraphs [0017]-[0018], wherein the circuit design is targeted to be manufactured as an ASIC, FPGA, SOC, etc…); and
determining the respective feature sets includes determining for each circuit design, a high-fanout indicator (Saha paragraphs [0041] and [0058]-[0059], wherein features include counts of fan-out).
Regarding Claim 15, Saha further teaches wherein determining the respective feature sets includes estimating a worst negative slack and a worst hold slack from each netlist, and each feature set includes the worst negative slack and the worst hold slack (Saha paragraph [0041], wherein node features include worst slack).
Regarding Claim 16, Saha further teaches wherein:
the circuit designs are targeted for implementation on a target integrated circuit (IC) device (Saha paragraphs [0017]-[0018], wherein the circuit design is targeted to be manufactured as an ASIC, FPGA, SOC, etc…); and
determining the respective feature sets includes indicating a number of programmable processors and a number of transceivers available on the target IC device (Saha paragraph [0118], wherein features of target devices include programmable processors and transceivers).
Regarding Claim 17, Saha teaches a system comprising:
one or more computer processors configured to execute program code (Saha paragraph [0069], see microprocessor); and
a memory arrangement coupled to the one or more computer processors, wherein the memory arrangement is configured with instructions of a design tool (Saha paragraph [0071], see data stores having machine readable instructions) that when executed by the one or more computer processors cause the one or more computer processors to perform operations including:
synthesizing a circuit design into a netlist (Saha paragraphs [0020] and [0026], wherein logic synthesis is performed on an RTL description of a circuit design that produces a netlist);
identifying features from the netlist (Saha paragraphs [0031], [0041]-[0042] and [0044], wherein the netlist is processed to extract path and node level features);
applying a congestion prediction model to the features prior to placement, wherein application of the congestion prediction model generates a prediction value indicative of a congestion level likely to result from placement and routing of the netlist (Saha paragraph [0046], wherein a machine learning model is used to predict congestion values); and
in response to the prediction value indicating the congestion level is greater than a threshold:
determining an implementation-flow action (Saha paragraphs [0026]-[0027] and [0031], wherein if target optimization goals and quality metrics thresholds are not satisfied, changes to the design parameters are implemented), and
performing the implementation-flow action to generate implementation data that is suitable for making an integrated circuit (IC) (Saha paragraph [0031], wherein the changes are implemented until a solution that meets optimization goals and quality metrics is achieved).
Saha does not explicitly teach the implementation-flow action including automatically selecting one or more directives for placement and routing to reduce routing congestion during at least one placement and routing phase of the implementation flow.
Dasasathyan teaches the implementation-flow action including automatically selecting one or more directives for placement and routing to reduce routing congestion during at least one placement and routing phase of the implementation flow (Dasasathyan Col. 6, Lines 32-61 and Col. 8, Lines 1-67, wherein strategies are automatically selected which contain directives for placement and routing, directives including routing directives to choose alternative routing algorithms that may reduce routing congestion).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saha and Dasasathyan to apply the known technique of automatically selecting routing strategies and directives to improve on a routing solution as taught by Dasasathyan to improve on the routing solutions at taught by Saha, yielding the predictable results of an improved routing solution to meet design specifications.
Regarding Claim 18, Saha further teaches wherein:
the instructions for determining the implementation-flow action include instructions for determining parameter settings for a placement process or a routing process of the design tool (Saha paragraphs [0027], [0031] and [0046], wherein design parameters for the design process may be modified, the design process including physical synthesis which includes placement and routing); and
the instructions for performing the implementation-flow action include instructions for executing the placement process and the routing process using the parameters settings (Saha paragraph [0031], wherein the settings are iteratively changed and input to the machine learning model to determine if the predicted values meet design specifications).
Regarding Claim 19, Saha further teaches wherein the instructions of the design tool includes instructions for bypassing determining the parameter settings and executing the placement process and the routing process of the design tool in response to the prediction value indicating the congestion level is less than a threshold (Saha paragraph [0031], wherein if optimization goals and quality metrics are achieved, the circuit solution is acceptable and does not need changes).
Regarding Claim 20, Saha further teaches wherein:
the instructions for determining the implementation-flow action include instructions for determining modifications to make to the circuit design (Saha paragraphs [0026]-[0027] and [0031], wherein if target optimization goals and quality metrics thresholds are not satisfied, changes to the design parameters are implemented); and
the instructions for performing the implementation-flow action include instructions for modifying the circuit design to include the modifications (Saha paragraph [0031], wherein the changes are implemented until a solution that meets optimization goals and quality metrics is achieved).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Saha modified by Dasasathyan as applied to claim 1 above, and further in view of Varadrajan et al., hereinafter Varadrajan, US Patent No. 8,745,567.
Regarding Claim 11, Saha modified by Dasasathyan does not explicitly teach wherein identifying the features includes estimating interconnection complexity from the netlist using Rent's rule.
Varadrajan teaches wherein identifying the features includes estimating interconnection complexity from the netlist using Rent's rule (Varadrajan Col. 6, Lines 36-47, wherein routing congestion severity is calculated using Rent’s rule).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Saha modified by Dasasathyan and Varadrajan because the combination would allow the routing congestion severity as taught by Varadrajan to be predicted by the machine learning model as taught by Saha modified by Dasasathyan, yielding the predictable results of faster circuit design optimization, thereby saving design time and costs.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been fully considered but are moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC D LEE/Primary Examiner, Art Unit 2851
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