DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CONTINUED EXAMINATION UNDER 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/6/2026 has been entered.
RESPONSE TO ARGUMENTS
Applicant’s arguments with respect to claims 1-24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
I. REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-24 are rejected under 35 U.S.C. 103 as being unpatentable over Byeon et al. (US Pub.: 2023/0146647) in view of Nikibly et al. (US Patent 11,880,327), Black et al. (US Pub.: 2012/0210071), and Wein et al. (US Pub.: 2012/0180068).
As per claim 1, Byeon teaches/suggest a method comprising: running, with a first core of a first multiprocessor system on chip (MPSoC) of a distributed computing architecture, a first process/thread on input data, the first process/thread pinned to the first core (e.g. associated with a first SOC using CPUs, GPUs processors, and/or accelerators for processing first process/thread : Fig. 11C-11D; Fig. 16A; [0174]-[0176]; [0180]; [0295]; [0473]); operating with the first process/thread; operating with a second process/thread pinned to a second core of a second MPSoC of the distributed computing architecture (e.g. associated with a second SOC using CPUs, GPUs processors, and/or accelerators for processing second process/thread : Fig. 11C-11D; Fig. 16A; [0174]-[0176]; [0180]; [0295]; [0473]); and running, with the second core of the second MPSoC, the second process/thread on data (e.g. associated with a second SOC using CPUs, GPUs processors, and/or accelerators for processing second process/thread : Fig. 11C-11D; Fig. 16A; [0174]-[0176]; [0180]; [0295]; [0473]), wherein the first MPSoC and the second MPSoC each have multiple cores that operating with a pinned process while operating with other MPSoC in the distributed computing architecture (Fig. 11C-11D; Fig. 16A; [0173]-[0257]; [0285]-[0295]; and [0473]-[0480]).
Byeon does not teach the method comprising:
storing, using a cache coherency fabric, first data in shared memory, the first data generated by first;
fetching the first data from the shared memory; and
operating with the first data,
that can be assigned to a process from any other.
Nikibly teaches/suggest a method comprising: using a cache coherency fabric (e.g. associated coherent interconnect between SOCs: Fig. 1) (Fig. 1; and col. 1, l. 46 to col. 5, l. 14).
Black teaches/suggest a method comprising: storing first data in shared memory, the first data generated by first (e.g. associated with core 4 writing to memory of core 1: [0028]); fetching the first data from the shared memory; and operating with the first data (e.g. associated with process running on core 1 accessing data written by core 4 as input: [0028]) (Fig. 4; and [0027]-[0030]).
Wein aches/suggest a method comprising: that can be assigned to a process from any other (e.g. associated with moving tasks from a physical CPU chip to another physical CPU chip) (Fig. 6; [0017]-[0018]; [0079]; and [0163]).
It would have been obvious for one of ordinary skill in this art, before the effective filing date of the claimed invention, to include Nikibly’s coherency architecture, Black’s coherency operations, and Wein’s moving of tasks into Byeon’s architecture for the benefit of improving system timing (Nikibly, col. 3, ll. 4-5), implementing a simple and effective manner to transfer data while reducing overhead (Black, [0028]) and dynamically optimizing performance (Wein, [0163])to obtain the invention as specified in claim 1.
As per claim 2, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 1 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method further comprising: storing second data generated by the second process/thread in the shared memory or other memory (e.g. associated with maintaining cache coherency among processing elements as the second processing element generates corresponding data) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 3, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 1 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the input data is sensor data, the first process/thread implements a first portion of a deep learning network, and the second process/thread implements a second portion of the deep learning network that is different than the first portion (e.g. Byeon, Fig. 9; [0129]; [0180]; [0186]; [0207]-[0209]; [0255]) [(Byeon, Fig. 9; Fig. 11C-11D; Fig. 16A; [0129]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 4, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 3 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the sensor data is at least one of two-dimensional (2D) data or three-dimensional (3D) data (e.g. Byeon, [0207]-[0209]; [0255]; [0480]) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 5, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 1 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the first process/thread or second process/thread implements at least one multiply-and-accumulate operation (e.g. Byeon, [0511]-[0512]) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; [0511]-[0512]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 6, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 1 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the first process/thread and second process/thread implement different tasks in a processing pipeline of an autonomous vehicle (AV) (e.g. Byeon, [0152]-[0153]) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0151]-[0156]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 7, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 6 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the first process/thread includes localization of the AV and the second process/thread includes route planning for the AV (e.g. Byeon, [0151]-[0156]; [0158]; [0195]) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0151]-[0156]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 8, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 6 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the first process/thread includes a first perception task and the second process/thread includes a second perception task that is different than the first perception task (e.g. Byeon, [0185]) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0151]-[0156]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 9, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 8 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the first perception task includes object classification and the second perception task includes object localization (e.g. Byeon, [0158]; [0185]; [0195]; [0256]) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0151]-[0156]; [0173]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 10, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 1 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the shared memory includes at least one lockless ring buffer (e.g. associated with use of circular buffer for real-time operations) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0173]-[0186]; [0251]-[0257]; [0285]-[0295]; [0473]-[0480]; [0550]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; [0037]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 11, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 1 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the second process/thread fetches a portion of at least one buffer in shared memory (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0173]-[0186]; [0251]-[0257]; [0285]-[0295]; [0364]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; Black, Fig. 4; [0027]-[0030]; [0037]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claim 12, Byeon, Nikibly, Black and Wein teach/suggest all the claimed features of claim 1 above, where Byeon, Nikibly, Black and Wein further teach/suggest the method comprising: wherein the second process/thread skips at least one buffer of first data when fetching the first data from the shared memory (e.g. associated with real-time operations as data is access based on timing rather than order of data being buffered) (Byeon, Fig. 11C-11D; Fig. 16A; [0129]; [0173]-[0186]; [0251]-[0257]; [0285]-[0295]; [0473]-[0480]; Nikibly, Fig. 1; col. 1, l. 46 to col. 5, l. 14; col. 15, ll. 8-30; Black, Fig. 4; [0027]-[0030]; [0037]; and Wein, Fig. 6; [0017]-[0018]; [0079]; [0163]).
As per claims 13-24, claims 13-24 are rejected in accordance to the same rational and reasoning as the above rejection of claims 1-12 as claims 13-24 is the distributed computing architecture carrying out the method of claims 1-12.
II. CLOSING COMMENTS
CONCLUSION
STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-24 have received a first action on the merits and are subject of a first action non-final.
DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHUN KUAN LEE whose telephone number is (571)272-0671. The examiner can normally be reached Monday-Friday.
IMPORTANT NOTE
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached on (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHUN KUAN LEE/Primary Examiner
Art Unit 2181 March 06, 2026