DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (claims 1-8, the device) in the reply filed on 10/24/2025 is acknowledged.
Examiners interpretation:
Under broadest reasonable interpretation the term “on” includes the use as “a function word to indicate position in close proximity with” [Merriam-Webster]. The examiner is using this interpretation of the term “on” to interpret and meet the the limitations of the claims. If the attorney does not wish to include this meaning or if the attorney intends the relative term “on” to have a narrower interpretation, the examiner recommends amending the claims by further defining the relative positions of the claimed elements within the language of the claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over US 20180277430 A1 Xie et al hereafter “Xie” and further in view of US 20150255571 A1 Xu et al hereafter “Xu
Claim 1 Xie teaches a semiconductor structure, comprising:
a base (102 fig. 2Q);
a plurality of gate structures (101A-C and/or 104 fig. 2Q), separately arranged on the base;
a first spacer (not illustrated but explicitly disclosed Paragraph [0023], “the final gate structure 104 typically includes a gate insulation layer (not separately shown), such as silicon dioxide or a high-k (k value greater than 10) insulating material, and one or more layers of conductive material (not separately shown) that act as the gate electrode, e.g., a metal, a metal alloy, titanium nitride, tantalum nitride, tungsten, aluminum, polysilicon, etc.”)
a source/drain doped region (comprising 114 fig. 2Q, “semiconductor material 114 that was formed in the source/drain regions of the transistor device” [Paragraph 0024], disclosed as doped paragraph [0022] “various doped regions, e.g., source/drain regions”), arranged within the base on two sides (a left and right-side fig. 2Q) of the gate structures of the plurality of gate structures [sufficiently illustrated fig. 2Q];
a first dielectric layer (110 fig. 2Q), arranged on the gate structures of the plurality of gate structures [met under broadest reasonable interpretation 110 is “on” the left and right side of the gate structures of the plurality of gate fig. 2Q] and on the base [sufficiently illustrated fig. 2Q] and the source/drain doped region that are located on a side of the first spacer;
a source/drain interconnecting layer (comprising 112R and/or 141 fig. 2Q), extending through the first dielectric layer on a top of the source/drain doped region [met under broadest reasonable interpretation extends through the center/middle of the collective 110 layers], wherein a sidewall of the source/drain interconnecting layer is spaced apart from a sidewall of the first spacer [sufficiently illustrated fig. 2Q 141 and/or 122R are spaced apart from 104 comprising the first spacer and gate electrode];
an air gap (the width of 128 fig. 2Q), arranged between the first spacer and the source/drain interconnecting layer [sufficiently illustrated fig. 2Q wherein the gate 104 comprises the first spacer and gate electrode]; a second spacer (comprising 130, 126 and 108R fig. 2Q), arranged on a bottom of the air gap and on the source/drain interconnecting layer exposed from the air gap [sufficiently illustrated fig. 2Q, a portion of 126 and all of 108R are arranged on a bottom of the air gap 128]; and
a sealing layer (134 fig. 2Q, met under broadest reasonable as it seals and/or encapsulates the top of the device ), sealing a top of the air gap [met under broadest reasonable interpretation the sealing layer 134, seals the top of the air gap within the device], an air spacer (128 fig. 2Q) and along a direction perpendicular to the sidewall of the first spacer [left to right of fig. 2Q], a width of a part of the air spacer away from the base is greater than a width of a part of the air spacer close to the base [sufficiently illustrated fig. 2Q with the oval shape that has a smaller width at the bottom and a large width in the center, see annotation below].
Xie does not explicitly illustrate/teach the first spacer, arranged on a sidewall of each of the gate structures of the plurality of gate structures; Nor the sealing layer, the first spacer, and the second spacer form an air spacer.
Xu teaches a first spacer (136a fig. 19, illustrated but not labeled fig. 20), arranged on a sidewall (left and right sidewalls) of each of a gate structure (304 fig. 19 and 20); and a sealing layer (136c fig. 20), the first spacer, and a second spacer (136b fig. 19, illustrated but not labeled fig. 20) form an air spacer (120 fig. 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to rearrange the device Xie teaches in view of the device and Xu teaches such that the “first spacer, arranged on a sidewall of each of the gate structures of the plurality of gate structures; and the sealing layer, the first spacer, and the second spacer form an air spacer” as rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 VI. C.] and/or to reduce parasitic capacitance and/or improve AC performance and/or delay time and/or switch energy [Xu paragraph 0060] and/or art recognized equivalence for the same purpose [2144.06 I.] where the purpose is forming an airgap to reduce parasitic capacitance and/or isolate adjacent conductive structures [Xu paragraph 0060].
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Xie annotated fig. 2Q: highlighting the widths of part of the air spacer
Claim 2 Xie in view of Xu teaches the semiconductor structure according to claim 1, wherein:
the source/drain interconnecting layer comprises a bottom interconnecting layer (122R fig. 2Q) and a top interconnecting layer (141 fig. 2Q) on the bottom interconnecting layer, and along a direction perpendicular to an extending direction of the gate structure, a sidewall of the top interconnecting layer is retracted relative to a sidewall of the bottom interconnecting layer on a same side [sufficiently illustrated fig. 2Q, see annotation below].
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Xie Annotated fig. 2Q: highlighting the sidewalls
Claim 3 Xie in view of Xu the semiconductor structure according to claim 1, wherein:
the air spacer comprises a first portion [see annotation below, met under broadest reasonable interpretation] and a second portion on the first portion [see annotation below, met under broadest reasonable interpretation], and along the direction perpendicular to the sidewall of the first spacer, a width of the second portion is greater than a width of the first portion [sufficiently illustrated fig. 2Q see annotation below].
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Xie Annotated fig. 20: highlighting the first portion and the second portion
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Xie annotated fig. 2Q: highlighting the widths of a first portion and the width of a second portion
Claim 4 Xie in view of Xu teaches as shown above the semiconductor structure according to claim 3, wherein the second spacer comprises:
a first spacer material layer (108R fig. 2Q), arranged on a bottom of the first portion [sufficiently illustrated fig. 2Q] and on the bottom interconnecting layer exposed from the first portion [sufficiently illustrated fig. 2Q];
a second spacer material layer (126 fig. 2Q), arranged on a top surface of the bottom interconnecting layer exposed from the second portion and covering a top of the first spacer material layer [sufficiently illustrated fig. 2Q at least a portion of 126]; and a third spacer material layer (130 fig. 2Q), arranged on a sidewall of the top interconnecting layer and connected to the second spacer material layer [sufficiently illustrated fig. 2Q]; or the second spacer is integrally formed [sufficiently illustrated fig. 2Q under broadest reasonable interpretation, fig. 2Q illustrates and single integrated and/or integral device as such all components within the device are considered integral and/or integrated to each other].
Xie in view of Xu does not teach the second spacer material exposed from the second portion.
The limitation “or the second spacer is integrally formed” has been matched above, thus the alternative limitation the second spacer material is “exposed from the second portion” in “a first spacer material layer, arranged on a bottom of the first portion and on the bottom interconnecting layer exposed from the first portion; a second spacer material layer, arranged on a top surface of the bottom interconnecting layer exposed from the second portion and covering a top of the first spacer material layer; and a third spacer material layer, arranged on a sidewall of the top interconnecting layer exposed from the second portion and connected to the second spacer material layer” is not required to be met as its alternative is met however for the sake of compact prosecution the below alternative modification is shown.
It would have been obvious to one of ordinary skill in the art to modify the device Xie in view of Xu teaches such that the second spacer material is “exposed from the second portion” as rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 VI. C.].
Also, should the applicant disagree with the examiner interpretation of “integrally formed” as applied to the prior art.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xie in view of XU teaches such that “the second spacer is integrally formed” as making and/or forming components integrally is prima facie type obviousness [see MPEP MPEP 2144.04 V. B.]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device Xie in view of Xu teaches such that the second spacer material is “exposed from the second portion” as rearrangement of parts is prima facie type obviousness [see MPEP 2144.04 VI. C.].
Claim 5 Xie in view of Xu teaches as shown above the semiconductor structure according to claim 4, wherein a material of the first spacer material layer (Silicon nitride paragraph 0023) is the same as a material of the second spacer material layer (Silicon nitride paragraph 0030) and the third material layer is formed from any desired material [Paragraph 0032]
Xie in view of Xu does not explicitly teach a material of the third spacer material layer is the same as the first spacer material layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to selection the known material of Silicon Nitride for the device of Xie in view of Xu such that “a material the third spacer material layer” is the same as the first as selection of a known material for it’s know material properties (dielectric) is prima facie type obviousness [see MPEP 2144.07]
Claim 7 Xie in view of Xu teaches the semiconductor structure according to claim 1, wherein:
a material of the first spacer comprises at least one of silicon oxide, a low-k dielectric material, or an ultra-low-k dielectric material [Paragraph 0023 “Silicon dioxide” sufficiently meets the limitation as Low-K and ultra-low-k dielectric materials are relative terms and what K values constitute low-K and ultra-low-K is not further defined within the claims, note preferred embodiments within the specification do not constitute definitions];
a material of the sealing layer comprises at least one of silicon oxide, silicon nitride, a low- k dielectric material, or an ultra-low-k dielectric material [Paragraph 0035 “Silicon dioxide” sufficiently meets the limitation as Low-K and ultra-low-k dielectric materials are relative terms and what K values constitute low-K and ultra-low-K is not further defined within the claims, note preferred embodiments within the specification do not constitute definitions]; and
a material of the second spacer comprises at least one of silicon oxide, silicon nitride, a low-k dielectric material, or an ultra-low-k dielectric material [the second spacer comprises at least 126 “Silicon nitride” Paragraph [0030] and/or 108 “silicon nitride” Paragraph [0023]].
Claim 8 Xie in view of Xu teaches the semiconductor structure according to claim 1,
Xie in view of Xu does not teach a thickness of the second spacer on the bottom of the air gap ranges from 0.5 nm to 2 nm.
It would have been obvious ne one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Xie in view of Xu such that “a thickness of the second spacer on the bottom of the air gap ranges from 0.5 nm to 2 nm” as a part of routine optimization of parasitic capacitance and/or AC performance and/or delay time and/or switch energy [Xu paragraph 0060] [see MPEP 2144.05 II.].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Xie in view of Xu as applied the claims above, and further in view of US 20200203497 A1 Xie et al “Xie 2020”.
Claim 6 Xie in view of Xu teaches as shown above the semiconductor structure according to claim 1, wherein:
the sealing layer is arranged on the first dielectric layer [sufficiently illustrated fig. 2Q] and the gate structure [sufficiently illustrated fig. 2Q] and seals the top of the air gap [met under broadest reasonable interpretation of Xie fig. 2Q as discussed above in claim 1, and/or met in view of the modification in view of Xu illustrated fig. 20 Xu.]
Xie in view of Xu does not teach the semiconductor structure further comprises a planarization stop layer arranged between the first dielectric layer and the sealing layer and between a top of the gate structure and the sealing layer.
Xie 2020 teaches a semiconductor structure further comprises a planarization stop layer (117 fig. 39 sufficiently met by “etch stop layer” and Planarization is and/or maybe a type of etching) arranged between a first dielectric layer (109 fig. 39) and a sealing layer (119 fig. 39, met under broadest reasonable interpretation 119 seals and/or encapsulates the top of the device) and between a top of the gate structure (comprising at least 110 and 108 fig. 39) and the sealing layer [sufficiently illustrated fig. 39].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Xie in view of Xu with the device of Xie 2020 such that “the semiconductor structure further comprises a planarization stop layer arranged between the first dielectric layer and the sealing layer and between a top of the gate structure and the sealing layer” to stop any subsequent etching and/or planarization process from etching and/or planarizing the underlying layers [sufficiently disclosed Xie 2020 paragraph 0029 “the etching process stops on the etch stop layer”]
Conclusion
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893