DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 3/5/2026 is acknowledged.
Applicant amended claims 1, 3, 4, and 6.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/25/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, 18, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2021/0098592) (hereafter Kang), in view of Cheng et al. (US 9716158 B1) (hereafter Cheng158).
Regarding claim 1, Kang discloses a semiconductor structure, comprising:
a substrate (101 and 105 in Fig. 8, paragraph 0023);
a gate 165 (Fig. 8, paragraph 0070) on the substrate (101 and 105 in Fig. 8);
a sidewall structure 163 (Fig. 8, paragraph 0090) on sidewalls at two sides of the gate 165 (Fig. 8);
a source/drain region 150 (Fig. 8, paragraph 0023) in the substrate (101 and 105 in Fig. 8) at two sides of the gate 165 (Fig. 8) and the sidewall structure 161 (Fig. 8);
a source/drain electrical connection layer 180 (Fig. 8, paragraph 0023) on the source/drain region 150 (Fig. 8); and
an isolation structure (161, 169, and 162 in Fig. 8, paragraph 0030) between the source/drain electrical connection layer 180 (Fig. 8) and the gate 165 (Fig. 8), wherein
the isolation structure (161, 169, and 162 in Fig. 8) includes a cavity 169 (Fig. 8, paragraph 0030) and a first isolation layer (161 and 162 in Fig. 8, paragraph 0030),
the cavity 169 (Fig. 8) includes a first cavity region (lower region of 169 in Fig. 8) and a second cavity region (upper region of 169 in Fig. 8) located on the first cavity region (lower region of 169 in Fig. 8),
the second cavity region (upper region of 169 in Fig. 8) includes sidewalls formed by the first isolation layer (161 and 162 in Fig. 8), and the first isolation layer (161 and 162 in Fig. 8) is above the first cavity region (lower region of 169 in Fig. 8), such that a width of the second cavity region (upper region of 169 in Fig. 8) is smaller than a width of the first cavity region (lower region of 169 in Fig. 8); and
a top surface of the second cavity region (upper region of 169 in Fig. 8) is higher than a top surface of the gate 165 (Fig. 8).
Kang does not disclose the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer.
Cheng158 discloses the top surface of the second cavity region (upper region of 40 in Fig. 8A, second paragraph in Col. 10) is coplanar with a top surface of the source/drain electrical connection layer (element number is not shown in Fig. 8A but see 38 in Fig. 7A, second paragraph in Col. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang to form the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer, as taught by Cheng158, since the gaps 40 (Cheng158, Fig. 8A, second paragraph in Col. 10) remain unfilled during subsequent processing steps to reduce parasitic capacitance between the gate stacks and the metal source/drain contacts 38 (Cheng158, Fig. 7A, second paragraph in Col. 10) of the resulting structure.
Regarding claim 2, Kang in view of Cheng158 discloses the semiconductor structure according to claim 1, however Kang does not explicitly disclose the width of the second cavity region is less than approximately 3 nanometers; and the width of the first cavity region is in a range approximately from 4 nanometers to 8 nanometers.
Regarding the limitation, “the width of the second cavity region is less than approximately 3 nanometers; and the width of the first cavity region is in a range approximately from 4 nanometers to 8 nanometers”, Kang discloses the width (W1 in Fig. 2B, paragraph 0039) of the second cavity region (upper region of 169 in Fig. 2B) is in range (see paragraph 0039) of approximately 40 Å to 60 Å; and the width (W1 in Fig. 2B) of the second cavity region (upper region of 169 in Fig. 2B) decreases in upward direction. In addition, Kang discloses the width (W2 in Fig. 2B, paragraph 0039) of the first cavity region (lower region of 169 in Fig. 2B) is in range (see paragraph 0039) of approximately 40 Å to 60 Å. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang to form the width of the second cavity region is less than approximately 3 nanometers; and the width of the first cavity region is in a range approximately from 4 nanometers to 8 nanometers, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 3, Kang discloses a semiconductor structure comprising:
a substrate (101 and 105 in Fig. 8, paragraph 0023);
a gate 165 (Fig. 8, paragraph 0070) on the substrate (101 and 105 in Fig. 8);
a sidewall structure 163 (Fig. 8, paragraph 0090) on sidewalls at two sides of the gate 165 (Fig. 8);
a source/drain region 150 (Fig. 8, paragraph 0023) in the substrate (101 and 105 in Fig. 8) at two sides of the gate 165 (Fig. 8) and the sidewall structure 161 (Fig. 8);
a source/drain electrical connection layer 180 (Fig. 8, paragraph 0023) on the source/drain region 150 (Fig. 8); and
an isolation structure (161, 169, and 162 in Fig. 8, paragraph 0030) between the source/drain electrical connection layer 180 (Fig. 8) and the gate 165 (Fig. 8), wherein
the isolation structure (161, 169, and 162 in Fig. 8) includes a cavity 169 (Fig. 8, paragraph 0030), the cavity 169 (Fig. 8) includes a first cavity region (lower half region of 169 in Fig. 8) and a second cavity region (upper half region of 169 in Fig. 8) located on the first cavity region (lower half region of 169 in Fig. 8), and a width of the second cavity region (upper half region of 169 in Fig. 8) is smaller (see Fig. 8, wherein a horizontal length of upper half region of 169 is smaller than a horizontal length of lower half region of 169) than a width of the first cavity region (lower half region of 169 in Fig. 8), wherein: a ratio (see Fig. 8, wherein a vertical length of upper half region of 169 is same as a vertical length of lower half region of 169 such that the ratio is 1:1) of a length of the second cavity region (upper half region of 169 in Fig. 8) to a length of the first cavity region (lower half region of 169 in Fig. 8) is in a range approximately from 1:3 to 1:1, and
a top surface of the second cavity region (upper half region of 169 in Fig. 8) is higher than a top surface of the gate 165 (Fig. 8).
Kang does not disclose the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer.
Cheng158 discloses the top surface of the second cavity region (upper region of 40 in Fig. 8A, second paragraph in Col. 10) is coplanar with a top surface of the source/drain electrical connection layer (element number is not shown in Fig. 8A but see 38 in Fig. 7A, second paragraph in Col. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang to form the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer, as taught by Cheng158, since the gaps 40 (Cheng158, Fig. 8A, second paragraph in Col. 10) remain unfilled during subsequent processing steps to reduce parasitic capacitance between the gate stacks and the metal source/drain contacts 38 (Cheng158, Fig. 7A, second paragraph in Col. 10) of the resulting structure.
Regarding claim 4, Kang (utilized different elements for an isolation structure and a cavity as applied in claim 1 in the above) discloses a semiconductor structure, comprising:
a substrate (101 and 105 in Fig. 8, paragraph 0023);
a gate 165 (Fig. 8, paragraph 0070) on the substrate (101 and 105 in Fig. 8);
a sidewall structure 163 (Fig. 8, paragraph 0090) on sidewalls at two sides of the gate 165 (Fig. 8);
a source/drain region 150 (Fig. 8, paragraph 0023) in the substrate (101 and 105 in Fig. 8) at two sides of the gate 165 (Fig. 8) and the sidewall structure 161 (Fig. 8);
a source/drain electrical connection layer 180 (Fig. 8, paragraph 0023) on the source/drain region 150 (Fig. 8); and
an isolation structure (161, 169, 162, and 172 in Fig. 8) between the source/drain electrical connection layer 180 (Fig. 8) and the gate 165 (Fig. 8), wherein
the isolation structure (161, 169, 162, and 172 in Fig. 8) includes a cavity 169 (Fig. 8, paragraph 0030) and a first isolation layer (161 and 162 in Fig. 8, paragraph 0030),
the cavity 169 (Fig. 8) includes a first cavity region (left 169 in Fig. 8) and a second cavity region (right 169 in Fig. 8) located on (see Fig. 8, wherein left 169 is laterally on right 169) the first cavity region (left 169 in Fig. 8),
the second cavity region (right 169 in Fig. 8) includes sidewalls formed by the first isolation layer (161 and 162 in Fig. 8), and the first isolation layer (161 and 162 in Fig. 8) is above the first cavity region (left 169 in Fig. 8), such that a width (horizontal length of upper portion of right 169 in Fig. 8) of the second cavity region (right 169 in Fig. 8) is smaller than a width (horizontal length of lower portion of left 169 in Fig. 8) of the first cavity region (left 169 in Fig. 8);
a top surface of the second cavity region (right 169 in Fig. 8) is higher than a top surface of the gate 165 (Fig. 8);
wherein the isolation structure (161, 169, 162, and 172 in Fig. 8) further includes a second isolation layer 172 (Fig. 8, paragraph 0035) located on a sidewall of the source/drain electrical connection layer 180 (Fig. 8);
a cavity groove (element number is not shown in Fig. 8 but see 269 in Fig. 10A, paragraph 0077) exists between (see Fig. 8, wherein left 169 is between left 163 and rightmost portion of 172) the sidewall structure 163 (Fig. 8) and the second isolation layer 172 (Fig. 8);
the first isolation layer (161 and 162 in Fig. 8) is located on an upper portion of a sidewall surface of the cavity groove (element number is not shown in Fig. 8 but see 269 in Fig. 10A) such that the cavity groove (element number is not shown in Fig. 8 but see 269 in Fig. 10A) is divided into the first (left 169 in Fig. 8) and second cavity regions (right 169 in Fig. 8).
Kang does not disclose the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer.
Cheng158 discloses the top surface of the second cavity region (upper region of 40 in Fig. 8A, second paragraph in Col. 10) is coplanar with a top surface of the source/drain electrical connection layer (element number is not shown in Fig. 8A but see 38 in Fig. 7A, second paragraph in Col. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang to form the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer, as taught by Cheng158, since the gaps 40 (Cheng158, Fig. 8A, second paragraph in Col. 10) remain unfilled during subsequent processing steps to reduce parasitic capacitance between the gate stacks and the metal source/drain contacts 38 (Cheng158, Fig. 7A, second paragraph in Col. 10) of the resulting structure.
Regarding claim 6, Kang discloses a method of forming a semiconductor structure, comprising:
forming a gate 165 (Fig. 8, paragraph 0070) on a substrate (101 and 105 in Fig. 8, paragraph 0023),
forming a sidewall structure 163 (Fig. 8, paragraph 0090) on sidewalls at two sides of the gate 165 (Fig. 8), and a source/drain region 150 (Fig. 8, paragraph 0023) in the substrate (101 and 105 in Fig. 8) at two sides of the gate 165 (Fig. 8) and the sidewall structure 163 (Fig. 8);
forming a source/drain electrical connection layer 180 (Fig. 8, paragraph 0023) on the source/drain region 150 (Fig. 8); and
forming an isolation structure (161, 169, and 162 in Fig. 8, paragraph 0034) between the gate 165 (Fig. 8) and the source/drain electrical connection layer 180 (Fig. 8),
the isolation structure (161, 169, and 162 in Fig. 8) includes a cavity (left 169 in Fig. 8) and a first isolation layer (left 161 and left 162 in Fig. 8, paragraph 0030),
the cavity (left 169 in Fig. 8) includes a first cavity region (lower region of left 169 in Fig. 8) and a second cavity region (upper region of left 169 in Fig. 8) located on the first cavity region (lower region of left 169 in Fig. 8),
the second cavity region (upper region of left 169 in Fig. 8) includes sidewalls formed by the first isolation layer (left 161 and left 162 in Fig. 8) and the first isolation layer (left 161 and left 162 in Fig. 8) is formed above the first cavity region (lower region of left 169 in Fig. 8), such that a width of the second cavity region (upper region of left 169 in Fig. 8) is smaller than a width of the first cavity region width (lower region of left 169 in Fig. 8); and
a top surface of the second cavity region (upper region of 169 in Fig. 8) is higher than a top surface of the gate 165 (Fig. 8).
Kang does not disclose the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer.
Cheng158 discloses the top surface of the second cavity region (upper region of 40 in Fig. 8A, second paragraph in Col. 10) is coplanar with a top surface of the source/drain electrical connection layer (element number is not shown in Fig. 8A but see 38 in Fig. 7A, second paragraph in Col. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang to form the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer, as taught by Cheng158, since the gaps 40 (Cheng158, Fig. 8A, second paragraph in Col. 10) remain unfilled during subsequent processing steps to reduce parasitic capacitance between the gate stacks and the metal source/drain contacts 38 (Cheng158, Fig. 7A, second paragraph in Col. 10) of the resulting structure.
Regarding claim 7, Kang further discloses the method according to claim 6, wherein the isolation structure (161, 169, and 162 in Fig. 8) further includes:
a second isolation layer (right 161 and right 162 in Fig. 8, paragraph 0030) located on a sidewall of the source/drain electrical connection layer 180 (Fig. 8), wherein:
a cavity groove (element number is not shown in Fig. 8 but see 269 in Fig. 10A, paragraph 0077) exists between (see Fig. 8, wherein right 169 is between left 163 and right 162) the sidewall structure 163 (Fig. 8) and the second isolation layer (right 161 and right 162 in Fig. 8);
the first isolation layer (left 161 and left 162 in Fig. 8) is located on a portion of a sidewall surface of the cavity groove (element number is not shown in Fig. 8 but see 269 in Fig. 10A, paragraph 0077); and
the second cavity region (upper region of left 169 in Fig. 8) is located between the first isolation layers (left 161 and left 162 in Fig. 8).
Regarding claim 8, Kang further discloses the method according to claim 7, wherein a method of forming the isolation structure (161, 169, and 162 in Fig. 8) includes:
forming a first sacrificial layer 268 (Fig. 9, paragraph 0064) on the sidewall structure 263 (Fig. 9); and
forming the second isolation layer (right 261 and right 262 in Fig. 9, paragraph 0074) on the first sacrificial layer 268 (Fig. 9), wherein:
the source/drain electrical connection layer (“conductive material” in paragraph 0095) is formed after the second isolation layer (right 261 and right 262 in Fig. 9) is formed.
Regarding claim 18, Kang further discloses the method according to claim 7, wherein: the first isolation layer (left 161 and left 162 in Fig. 8, paragraph 0036, wherein “SiC, SiN, SiO, SiCN, SiOC, and/or SiOCN”) is made of a material including silicon nitride, silicon oxide, or a combination thereof, and/or depositing the first isolation layer includes atomic layer deposition.
Regarding claim 19, Kang further discloses the method according to claim 6, wherein: the sidewall structure 163 (Fig. 8, paragraph 0036, wherein “SiN”) is made of a material including silicon nitride.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kang as applied to claim 8 above, and further in view of Cheng et al. (US 2019/0312123) (hereafter Cheng123).
Regarding claim 10, Kang in view of Cheng158 discloses the method according to claim 8, however Kang and Cheng158 do not disclose the first sacrificial layer is made of a material including amorphous silicon.
Cheng123 discloses the first sacrificial layer 34 (Fig. 18, paragraph 0059, wherein “amorphous silicon”) is made of a material including amorphous silicon.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang in view of Cheng158 to include the first sacrificial layer is made of a material including amorphous silicon, as taught by Cheng123, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Claims 15-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Cheng158 as applied to claim 6 above, and further in view of Ching et al. (US 2016/0365426) (hereafter Ching).
Regarding claim 15, Kang further discloses the method according to claim 6, wherein a method of forming the gate 165 (Fig. 8), the source/drain region 150 (Fig. 8), and the sidewall structure 163 (Fig. 8) includes: forming a dummy gate 265 (Fig. 9, paragraph 0074) on the substrate (101 and 105 in Fig. 9);
forming a sidewall structure material layer 263 (Fig. 9, paragraph 0074) on a sidewall of the dummy gate 265 (Fig. 9);
forming a source/drain region 150 (Fig. 9, paragraph 0027) in the substrate (101 and 105 in Fig. 9) at two sides of the dummy gate 265 (Fig. 9);
forming a first isolation dielectric layer 172 (Fig. 10A, paragraph 0078) surrounding the dummy gate 265 (Fig. 10A) on the substrate (101 and 105 in Fig. 10A);
removing (see Fig. 12 and paragraph 0084) the dummy gate 265 (Fig. 9) to form a gate opening (OP1 in Fig. 12, paragraph 0084);
depositing an initial gate 165a (Fig. 13, paragraph 0089) within the gate opening (OP1 in Fig. 12); and
planarizing (see Fig. 13 and paragraph 0090, wherein “planarized”) the initial gate 165a (Fig. 13) and the sidewall structure material layer 163 (Fig. 13), to form the gate 165 (Fig. 14, paragraph 0092) and the sidewall structure 163 (Fig. 14) on sidewall surfaces at two sides of the gate 165 (Fig. 14).
Kang and Cheng158 do not disclose forming a sidewall structure material layer on a top surface of the dummy gate; and
forming a first isolation dielectric layer surrounding the source/drain region.
Ching discloses forming a sidewall structure material layer 92 (Fig. 14A, paragraph 0052) on a top surface (see paragraph 0052, wherein “Each of the sub-layers 92, 94, and 96 may be formed by conformally depositing, such as by CVD or the like”) of the dummy gate 48 (Fig. 14A, paragraph 0023); and
forming a first isolation dielectric layer (58 and 60 in Fig. 15A, paragraph 0031) surrounding the source/drain region 56 (Fig. 14A, paragraph 0026).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang in view of Cheng158 to include forming a sidewall structure material layer on a top surface of the dummy gate; and forming a first isolation dielectric layer surrounding the source/drain region, as taught by Ching, since parasitic capacitance (Ching, paragraph 0056) between the gate electrode 66 and the lower contacts 70 (Ching, Fig. 21A, paragraph 0056) can be reduced such that these advantages (Ching, paragraph 0056) may be advantageous for reduced technology nodes, such as 10 nm and below.
Regarding claim 16, Kang further discloses the method according to claim 15, wherein a method of forming the source/drain electrical connection layer 180 (Fig. 8) includes: forming a source/drain via (OP2 in Fig. 15, paragraph 0094) in the first isolation dielectric layer 176 (Fig. 15); and forming the source/drain electrical connection layer (“conductive material” in paragraph 0095) in the source/drain via (OP2 in Fig. 15).
Regarding claim 17, Kang further discloses the method according to claim 16, after forming the first isolation dielectric layer 172 (Fig. 10A, paragraph 0078) and before forming the source/drain via (OP2 in Fig. 15), further comprising: forming a first etch stop layer 176 (Fig. 14, paragraph 0023) on the first isolation dielectric layer 172 (Fig. 14);
and forming a second isolation dielectric layer 178 (Fig. 15, paragraph 0023) on the first etch stop layer 176 (Fig. 15), wherein: the source/drain via (OP2 in Fig. 15) is also located in the second isolation dielectric layer 178 (Fig. 15).
Regarding claim 20, Kang in view of Cheng158 discloses the method according to claim 6, however Kang and Cheng158 do not disclose after forming the cavity, further comprising: forming a second etch stop layer on a top of the isolation structure, wherein the second etch stop layer enclosing the cavity; and forming an electrical interconnection layer on the gate and on the source/drain electrical connection layer.
Ching discloses after forming the cavity 100 (Fig. 20A, paragraph 0054), further comprising: forming a second etch stop layer 98 (Fig. 20A, paragraph 0055) on a top (see paragraph 0055, wherein “the deposition may be substantially conformal and form gaps or voids”) of the isolation structure (92, 100, and 96 in Fig. 20A), wherein the second etch stop layer 98 (Fig. 20A) enclosing the cavity 100 (Fig. 20A); and forming an electrical interconnection layer (82 and 84 in Figs. 21A and 21B, paragraph 0045) on the gate 66 (Fig. 21B) and on the source/drain electrical connection layer 70 (Fig. 21A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kang in view of Cheng158 to form after forming the cavity, further comprising: forming a second etch stop layer on a top of the isolation structure, wherein the second etch stop layer enclosing the cavity; and forming an electrical interconnection layer on the gate and on the source/drain electrical connection layer, as taught by Ching, since respective gaps or voids 100 (Ching, Fig. 20A, paragraph 0055) can therefore be formed below the dielectric material of the second sub-layers 98 (Ching, Fig. 20A, paragraph 0055) and between the first sub-layer 92 (Ching, Fig. 20A, paragraph 0055) and the third sub-layer 96 (Ching, Fig. 20A, paragraph 0055) such that having a gap or void (Ching, paragraph 0056) formed in the gate spacer, the dielectric constant (k) can be further reduced, thereby reducing parasitic capacitance even further.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (US 2021/0193506) (hereafter Liang), in view of Cheng et al. (US 9716158 B1) (hereafter Cheng158).
Regarding claim 1, Liang discloses a semiconductor structure, comprising:
a substrate 221 (Fig. 6, paragraph 0032);
a gate 216 (Fig. 6, paragraph 0032) on the substrate 221 (Fig. 6);
a sidewall structure 210 (Fig. 6, paragraph 0036) on sidewalls at two sides of the gate 216 (Fig. 6);
a source/drain region 240 (Fig. 6, paragraph 0037) in the substrate 221 (Fig. 6) at two sides of the gate 216 (Fig. 6) and the sidewall structure 210 (Fig. 6);
a source/drain electrical connection layer (214 and 230 in Fig. 6, paragraph 0038) on the source/drain region 240 (Fig. 6); and
an isolation structure (532 and 542 in Fig. 6, paragraph 0060) between the source/drain electrical connection layer (214 and 230 in Fig. 6) and the gate 216 (Fig. 6), wherein
the isolation structure (532 and 542 in Fig. 6) includes a cavity 542 (Fig. 6, paragraph 0060) and a first isolation layer 532 (Fig. 6, paragraph 0060),
the cavity 542 (Fig. 6) includes a first cavity region (lower region of 542 in Fig. 6) and a second cavity region (upper region of 542 in Fig. 6) located on the first cavity region (lower region of 542 in Fig. 6),
the second cavity region (opening between 432B in Fig. 4C) includes sidewalls formed by the first isolation layer 432B (Fig. 4C, paragraph 0052), and the first isolation layer 432B (Fig. 4C) is above the first cavity region (opening between 432B in Fig. 4C), such that a width of the second cavity region (opening between 432B in Fig. 4C) is smaller than a width of the first cavity region (opening between 210 and 214 in Fig. 4C).
Liang does not disclose a top surface of the second cavity region is higher than a top surface of the gate, and the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer.
Cheng158 discloses a top surface of the second cavity region (upper region of 40 in Fig. 8A, second paragraph in Col. 10) is higher than a top surface of the gate 27 (Fig. 8A), and the top surface of the second cavity region (upper region of 40 in Fig. 8A, second paragraph in Col. 10) is coplanar with a top surface of the source/drain electrical connection layer (element number is not shown in Fig. 8A but see 38 in Fig. 7A, second paragraph in Col. 10).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Liang to form a top surface of the second cavity region is higher than a top surface of the gate, and the top surface of the second cavity region is coplanar with a top surface of the source/drain electrical connection layer, as taught by Cheng158, since the gaps 40 (Cheng158, Fig. 8A, second paragraph in Col. 10) remain unfilled during subsequent processing steps to reduce parasitic capacitance between the gate stacks and the metal source/drain contacts 38 (Cheng158, Fig. 7A, second paragraph in Col. 10) of the resulting structure.
Regarding claim 5, Liang further discloses the semiconductor structure according to claim 1, wherein: the source/drain region 240 (Fig. 6) is located in the substrate 221 (Fig. 6) at a side of the sidewall structure 210 (Fig. 6) away from the gate 216 (Fig. 6), and
the sidewall structure 210 (Fig. 6) includes an L-shape, and a portion of the sidewall structure 210 (Fig. 6) provides a bottom of the cavity 542 (Fig. 6).
Allowable Subject Matter
1. Claims 9 and 11-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 9 would be allowable because a closest prior art, Kang et al. (US 2021/0098592), discloses the cavity (left 169 in Fig. 8) includes a first cavity region (lower region of left 169 in Fig. 8) and a second cavity region (upper region of left 169 in Fig. 8) located on the first cavity region (lower region of left 169 in Fig. 8), and the second cavity region (upper region of left 169 in Fig. 8) includes sidewalls formed by the first isolation layer (left 161 and left 162 in Fig. 8) and the first isolation layer (left 161 and left 162 in Fig. 8) is formed above the first cavity region (lower region of left 169 in Fig. 8), such that a width of the second cavity region (upper region of left 169 in Fig. 8) is smaller than a width of the first cavity region width (lower region of left 169 in Fig. 8); a second isolation layer 163 (Fig. 8, paragraph 0030) located on a sidewall of the source/drain electrical connection layer 180 (Fig. 8); forming a first sacrificial layer 268 (Fig. 9, paragraph 0064) on the sidewall structure 263 (Fig. 9, paragraph 0074); and forming the second isolation layer (right 261 and right 262 in Fig. 9, paragraph 0074) on the first sacrificial layer 268 (Fig. 9), wherein: the source/drain electrical connection layer (“conductive material” in paragraph 0095) is formed after the second isolation layer (right 261 and right 262 in Fig. 9) is formed but fails to disclose after forming the source/drain electrical connection layer, etching back the first sacrificial layer to form a second sacrificial layer and an initial cavity groove; depositing the first isolation layer on a sidewall of the initial cavity groove, and forming the second cavity region between the first isolation layers; and after forming the first isolation layer, removing the second sacrificial layer to form the first cavity region. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method of forming a semiconductor structure, comprising: after forming the source/drain electrical connection layer, etching back the first sacrificial layer to form a second sacrificial layer and an initial cavity groove; depositing the first isolation layer on a sidewall of the initial cavity groove, and forming the second cavity region between the first isolation layers; and after forming the first isolation layer, removing the second sacrificial layer to form the first cavity region in combination with other elements of the base claims 8, 7, and 6. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claims 11-12 depend on claim 9.
Furthermore, claim 13 would be allowable because a closest prior art, Kang et al. (US 2021/0098592), discloses forming a source/drain electrical connection layer 180 (Fig. 8, paragraph 0023) on the source/drain region 150 (Fig. 8); forming an isolation structure (161, 169, and 162 in Fig. 8, paragraph 0034) located between the gate 165 (Fig. 8) and the source/drain electrical connection layer 180 (Fig. 8); and a second isolation layer (right 161 and right 162 in Fig. 8, paragraph 0030) located on a sidewall of the source/drain electrical connection layer 180 (Fig. 8) but fails to disclose forming the isolation structure further includes: after forming the source/drain electrical connection layer, removing the first sacrificial layer to form a cavity groove; depositing an initial second sacrificial layer in the cavity groove; etching back the initial second sacrificial layer to form a second sacrificial layer, wherein a surface of the second sacrificial layer is lower than a surface of the first sacrificial layer; depositing the second isolation layer on a sidewall surface of the cavity groove, and forming the second cavity region between the second isolation layers; and after depositing the second isolation layer, removing the second sacrificial layer to form the first cavity region. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a method of forming a semiconductor structure, comprising: forming the isolation structure further includes: after forming the source/drain electrical connection layer, removing the first sacrificial layer to form a cavity groove; depositing an initial second sacrificial layer in the cavity groove; etching back the initial second sacrificial layer to form a second sacrificial layer, wherein a surface of the second sacrificial layer is lower than a surface of the first sacrificial layer; depositing the second isolation layer on a sidewall surface of the cavity groove, and forming the second cavity region between the second isolation layers; and after depositing the second isolation layer, removing the second sacrificial layer to form the first cavity region in combination with other elements of the base claims 8, 7, and 6. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claim 14 depends on claim 13.
Response to Arguments
1. Applicant's arguments filed 12/22/2025 have been fully considered.
2. The applicant argues (REMARKS, first paragraph in page 14) that “As such, Kang at least fails to disclose: the cavity includes a first cavity region and a second cavity region located on the first cavity region, the second cavity region includes sidewalls formed by the first isolation layer and the first isolation layer is above the first cavity region, such that a width of the second cavity region is smaller than a width of the first cavity region, as claimed. Kang thus does not anticipate the claimed invention. The amended claims 1, and 6, and their dependent claims are patentable over Kang under 35 U.S.C. 102.” However, Kang et al. (US 2021/0098592) disclose the cavity 169 (Fig. 8) includes a first cavity region (lower region of 169 in Fig. 8) and a second cavity region (upper region of 169 in Fig. 8) located on the first cavity region (lower region of 169 in Fig. 8), the second cavity region (upper region of 169 in Fig. 8) includes sidewalls formed by the first isolation layer (161 and 162 in Fig. 8), and the first isolation layer (161 and 162 in Fig. 8) is above the first cavity region (lower region of 169 in Fig. 8), such that a width of the second cavity region (upper region of 169 in Fig. 8) is smaller than a width of the first cavity region (lower region of 169 in Fig. 8).
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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