DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the application filed on 4/27/23. Claims 1-20 are pending.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sarkar et al. (US PGPub 2019/0371719, hereinafter referred to as “Sarkar”).
Sarkar discloses the semiconductor method as claimed. See figures 1A-13 and corresponding text, where Sarkar teaches, in claim 1, a semiconductor die, comprising:
a substrate (902) having a device side and a backside (figure 10; [0050-0051]);
an active device layer in or on the device side of the substrate (902) (figure 10; [0050-0051]);
a dielectric structure (912) over the active device layer;
a first die-edge metal guard ring (914) in the dielectric structure (912) and around an outer perimeter of the substrate (902);
a plurality of metallization layers (908) in the dielectric structure (912) and within the first die-edge metal guard ring (914);
a plurality of through silicon vias in the substrate that extend into the dielectric structure and are connected to the plurality of metallization layers ([0050]);
a plurality of backside metallization structures beneath the backside of the substrate (902), wherein the plurality of through silicon vias are connected to the plurality of backside metallization structures ([0053]); and
a second die-edge metal guard ring (916) laterally around the plurality of backside metallization structures.
Sarkar teaches, in claim 2, wherein the first die-edge metal guard ring is a first square or rectangular frame, and the second die-edge metal guard ring is a second square or rectangular frame (figure 10; [0052-0053]).
Sarkar teaches, in claim 3, wherein the first die-edge metal guard ring and the second die-edge metal guard ring each comprise multiple layers of alternating metal lines and vias (figure 10; [0050-0051]).
Sarkar teaches, in claim 4, wherein the substrate is vertically intervening between the first die-edge metal guard ring and the second die-edge metal guard ring (figure 10; [0050-0051]).
Sarkar teaches, in claim 5, further comprising:
a second plurality of through silicon vias coupling the first die-edge metal guard ring to the second die-edge metal guard ring (figure 10; [0050-0051]).
Sarkar teaches, in claim 6, a semiconductor die, comprising:
a substrate (902);
a mid-level metallization layer (908) above the substrate (902) (figure 10; [0050-0052]);
a higher metallization layer ([0053]) above the mid-level metallization layer (908) (figures 9 and 10; [0050-0053]);
a through silicon via (TSV) (914) that extends from a location within the substrate to the mid-level metallization layer (908) (figures 9 and 10; [0050-0055]); and
a TSV etch ring that surrounds the TSV (916) (figures 9 and 10; [0050-0053])
Sarkar teaches, in claim 7, further comprising:
upper metallization layers that couple the TSV to the higher metallization layer (figures 9 and 10; [0050-0055]).
Sarkar teaches, in claim 8, wherein the TSV etch ring is a square or rectangular frame (figure 6; [0047]).
Sarkar teaches, in claim 9, wherein the TSV is the only TSV surrounded by the TSV etch ring (figure 6; [0047]).
Sarkar teaches, in claim 10, wherein the TSV etch ring surrounds one or more additional TSVs (figure 6; [0047]).
Sarkar teaches, in claim 11, a computing device, comprising:
a board(figure 11; [0055]); and
a component coupled to the board (figure 11; [0055]), the component including a semiconductor die, the semiconductor die comprising:
a substrate (902) having a device side and a backside;
an active device layer in or on the device side of the substrate;
a dielectric structure (912) over the active device layer;
a first die-edge metal guard ring (914) in the dielectric structure and around an outer perimeter of the substrate;
a plurality of metallization layers (908) in the dielectric structure (912) and within the first die-edge metal guard ring (914);
a plurality of through silicon vias in the substrate that extend into the dielectric structure (912) and are connected to the plurality of metallization layers (908);
a plurality of backside metallization structures beneath the backside of the substrate, wherein the plurality of through silicon vias are connected to the plurality of backside metallization structures; and
a second die-edge metal guard ring (916) laterally around the plurality of backside metallization structures (figures 9 and 10; [0050-0053]; figure 11; [0055]).
Sarkar teaches, in claim 12, further comprising:
a memory coupled to the board (figure 11; [0055]).
Sarkar teaches, in claim 13, further comprising:
a communication chip coupled to the board (figure 11; [0055]).
Sarkar teaches, in claim 14, further comprising:
a camera coupled to the board (figure 11; [0055]).
Sarkar teaches, in claim 15, wherein the component is a packaged integrated circuit die (figure 11; [0055]).
Sarkar teaches, in claim 16, a computing device, comprising:
a board (figure 11; [0055]); and
a component coupled to the board, the component including a semiconductor die (figure 11; [0055]), the semiconductor die comprising:
a substrate (902);
a mid-level metallization layer (908) above the substrate (902);
a higher metallization layer above the mid-level metallization layer;
a through silicon via (TSV) (914) that extends from a location within the substrate to the mid-level metallization layer; and
a TSV etch ring (916) that surrounds the TSV (figures 9 and 10; [0050-0053]; figure 11; [0055]).
Sarkar teaches, in claim 17, further comprising:
a memory coupled to the board (figure 11; [0055]).
Sarkar teaches, in claim 18, further comprising:
a communication chip coupled to the board ([0069]).
Sarkar teaches, in claim 19, further comprising:
a camera coupled to the board ([0069]).
Sarkar teaches, in claim 20, wherein the component is a packaged integrated circuit die ([0069]).
Conclusion
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/STANETTA D ISAAC/Examiner, Art Unit 2898 June 13, 2026
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