DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Response to Arguments
5. Applicant’s arguments, see Rejection under 35 U.S.C. § 102, filed 11/26/2025, with respect to the rejection(s) of claims 1 and 16 under 35 USC § 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kawamura, Keisuke et al. (Pub No. US 20250006799 A1) (hereinafter, Kawamura).
6. Applicant’s arguments, see Rejection under 35 U.S.C. § 103, filed 11/26/2025, with respect to the rejection(s) of claim 12 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kawamura, Keisuke et al. (Pub No. US 20250006799 A1) (hereinafter, Kawamura) in view of Lin, Jiann-Horng (Pub No. US 20200020532 A1) (hereinafter, Lin).
7. Applicant’s arguments with respect to claims 5, 7-9, 12-15, 17 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
For above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
9. Claims 1-6, 9, 11, 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kawamura, Keisuke et al. (Pub No. US 20250006799 A1) (hereinafter, Kawamura).
Kawamura, Fig 4: Multilayered structure including amorphous layers over diamond substrate
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Re Claim 1, (Currently Amended) Kawamura teaches a method of reducing process and final deformation of a gallium nitride (GaN) semiconductor device, the method comprising:
forming at least one multi-layered structure (Amorphous layers; 3a/3b; Fig 4; ¶[0115]) on at least one surface (Upper surface of diamond substrate 1; Fig 4) of a semiconductor substrate (Diamond substrate; 1; Fig 4; ¶[0113]); and
depositing a gallium nitride (GaN) semiconductor layer (Nitride semiconductor layer; 4; Fig 4; ¶[0096]; Note: Per ¶[0096] may be AlGaN or GaN layer) on the semiconductor substrate;
wherein the at least one multi-layered structure is formed by applying a first amorphous layer (Amorphous layer; 3b/3d; Figs 4/10; ¶[0115]) on the at least one surface of the semiconductor substrate, the first amorphous layer having a first thermal expansion coefficient (Thermal expansion coefficient of SiC, i.e. 2.3 to 4.5 x 10^-6 /K; ¶[0115]),
and applying a second amorphous layer (Amorphous layer; 3a/3c; Figs 4/10; ¶[0115]) on the first amorphous layer, the second amorphous layer having a second thermal expansion coefficient (Thermal expansion coefficient of SiO2, i.e. 0.55 x 10^-6 /K; ¶[0128]), different from the first thermal expansion coefficient.
prior to applying the first amorphous layer and second amorphous layer, calculating a deposition thickness (Greater than 0 to less than or equal to 5 nm; ¶[0113]) and/or deposition temperature for the first amorphous layer and second amorphous layer,
However, Kawamura does not teach prior to applying a first amorphous layer and second amorphous layer, calculating a deposition thickness and/or deposition temperature for the first amorphous layer and second amorphous layer, based on a predetermined desired thickness of the gallium nitride (GaN) semiconductor layer.
However, Claim 1 recites the functional limitation wherein “prior to applying a first amorphous layer and second amorphous layer, calculating a deposition thickness and/or deposition temperature for the first amorphous layer and second amorphous layer, based on a predetermined desired thickness of the gallium nitride (GaN) semiconductor layer,” which is not specifically disclosed in Kawamura.
But, “a claim containing a ‘recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus' if the prior art apparatus teaches all the structural limitations of the claim.” MPEP § 2114 (quoting Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)). Moreover, “If an examiner concludes that a functional limitation is an inherent characteristic of the prior art, then to establish a prima case of anticipation or obviousness, the examiner should explain that the prior art structure inherently possesses the functionally defined limitations of the claimed apparatus.” MPEP § 2114 (citing In re Schreiber, 128 F.3d 1473, 1478 (Fed. Cir. 1997)). “The burden then shifts to applicant to establish that the prior art does not possess the characteristic relied on.” MPEP § 2114 (citing In re Schrieber, 128 F.3d at 1478).
In the instant case, the semiconductor device disclosed in Kawamura discloses all of the structural limitations of the presently rejected claim 1, noted in the above rejection of independent claim 1. Moreover, the amorphous layers disclosed in Kawamura inherently possess the functionally defined limitations of Applicant' s claimed device for at least the following reasons:
(1) Disclosed in FIG. 4 of Kawamura and in various figures such as, for instance, FIG. 4 of the present application, the first and second amorphous layers 3a/3b of Kawamura have a deposition thickness of greater than 0 and less than or equal to 5 nm (¶[0113]). Also, the GaN semiconductor layer 4 of Kawamura has a disclosed thickness of 0.5 microns to 6 microns.
(2) Both disclosures contemplate the structures performing similar intended functions—support of another structure. See Kawamura [0002]: “Non-patent document 1 below discloses a nitride semiconductor device equipped with an SOI (Silicon On Insulator) substrate and a HEMT (High Electron Mobility Transistor) formed on the Si layer within the SOI substrate.”
Re Claim 2, (Original) Kawamura teaches the method of claim 1, wherein the first thermal expansion coefficient (Thermal expansion coefficient of SiC, i.e. 2.3 to 4.5 x 10^-6 /K) is greater than a thermal expansion coefficient (Thermal expansion coefficient of diamond, i.e. 1.0 × 10-6/K) of the semiconductor substrate (Diamond substrate; 1; Fig 4; ¶[0113]),
and wherein the second thermal expansion coefficient (Thermal expansion coefficient of SiO2, i.e. 0.55 x 10^-6 /K) is less than the thermal expansion coefficient of the semiconductor substrate.
Re Claim 3, (Original) Kawamura teaches the method of claim 1, wherein the semiconductor substrate (Diamond substrate; 1; Fig 4; ¶[0113]) comprises at least one of a silicon-based substrate, a silicon-on-insulator (SOI) substrate, a silicon carbide (SiC) substrate, a silicon-on-sapphire substrate (SOS) substrate, a bonded silicon substrate, or doped or un-doped silicon substrate, a sapphire substrate, a diamond substrate, or a combination thereof (Diamond substrate; 1; Fig 4; ¶[0113]).
Kawamura, Fig 33: Embodiment of GaN semiconductor device
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Re Claim 4, (Original) Kawamura teaches the method of claim 1, wherein the first amorphous layer (Amorphous layer within bonding layer 3; 3b/3d; Figs 4/10/33; ¶[0115]) comprises one or more layers selected from SiN, SiCxO(i-x), SiC, SiNxOi-x), A1203, and Cr2O3, or a combination thereof, wherein 0<x<1 (SiC; ¶[0128]),
and the second amorphous layer (Amorphous layer within bonding layer 3; 3a/3c; Figs 4/10/33; ¶[0115]) comprises one or more layers selected from SiO2, SiCxN(1-x), or a combination thereof, wherein 0<x<1 (SiO2; ¶[0115]).
Re Claim 5, (Original) Kawamura fails to disclose the exact temperature ranges as claimed.
Nevertheless, as depicted in paragraph [0118], the temperature must possess a particular range. The choice of a temperature range of 200 C to 400 C for the SiN layer and 800 C to 1100 C for the SiO2 layer is matter of engineering design choice; therefore, obvious expedient. Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Kawamura's temperature range of 200 C to 400 C for the SiN layer and 800 C to 1100 C for the SiO2 layer, respectively, because this would be the best engineering design choice.
In addition, the selection of particular temperature as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04"
Re Claim 6, (Original) Kawamura teaches the method of claim 1, wherein the at least one multi-layered structure (Amorphous layers; 3a/3b; Fig 4; ¶[0115])) is formed on a bottom side of the semiconductor substrate, or on a top side (Upper side of 1; Fig 4) of a semiconductor substrate (Diamond substrate; 1; Fig 4; ¶[0113]), or a combination thereof.
Re Claim 9, (Original) Kawamura does not teach the method of claim 1, wherein the first amorphous layer and second amorphous layer have a thickness of about 0.1 µm to 30 µm.
However, the ordinary artisan would have recognized the thickness of the first and second amorphous layers to have a range of about 0.1 µm to 30 µm, to be a result effective variable affecting the stress of the surrounding layers. Thus, it would have been obvious to modify the thickness of the first and second amorphous layers within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. (See MPEP 2144.05 II.B)
Re Claim 11, (Original) Kawamura teaches the method of claim 1, wherein the final deformation (Warping; ¶[0229]) of the gallium nitride (GaN) semiconductor device (Semiconductor substrate, i.e. all of stacked layers excluding upper surface electronic components; NS2; Fig 33; ¶[0229]) is less than about 50 µm (Warping of semiconductor substrate NS2 is 0 to 50 µm; Fig 33; ¶[0229]).
Re Claim 16, (Currently Amended) Kawamura teaches a semiconductor device, comprising:
at least one multi-layered structure (Bonding layer/Amorphous layers; 3/3a/3b; Figs 4/33; ¶[0115])) formed on at least one surface a semiconductor substrate;
a buffer layer (Nitride semiconductor layer; 410; Fig 33; ¶[0195]); and
a gallium nitride (GaN) semiconductor layer (C-GaN layers; 421; Fig 33; ¶[0206]);
wherein the at least one multi-layered structure comprises a first amorphous layer (Amorphous layer within bonding layer 3; 3b/3d; Figs 4/10/33; ¶[0115]), the first amorphous layer having a first thermal expansion coefficients (CTE) (Thermal expansion coefficient of SiC, i.e. 2.3 to 4.5 x 10^-6 /K),
and a second amorphous layer (Amorphous layer within bonding layer 3; 3a/3c; Figs 4/10/33; ¶[0115]) formed on the first amorphous layer, the second amorphous layer having a second thermal expansion coefficient (Thermal expansion coefficient of SiO2, i.e. 0.55 x 10^-6 /K), different from the first thermal expansion coefficient.
However, Kawamura does not teach wherein the thickness of the first amorphous layer and second amorphous layer is predetermined based on the thickness of the gallium nitride semiconductor layer.
However, Claim 16 recites the functional limitation wherein “wherein the thickness of the first amorphous layer and second amorphous layer is predetermined based on the thickness of the gallium nitride semiconductor layer,” which is not specifically disclosed in Kawamura.
But, “a claim containing a ‘recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus' if the prior art apparatus teaches all the structural limitations of the claim.” MPEP § 2114 (quoting Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)). Moreover, “If an examiner concludes that a functional limitation is an inherent characteristic of the prior art, then to establish a prima case of anticipation or obviousness, the examiner should explain that the prior art structure inherently possesses the functionally defined limitations of the claimed apparatus.” MPEP § 2114 (citing In re Schreiber, 128 F.3d 1473, 1478 (Fed. Cir. 1997)). “The burden then shifts to applicant to establish that the prior art does not possess the characteristic relied on.” MPEP § 2114 (citing In re Schrieber, 128 F.3d at 1478).
In the instant case, the semiconductor device disclosed in Kawamura discloses all of the structural limitations of the presently rejected claim 1, noted in the above rejection of independent claim 1. Moreover, the amorphous layers disclosed in Kawamura inherently possess the functionally defined limitations of Applicant' s claimed device for at least the following reasons:
(1) Disclosed in FIG. 4 of Kawamura and in various figures such as, for instance, FIG. 4 of the present application, the first and second amorphous layers 3a/3b of Kawamura have a deposition thickness of greater than 0 and less than or equal to 5 nm (¶[0113]). Also, the GaN semiconductor layer 4 of Kawamura has a disclosed thickness of 0.5 microns to 6 microns.
(2) Both disclosures contemplate the structures performing similar intended functions—support of another structure. See Kawamura [0002]: “Non-patent document 1 below discloses a nitride semiconductor device equipped with an SOI (Silicon On Insulator) substrate and a HEMT (High Electron Mobility Transistor) formed on the Si layer within the SOI substrate.”
Re Claim 20, (Original) Kawamura does not teach the semiconductor device of claim 16, wherein the first amorphous layer or second amorphous layer have a thickness of about 0.1 µm to 30 µm.
However, the ordinary artisan would have recognized the thickness of the first and second amorphous layers to have a range of about 0.1 µm to 30 µm, to be a result effective variable affecting the stress of the surrounding layers. Thus, it would have been obvious to modify the thickness of the first and second amorphous layers within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. (See MPEP 2144.05 II.B)
10. Claims 7 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kawamura, Keisuke et al. (Pub No. US 20250006799 A1) (hereinafter, Kawamura) as applied to claim 1 above, and further in view of Lin, Jiann-Horng (Pub No. US 20200020532 A1) (hereinafter, Lin).
Re Claim 7, (Original) Kawamura does not teach the method of claim 1, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate and wherein the at least one multi-layered structure is formed between a silicon base layer and a SiO2 insulator layer of the semiconductor substrate.
In the same field of endeavor, Lin teaches the method of claim 1, wherein the semiconductor substrate (Multiple layer scheme; 199; Fig 2B; ¶[0014]) comprises a silicon-on-insulator (SOI) substrate (Semiconductor-on-insulator (SOI) substrate; 100; Fig 2B; ¶[0011]) and wherein the at least one multi-layered structure (Material layer/hardmask layer; 101/102; Fig 2B; ¶¶[0012,0014]) is formed between a silicon base layer (Semiconductor-on-insulator (SOI) substrate; 100; Fig 2B; ¶[0011]) and a SiO2 insulator layer (Dielectric layer, i.e. silicon oxide; 104; Fig 2B; ¶[0014]) of the semiconductor substrate.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a semiconductor substrate comprising of a silicon-on-insulator (SOI) substrate and wherein the at least one multi-layered structure is formed between a silicon base layer and a SiO2 insulator layer of the semiconductor substrate, as taught by Lin, for the semiconductor device of Kawamura. One would have been motivated to do this with a reasonable expectation of success such that the SiO2 layer may be used as an etching mask during the patterning process, to etch the multi-layer stack below, including the silicon substrate, as suggested by Lin (¶[0036]).
Re Claim 12, (Currently Amended) Kawamura teaches a method of manufacturing a gallium nitride (GaN) semiconductor device, the method comprising:
depositing at least one multi-layered structure (Bonding layer/Amorphous layers; 3/3a/3b; Figs 4/33; ¶[0115]; Note: Bonding layer 3 comprises the two amorphous layers 3a/3b) on a bottom side and/or a topside (Upper surface of diamond substrate 1; Figs 4/33) of a semiconductor substrate (Diamond substrate; 1; Figs 4/33; ¶[0113]);
depositing a buffer layer (First nitride semiconductor layer; 410; Fig 33; ¶[0195]) on a top side (Upper surface of diamond substrate 1; Figs 4/33) of the semiconductor substrate; and
depositing a gallium nitride (GaN) semiconductor layer (C-GaN layer; 420; Fig 33; ¶[0202]) on the buffer layer;
wherein the at least one multi-layered structure comprises a first amorphous layer (Amorphous layer; 3b/3d; Figs 4/10; ¶[0115]) and a second amorphous layer (Amorphous layer; 3a/3c; Figs 4/10; ¶[0115]) , selected from SiN, SiCxO(i-x), SiC, SiNxOi-x), A1203, and Cr203, or a combination thereof, wherein 0<x<1 (SiC; ¶[0128]).
However, Kawamura does not teach a third amorphous layer and fourth amorphous layer selected from SiO2, SiCxN(1-x), or a combination thereof, wherein 0<x<1,
prior to depositing a first amorphous layer and second amorphous layer, calculating a deposition thickness and/or deposition temperature for the first amorphous layer and second amorphous layer, based on a predetermined desired thickness of the gallium nitride (GaN) semiconductor layer.
In the same field of endeavor, Lin teaches a third amorphous layer (Hardmask layer, i.e. may be combination of SiN and SiC or the like; 102; Fig 2B; ¶[0014]; Note: SiCN may be an amorphous material) and fourth amorphous layer (Bottom layer, i.e. Silicon oxide; 114; Fig 2B; ¶[0016]; Note: SiO2 may be an amorphous material) selected from SiO2, SiCxN(1-x), or a combination thereof, wherein 0<x<1.
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a third amorphous layer and fourth amorphous layer selected from SiO2, SiCxN(1-x), the materials of which may be amorphous, or a combination thereof, wherein 0<x<1, as taught by Lin, for the semiconductor device of Kawamura. One would have been motivated to do this with a reasonable expectation of success because additional amorphous layers would facilitate the features and structures within the semiconductor device without early deformation or collapse, as suggested by Lin (¶[0039]).
However, Kawamura in view of Lin does not teach prior to depositing a first amorphous layer and second amorphous layer, calculating a deposition thickness and/or deposition temperature for the first amorphous layer and second amorphous layer, based on a predetermined desired thickness of the gallium nitride (GaN) semiconductor layer.
However, Claim 12 recites the functional limitation wherein “prior to depositing a first amorphous layer and second amorphous layer, calculating a deposition thickness and/or deposition temperature for the first amorphous layer and second amorphous layer, based on a predetermined desired thickness of the gallium nitride (GaN) semiconductor layer,” which is not specifically disclosed in Kawamura in view of Lin.
But, “a claim containing a ‘recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus' if the prior art apparatus teaches all the structural limitations of the claim.” MPEP § 2114 (quoting Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)). Moreover, “If an examiner concludes that a functional limitation is an inherent characteristic of the prior art, then to establish a prima case of anticipation or obviousness, the examiner should explain that the prior art structure inherently possesses the functionally defined limitations of the claimed apparatus.” MPEP § 2114 (citing In re Schreiber, 128 F.3d 1473, 1478 (Fed. Cir. 1997)). “The burden then shifts to applicant to establish that the prior art does not possess the characteristic relied on.” MPEP § 2114 (citing In re Schrieber, 128 F.3d at 1478).
In the instant case, the semiconductor device disclosed in Kawamura discloses all of the structural limitations of the presently rejected claim 1, noted in the above rejection of independent claim 1. Moreover, the amorphous layers disclosed in Kawamura inherently possess the functionally defined limitations of Applicant' s claimed device for at least the following reasons:
(1) Disclosed in FIG. 4 of Kawamura and in various figures such as, for instance, FIG. 4 of the present application, the first and second amorphous layers 3a/3b of Kawamura have a deposition thickness of greater than 0 and less than or equal to 5 nm (¶[0113]). Also, the GaN semiconductor layer 4 of Kawamura has a disclosed thickness of 0.5 microns to 6 microns.
(2) Both disclosures contemplate the structures performing similar intended functions—support of another structure. See Kawamura [0002]: “Non-patent document 1 below discloses a nitride semiconductor device equipped with an SOI (Silicon On Insulator) substrate and a HEMT (High Electron Mobility Transistor) formed on the Si layer within the SOI substrate.”
Re Claim 13, (Original) Kawamura fails to disclose the exact temperature ranges as claimed.
Nevertheless, as depicted in paragraph [0118], the temperature must possess a particular range. The choice of a temperature range of 200 C to 400 C for the SiN layer and 800 C to 1100 C for the SiO2 layer is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Kawamura's temperature range of 200 C to 400 C for the SiN layer and 800 C to 1100 C for the SiO2 layer, respectively, because this would be the best engineering design choice.
In addition, the selection of particular temperature as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04"
Re Claim 14, (Original) Kawamura teaches the method of claim 12, wherein the gallium nitride (GaN) layer (C-GaN layers; 421; Fig 33; ¶[0206]) is deposited at a thickness of about 1 µm - 100 µm (Per ¶[0206] preferably each layer 421 has thickness of 0.8 to 2.5 µm).
11. Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kawamura, Keisuke et al. (Pub No. US 20250006799 A1) (hereinafter, Kawamura) as applied to claims 1 and 16 above, and further in view of Yamada, Atsushi (Pub No. JP 2012044115 A) (hereinafter, Yamada).
Re Claim 8, (Original) Kawamura teaches the method of claim 1, wherein forming at least one multi-layered structure (Amorphous layers; 3a/3b; Fig 4; ¶[0115]) comprises: forming a second multi-layered structure (Amorphous layers; 3a/3b; Fig 4; ¶[0115]) on a top side (Upper side of 1; Figs 4/33) of the semiconductor substrate (Diamond substrate; 1; Fig 4; ¶[0113]),
wherein the second multi-layered structure is between an insulator layer or silicon top layer (Support substrate; 95; Fig 4; ¶[0108]) and a base layer (Diamond substrate; 1; Fig 4; ¶[0113]) of the semiconductor substrate.
However, Kawamura does not teach forming a first multi-layered structure on a bottom side of the semiconductor substrate.
In the same field of endeavor, Yamada teaches forming a first multi-layered structure (SiC layer/SiGe layer; 20/50; Fig 18; ¶¶[0019,0033]) on a bottom side (Beneath substrate 1; Fig 18) of the semiconductor substrate (Semiconductor substrate; 1; Fig 18; ¶[0019]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a multi-layered structure on the bottom side of the semiconductor substrate, as taught by Yamada, for the semiconductor device of Kawamura. One would have been motivated to do this with a reasonable expectation of success because when the direction of stress generated in the upper multi-layer structure and bottom multi-layer structure is balanced on opposite sides of the substrate, warpage of the substrate is suppressed, as suggested by Yamada (¶[0035]).
Re Claim 17, (Original) Kawamura teaches the semiconductor device of claim 16, wherein the at least one multi- layered structure (Amorphous layers; 3a/3b; Fig 4; ¶[0115])) comprises a second multi-layered structure (Amorphous layers; 3a/3b; Fig 4; ¶[0115]) on a top side (Upper side of 1; Fig 4) of the semiconductor substrate (Diamond substrate; 1; Fig 4; ¶[0113]).
However, Kawamura does not teach a first multi-layered structure on a bottom side of the semiconductor substrate.
In the same field of endeavor, Yamada teaches a first multi-layered structure (SiC layer/SiGe layer; 20/50; Fig 18; ¶¶[0019,0033]) on a bottom side (Beneath substrate 1; Fig 18) of the semiconductor substrate (Semiconductor substrate; 1; Fig 18; ¶[0019]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a multi-layered structure on the bottom side of the semiconductor substrate, as taught by Yamada, for the semiconductor device of Kawamura. One would have been motivated to do this with a reasonable expectation of success because when the direction of stress generated in the upper multi-layer structure and bottom multi-layer structure is balanced on opposite sides of the substrate, warpage of the substrate is suppressed, as suggested by Yamada (¶[0035]).
12. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kawamura, Keisuke et al. (Pub No. US 20250006799 A1) (hereinafter, Kawamura) in view of Lin, Jiann-Horng (Pub No. US 20200020532 A1) (hereinafter, Lin) as applied to claim 12 above, and further in view of Yamada, Atsushi (Pub No. JP 2012044115 A) (hereinafter, Yamada).
Re Claim 15, (Original) Kawamura teaches the method of claim 12, wherein a second multi-layered structure (Amorphous layers; 3a/3b; Fig 4; ¶[0115]) is deposited on a top side (Upper side of 1; Fig 4) of the semiconductor substrate (Diamond substrate; 1; Fig 4; ¶[0113]).
However, Kawamura in view of Lin does not teach a first multi-layered structure is deposited on a bottom side of the semiconductor substrate.
In the same field of endeavor, Yamada teaches a first multi-layered structure (SiC layer/SiGe layer; 20/50; Fig 18; ¶¶[0019,0033]) is deposited on a bottom side (Beneath substrate 1; Fig 18) of the semiconductor substrate (Semiconductor substrate; 1; Fig 18; ¶[0019]).
Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a multi-layered structure on the bottom side of the semiconductor substrate, as taught by Yamada, for the semiconductor device of Kawamura in view of Lin. One would have been motivated to do this with a reasonable expectation of success because when the direction of stress generated in the upper multi-layer structure and bottom multi-layer structure is balanced on opposite sides of the substrate, warpage of the substrate is suppressed, as suggested by Yamada (¶[0035]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Coursey, Belford T. et al. (Pub No. US20140183443A1) teaches engineered substrates having epitaxial formation structures with enhanced shear strength and associated systems by forming a shear strength enhancement material at a front surface of a donor substrate and implanting ions a depth into the donor substrate through the shear strength enhancement material.
[2] Ramdani, Jamal (Pub No. US20140295651A1) teaches forming a stress compensation layer over a first side of a semiconductor substrate and forming a Group III-nitride layer over a second side of the substrate. Stress created on the substrate by the Group III-nitride layer is at least partially reduced by stress created on the substrate by the stress compensation layer. Forming the stress compensation layer could include forming a stress compensation layer from amorphous or microcrystalline material. Also, the method could include crystallizing the amorphous or microcrystalline material during subsequent formation of one or more layers over the second side of the substrate. Crystallizing the amorphous or microcrystalline material could occur during subsequent formation of the Group III-nitride layer and/or during an annealing process.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817