Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Non-Final office is a response to the papers filed on 04/27/2023.
Claims 1-20 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amaru et al. (Pub. No. 20200074019 A1).
Regarding claim 1, Amaru discloses:
A method comprising:
selecting a gate in a mapped network (see par [0016], selecting a first node and a second node from the sorted list of nodes, determining a first sub-network and a second sub-network corresponding to the first node and the second node [wherein first sub-network and second sub-network obtain gate], see Fig. 7B);
un-mapping the gate into a current Boolean expression (see par [0016-0017], responsive to determining that the first sub-network and the second sub-network are good candidates for performing Boolean difference based resubstitution optimization, computing an optimized sub-network based on the first sub-network and the second sub-network by using Boolean difference based resubstitution optimization….[which is un-mapping the gate into Boolean expression]);
generating a don't-care set for the gate that includes a plurality of don't-care terms where an input sequence for a target gate does not affect an output functionality of another gate in the mapped network (see par [0005], the logic network is optimized by making use of local transformations obtained by considering Boolean algebra and local don't cares. Due to observability and controllability don't cares, often the function at a node n in the logic network can be replaced with another function without changing the behavior at the primary outputs…..,see Fig. 7B) ;
performing, by a processing device, resubstitution using the don't care set to generate a new Boolean expression for the gate (see par [009], A generalization to resubstitution is given by a k-resubstitution, which adds k new nodes to the logic network,…., see par [0016-0018] and par [0083-0085], see Fig. 7B); and
responsive to determining that the new Boolean expression is functionally equivalent to the current Boolean expression, re-mapping the gate into a mapped gate based on the new Boolean expression (see par [0069-0071], A new resubstitution framework based on Boolean difference is now described….., it indicates whether the two functions are functionally equivalent…., see par [0083-0085], see Fig. 7B, step 762).
Regarding claim 11, Amaru discloses:
A system (see Fig. 8), comprising:
a processor (see Fig. 8, processor 804); and
a memory containing a program which when executed by the processor performs an operation comprising (see Fig. 8, memory 808):
selecting a gate in a mapped network (see par [0016], selecting a first node and a second node from the sorted list of nodes, determining a first sub-network and a second sub-network corresponding to the first node and the second node [wherein first sub-network and second sub-network obtain gate], see Fig. 7B);
un-mapping the gate into a current Boolean expression (see par [0016-0017], responsive to determining that the first sub-network and the second sub-network are good candidates for performing Boolean difference based resubstitution optimization, computing an optimized sub-network based on the first sub-network and the second sub-network by using Boolean difference based resubstitution optimization….[which is un-mapping the gate into Boolean expression], see par [0005], transformation…);
identifying a divisor within a window associated with the gate (see par [0066], Detecting all reconvergent maximum fanout free cone MFFC is a special case scenario.….[wherein a node n is substiruted or removed is advisor], see par [0005],…, see par [0017], [0084], and par [0102], [wherein replacing the first sub-network and the second sub-network by the optimized sub-network reduces the size metric of the logic network is using divisor]);
performing resubstitution to generate a new Boolean expression for the gate using the divisor (see par [009], A generalization to resubstitution is given by a k-resubstitution, which adds k new nodes to the logic network,…., see par [0016-0018] and par [0083-0085], see Fig. 7B); and
responsive to determining that the new Boolean expression is functionally equivalent to the current Boolean expression, re-mapping the gate into a mapped gate based on the new Boolean expression (see par [0069-0071], A new resubstitution framework based on Boolean difference is now described….., it indicates whether the two functions are functionally equivalent…., see par [0083-0085], see Fig. 7B, step 762).
Regarding claim 15, Amaru discloses:
A non-transitory computer-readable storage medium having computer- readable program code embodied therewith, the computer-readable program code executable by a processor to perform an operation comprising (see Fig. 8, processor 804, memory 808):
(i) selecting a gate in a mapped network (see par [0016], selecting a first node and a second node from the sorted list of nodes, determining a first sub-network and a second sub-network corresponding to the first node and the second node [wherein first sub-network and second sub-network obtain gate], see Fig. 7B);
(ii) un-mapping the gate into a current Boolean expression (see par [0016-0017], responsive to determining that the first sub-network and the second sub-network are good candidates for performing Boolean difference based resubstitution optimization, computing an optimized sub-network based on the first sub-network and the second sub-network by using Boolean difference based resubstitution optimization….[which is un-mapping the gate into Boolean expression], see par [0005], transformation…);
(iii) performing resubstitution for the gate to generate a new Boolean expression for the gate (see par [009], A generalization to resubstitution is given by a k-resubstitution, which adds k new nodes to the logic network,…., see par [0016-0018] and par [0083-0085], see Fig. 7B);; and
(iv) responsive to determining that the new Boolean expression is functionally equivalent to the current Boolean expression, re-mapping the gate into a mapped gate based on the new Boolean expression (see par [0069-0071], A new resubstitution framework based on Boolean difference is now described….., it indicates whether the two functions are functionally equivalent…., see par [0083-0085], see Fig. 7B, step 762); and
(v) repeating (i)-(iv) for each gate in the mapped network over multiple iterations until reaching a threshold number of iterations (see par [0016-0018], iteratively performing a set of operations, comprising: selecting a first node and a second node from the sorted list of nodes, determining a first sub-network and a second sub-network …, see par [0083], and [0090-0091]).
Regarding claim 2 and 12, Amaru discloses:
performing resubstitution for each gate in the mapped network to determine whether a resulting new Boolean expression is functionally equivalent to a respective, current Boolean expression (see par [0006-0008], When Boolean methods are applied to small windows of logic, they enable very fast implementation and can be used for fast equivalence checking of two functions…., see par [0048]).
Regarding claim 3, Amaru discloses:
performing resubstitution for each gate in the mapped network over multiple iterations (see par [0016-0018], iteratively performing a set of operations, comprising: selecting a first node and a second node from the sorted list of nodes, determining a first sub-network and a second sub-network …, see par [0083], and [0090-0091]).
Regarding claims 4, 13, and 16, Amaru discloses:
identifying, over the multiple iterations, multiple gates in the mapped network that have new Boolean expressions that are functionally equivalent to current Boolean expressions; re-mapping the multiple gates to mapped nodes responsive to completing the multiple iterations (see Fig. 6b, see par [0016-0018], iteratively performing a set of operations, comprising: selecting a first node and a second node from the sorted list of nodes, determining a first sub-network and a second sub-network …, see par [0083], and [0090-0091]).
Regarding claims 5, 14, and 17, Amaru discloses:
before performing resubstitution: identifying a window for the gate, the window comprising one or more levels of fan in of the gate and one or more levels of fan out for the gate; and identifying, from within the window, divisors to be used when performing resubstitution (see par [0066], Detecting all reconvergent maximum fanout free cone MFFC is a special case scenario.…., see par [0005],…, see par [0017], [0084], and par [0102], [wherein replacing the first sub-network and the second sub-network by the optimized sub-network reduces the size metric of the logic network is using divisor].
Regarding claims 6 and 18, Amaru discloses:
wherein un-mapping the gate comprises un-mapping the gate from a library cell to the current Boolean expression (see par [0108], The term ‘cell’ as used in electronic circuit design signifies a specification of one or more components, for example, a set of transistors that are connected to function as a logic gate. Cells are usually stored in a database, to be accessed by circuit designers and design processes…).
Regarding claim 7, Amaru discloses:
wherein generating the don't-care set comprises: formulating a SAT instance in a Conjunctive-Normal Form (CNF) format (see par [0052], It is fair mentioning that there is some overhead in translating circuit-SAT problems in Conjunctive Normal Form (CNF)…).
Regarding claims 8 and 19, Amaru discloses:
wherein performing resubstitution comprises: performing factored-form (FF) literal costing, wherein the FF literal costing comprises a literal cost of the new Boolean expression re-expressing the gate and the literal cost of a Maximum-Fanout-Free Cone (MFFC) of zero-fan out gates being removed in response to performing resubstitution (see par [0070-0080], and par [0089-0096], moves have an associated cost, which correlates to their runtime complexity. For example, rewriting and low-effort refactoring have unit cost, while MSPF resub has a cost of 3 units…., number of terms or literals…. …. [wherein AIG comprises factored-form literal costing]).
Regarding claim 9, Amaru discloses:
after performing resubstitution, a design of a circuit defined by the mapped network is a hybrid design that comprises both mapped and unmapped nodes (see par [0016-0017], replacing the first sub-network and the second sub-network by the optimized sub-network reduces a size metric of the logic network…., see par [0042-0044], he following sections describe techniques and systems for automatically identifying scenarios….)
Regarding claims 10 and 20, Amaru discloses:
performing, after performing resubstitution, local function simplification on the gate using factored-form (FF) literal costing (see par [0089-0096], moves have an associated cost, which correlates to their runtime complexity. For example, rewriting and low-effort refactoring have unit cost, while MSPF resub has a cost of 3 units…, number of terms or literals…..[wherein AIG comprises factored-form literal costing]).
Conclusion
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/BRIAN NGO/ Primary Examiner, Art Unit 2851