Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claims 1-3 be found allowable, claims 9-11 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Specifically, the content of claims 9-11 appear to be slight rewordings corresponding to the subject matter previously disclosed in claims 1-3 respectively; for example, the term “pre-plated leadframe” introduced in claim 9 is interpreted as a substantial duplicate of the term “substrate” in claim 1.
Claim Rejections - 35 USC § 103
Claim(s) 1-4 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Fontana (PGPub No. 20170040244) in further view of Chen (PGPub No. 20140070395) and Signorini (PGPub No. 20210057367).
Regarding claim 1, Fontana teaches a method, comprising steps performed in the following order: arranging a semiconductor integrated circuit chip on a first surface of a substrate, the substrate comprising electrically conductive lead formations covered by a masking layer at a second surface opposite the first surface (Fig. 10 points to a semiconductor device comprising an integrated circuit (die) 18 (circuit chip), a base member 10 (substrate), “islands” 14’ (electrically conductive lead formations), and an electrically conductive layer 26 (masking layer).); and providing an insulating encapsulation of the semiconductor integrated circuit chip arranged on the first surface of the substrate (Id. points to an electrically insulating package molding compound (PMC) 22 (encapsulation material).).
Fontana fails to teach removing the masking layer that covers at least one of the electrically conductive lead formations between first and second ones of the electrically conductive lead formations covered by the masking layer in order to leave said at least one of the electrically conductive lead formations uncovered by the masking layer; and applying etching to the second surface of the substrate to remove said at least one of the electrically conductive lead formations that was left uncovered by removal of the masking layer in order to control a creepage distance between said first and second ones of the electrically conductive lead formations.
Chen teaches removing the masking layer that covers at least one of the electrically conductive lead formations between first and second ones of the electrically conductive lead formations covered by the masking layer in order to leave said at least one of the electrically conductive lead formations uncovered by the masking layer (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (masking layer) via laser ablating.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Fontana and Chen, such that the masking layer is selectively removed to expose at least one of the electrically conductive lead formations in order to, for example, allow for further processing and development of future electrical connections while still maintaining an adequate level of protection via the masking layer.
Fontana in further view of Chen still fails to teach applying etching to the second surface of the substrate to remove said at least one of the electrically conductive lead formations that was left uncovered by removal of the masking layer in order to control a creepage distance between said first and second ones of the electrically conductive lead formations.
Signorini teaches applying etching to the second surface of the substrate to remove said at least one of the electrically conductive lead formations that was left uncovered by removal of the masking layer in order to control a creepage distance between said first and second ones of the electrically conductive lead formations ([0039] points to a method of processing a copper layer (substrate) by first patterning said layer to form pads (electrically conductive lead formations) and then etching to remove the unwanted copper areas (at least one of the electrically conductive lead formations).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fontana et al. and Signorini, such that at least one of the electrically conductive lead formations is etched and removed from the substrate in order to reduce capacitive coupling, improve thermal management, and/or prevent unintended contacts.
Regarding claim 2, Chen teaches wherein removing the masking layer comprises laser ablating said masking layer from said at least one of the electrically conductive formations at the second surface of the substrate (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (masking layer) via laser ablating.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fontana and Chen, such that the masking layer is selectively removed via laser ablation in order to make use of maskless, non-contact patterning while avoiding the difficulties that would come from wet etching a masking layer comprised of multiple materials.
Regarding claim 3, Fontana teaches wherein the masking layer is a NiPdAu layer ([0027] points to electroplating with electrically conductive material such as Ni, Au, Pd to form an electrically conductive layer 26 (masking layer).).
Regarding claim 4, Fontana teaches wherein the substrate comprises at least one semiconductor integrated circuit chip mounting area at the first surface of the substrate and the electrically conductive lead formations comprise an array of electrically conductive leads around the said semiconductor chip mounting area (Fig. 2 points to a base member 10 (substrate) comprising a die attachment portion 12 (semiconductor integrated circuit chip mounting area) and the lead frame portion 14 (array of electrically conductive leads).), and wherein arranging the semiconductor integrated circuit chip comprises mounting the semiconductor integrated circuit chip to the at least one semiconductor integrated circuit chip mounting area (Fig. 4 and [0019] point to attaching an integrated circuit (die) 18 to the die attachment portion 12 (semiconductor integrated circuit chip mounting area).).
Regarding claim 9, Fontana teaches a method, comprising steps performed in the following order: providing a pre-plated metal leadframe including a die pad and a plurality of electrically conductive lead formations surrounding the die pad, where a back surface of the pre-plated leadframe includes a plating mask layer at lead locations of the plurality of electrically conductive lead formations (Fig. 10 points to a semiconductor device comprising an electrically conductive laminar base member 10 (leadframe), a die attachment portion 12 (die pad), “islands” 14’ (electrically conductive lead formations), and an electrically conductive layer 26 (masking layer).); mounting a semiconductor integrated circuit chip on a front surface of the die pad (Id. points to an integrated circuit (die) 18.); and encapsulating the semiconductor integrated circuit chip and a front surface of the plurality of electrically conductive lead formations with an encapsulating material (Id. points to an electrically insulating package molding compound (PMC) 22 (encapsulation material).).
Fontana fails to teach selectively removing the plating mask layer from the back surface of the pre-plated leadframe at one or more lead locations; applying etching to the back surface of the pre-plated metal leadframe to remove metal material which is not covered by the plating mask layer and thus remove electrically conductive lead formations at the one or more lead locations where the plating mask layer was selectively removed in order to control a creepage distance between said two other lead locations where the plating mask layer was not selectively removed.
Chen teaches selectively removing the plating mask layer from the back surface of the pre-plated leadframe at one or more lead locations. (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (masking layer) via laser ablating.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fontana and Chen, such that the masking layer is selectively removed to expose at least one of the electrically conductive lead formations in order to, for example, allow for further processing and development of future electrical connections while still maintaining an adequate level of protection via the masking layer.
Fontana et al. still fails to teach applying etching to the back surface of the pre-plated metal leadframe to remove metal material which is not covered by the plating mask layer and thus remove electrically conductive lead formations at the one or more lead locations where the plating mask layer was selectively removed in order to control a creepage distance between said two other lead locations where the plating mask layer was not selectively removed.
Signorini teaches applying etching to the back surface of the pre-plated metal leadframe to remove metal material which is not covered by the plating mask layer and thus remove electrically conductive lead formations at the one or more lead locations where the plating mask layer was selectively removed in order to control a creepage distance between said two other lead locations where the plating mask layer was not selectively removed ([0039] point to a method of processing a copper layer (leadframe) by first patterning said layer to form pads (electrically conductive lead formations) and then etching to remove the unwanted copper areas (metal material).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fontana et al. and Signorini, such that at least one of the electrically conductive lead formations is etched and removed from the substrate in order to reduce capacitive coupling, improve thermal management, and/or prevent unintended contacts.
Regarding claim 10, Chen teaches wherein selectively removing comprises performing a laser ablating of the plating mask layer to uncover the one or more lead locations of the pre- plated leadframe (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (masking layer) via laser ablating.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fontana and Chen, such that the masking layer is selectively removed via laser ablation in order to make use of maskless, non-contact patterning while avoiding the difficulties that would come from wet etching a masking layer comprised of multiple materials.
Regarding claim 11, Fontana teaches wherein the plating masking layer is made of a NiPdAu plating ([0027] points to electroplating with electrically conductive material such as Ni, Au, Pd to form an electrically conductive layer 26 (masking layer).).
Response to Arguments
Applicant's arguments filed 12/01/2025 have been fully considered but they are not persuasive. Specifically, Applicant argues that the combined teachings of Fontana (PGPub No. 20170040244) in further view of Chen (PGPub No. 20140070395) and Signorini (PGPub No. 20210057367) fail to teach the limitation “removing the masking layer that covers at least one of the electrically conductive lead formations” as disclosed in claim 1, citing in particular that the laser ablation performed in Chen removes a portion of a metal layer (masking layer) covering a molding and not an electrically conductive formation. Examiner argues that Applicant is providing a piecemeal analysis rather than viewing the references in combination. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Fontana teaches “electrically conductive formations covered by a masking layer” as disclosed in claim 1, while Chen teaches “removing the masking layer”; the combination of Fontana and Chen would thus teach one of ordinary skill in the art the formation of a masking layer covering electrically conductive formations that is then selectively removed to reveal the underlying formation(s). Thus, Applicant’s arguments are considered unpersuasive, and the rejection of claim 1 is upheld.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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