Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claims 1-3 be found allowable, claims 9-11 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Specifically, the content of claims 9-11 appear to be slight rewordings corresponding to the subject matter previously disclosed in claims 1-3 respectively; for example, the term “metal leadframe” introduced in claim 9 is interpreted as a substantial duplicate of the term “substrate” in claim 1, primarily due to the specification using the words interchangeably, e.g., “providing a substrate (a metal leadframe 12A, 12B, for instance)”; see pg. 9, lines 12-13. Additionally, the term “plating mask/masking layer” as used in claims 9-11 is considered to be interchangeable with the term “masking layer” as used in claims 1-3 due to both terms being described as having the same material composition as well as positioning in relation to the metal leadframe/substrate respectively. It should also be noted that the term “plating mask/masking layer” does not actually appear in the specification; at best, the specification describes a “plating” or “plating layer” comprising NiPdAu, which is the same material composition as the “masking layer”.
Claim Rejections - 35 USC § 103
Claim(s) 1-4 and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Camacho (US Patent No. 8604596) in further view of Chen (PGPub No. 20140070395) and Signorini (PGPub No. 20210057367).
Regarding claim 1, Camacho teaches a method, comprising steps performed in the following order: for a substrate having a first surface and a second surface opposite the first surface, wherein the substrate includes electrically conductive lead formations, covering the electrically conductive lead formations at the second surface with a masking layer (Figs. 5-6 point to a lead frame 402 (substrate), lead extensions 406 (electrically conductive lead formations), and exterior pads 210 (masking layer).); arranging a semiconductor integrated circuit chip on the first surface of the substrate; and providing an insulating encapsulation of the semiconductor integrated circuit chip arranged on the first surface of the substrate (Fig. 7 points to an integrated circuit 220 and an encapsulation 102.).
Camacho fails to teach removing from the second surface of the substrate the masking layer that covers at least one of the electrically conductive lead formations located between first and second ones of the electrically conductive lead formations which remain covered by the masking layer in order to leave said at least one of the electrically conductive lead formations uncovered by the masking layer; and applying etching to the second surface of the substrate to remove said at least one of the electrically conductive lead formations that was left uncovered by removal of the masking layer in order to control a creepage distance between said first and second ones of the electrically conductive lead formations.
Chen teaches removing from the second surface of the substrate the masking layer that covers at least one of the electrically conductive lead formations located between first and second ones of the electrically conductive lead formations which remain covered by the masking layer in order to leave said at least one of the electrically conductive lead formations uncovered by the masking layer (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (masking layer) via laser ablating.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Camacho and Chen, such that the masking layer is selectively removed to expose at least one of the electrically conductive lead formations in order to, for example, allow for further processing and development of future electrical connections while still maintaining an adequate level of protection via the masking layer.
Camacho et al. still fails to teach applying etching to the second surface of the substrate to remove said at least one of the electrically conductive lead formations that was left uncovered by removal of the masking layer in order to control a creepage distance between said first and second ones of the electrically conductive lead formations.
Signorini teaches applying etching to the second surface of the substrate to remove said at least one of the electrically conductive lead formations that was left uncovered by removal of the masking layer in order to control a creepage distance between said first and second ones of the electrically conductive lead formations ([0039] points to a method of processing a copper layer (substrate) by first patterning said layer to form pads (electrically conductive lead formations) and then etching to remove the unwanted copper areas (at least one of the electrically conductive lead formations).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Camacho et al. and Signorini, such that at least one of the electrically conductive lead formations is etched and removed from the substrate in order to reduce capacitive coupling, improve thermal management, and/or prevent unintended contacts.
Regarding claim 2, Chen teaches wherein removing the masking layer comprises laser ablating said masking layer from said at least one of the electrically conductive formations at the second surface of the substrate (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (masking layer) via laser ablating.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Camacho et al. and Chen, such that the masking layer is selectively removed via laser ablation in order to make use of maskless, non-contact patterning while avoiding the difficulties that would come from wet etching a masking layer comprised of multiple materials.
Regarding claim 3, Camacho teaches wherein the masking layer is a NiPdAu layer (Col. 6, lines 37-41 and 47-50 point to the exterior pad 210 (masking layer) comprising the same materials as the interior pad 208 and the interior paddle pad 214, that being a nickel palladium gold alloy (NiPdAu).).
Regarding claim 4, Camacho teaches wherein the substrate comprises at least one semiconductor integrated circuit chip mounting area at the first surface of the substrate and the electrically conductive lead formations comprise an array of electrically conductive leads around the said semiconductor chip mounting area, and wherein arranging the semiconductor integrated circuit chip comprises mounting the semiconductor integrated circuit chip to the at least one semiconductor integrated circuit chip mounting area (Fig. 7 points to a paddle extension 404 (integrated circuit chip mounting area), the lead extensions 406 (electrically conductive lead formations), and the integrated circuit 220.).
Regarding claim 9, Camacho teaches a method, comprising steps performed in the following order: for metal leadframe including a die pad and a plurality of electrically conductive lead formations surrounding the die pad, forming a plating mask layer at a back surface of the metal leadframe to cover lead locations of the plurality of electrically conductive lead formations (Figs. 5-6 point to a lead frame 402, lead extensions 406 (electrically conductive lead formations), and exterior pads 210 (plating mask layer).); mounting a semiconductor integrated circuit chip on a front surface of the die pad ; and encapsulating the semiconductor integrated circuit chip and a front surface of the plurality of electrically conductive lead formations with an encapsulating material (Fig. 7 points to an integrated circuit 220 and an encapsulation 102.).
Camacho fails to teach selectively removing the plating mask layer from the back surface of the leadframe at one or more lead locations; applying etching to the back surface of the metal leadframe to remove metal material which is not covered by the plating mask layer and thus remove electrically conductive lead formations at the one or more lead locations where the plating mask layer was selectively removed in order to control a creepage distance between two other lead locations where the plating mask layer was not selectively removed.
Chen teaches selectively removing the plating mask layer from the back surface of the leadframe at one or more lead locations. (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (plating mask layer) via laser ablating.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Camacho and Chen, such that the masking layer is selectively removed to expose at least one of the electrically conductive lead formations in order to, for example, allow for further processing and development of future electrical connections while still maintaining an adequate level of protection via the masking layer.
Camacho et al. still fails to teach applying etching to the back surface of the pre-plated metal leadframe to remove metal material which is not covered by the plating mask layer and thus remove electrically conductive lead formations at the one or more lead locations where the plating mask layer was selectively removed in order to control a creepage distance between said two other lead locations where the plating mask layer was not selectively removed.
Signorini teaches applying etching to the back surface of the metal leadframe to remove metal material which is not covered by the plating mask layer and thus remove electrically conductive lead formations at the one or more lead locations where the plating mask layer was selectively removed in order to control a creepage distance between two other lead locations where the plating mask layer was not selectively removed ([0039] point to a method of processing a copper layer (leadframe) by first patterning said layer to form pads (electrically conductive lead formations) and then etching to remove the unwanted copper areas (metal material).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Camacho et al. and Signorini, such that at least one of the electrically conductive lead formations is etched and removed from the substrate in order to reduce capacitive coupling, improve thermal management, and/or prevent unintended contacts.
Regarding claim 10, Chen teaches wherein selectively removing comprises performing a laser ablating of the plating mask layer to uncover the one or more lead locations of the metal leadframe (Fig. 4H and [0040] point to removing a portion of a first conductive layer 140 (plating mask layer) via laser ablating.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Fontana et al. and chen, such that the masking layer is selectively removed via laser ablation in order to make use of maskless, non-contact patterning while avoiding the difficulties that would come from wet etching a masking layer comprised of multiple materials.
Regarding claim 11, Camacho teaches wherein the plating masking layer is made of a NiPdAu plating (Col. 6, lines 37-41 and 47-50 point to the exterior pad 210 (plating masking layer) comprising the same materials as the interior pad 208 and the interior paddle pad 214, that being a nickel palladium gold alloy (NiPdAu).).
Response to Arguments
Applicant’s arguments, see Remarks, filed 03/19/2026, with respect to the rejection(s) of claim(s) 1 and 9 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Camacho (US Patent No. 8604596) in further view of Chen and Signorini.
Conclusion
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/PATRICK CULLEN/Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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