DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of species D/fig. 4, reflected in claims 1-22, 24-28 and 30 in the reply filed on XXX is acknowledged. Claims 23, 29 are withdrawn from further consideration pursuant to 37 CFR 1.142 (b), as being drawn to the nonelected group.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4-8 and 12-13 and 24-18 are rejected under 35 U.S.C. 103 as being unpatentable over DONG et al. (US 20130334601 A1, hereinafter Dong‘601) in view of Izumi et al. (US 20090078996 A1, hereinafter Izumi‘996).
Regarding independent claim 1, Dong‘601 teaches, “A semiconductor device (fig. 1-6; ¶ [0013] - ¶ [0136]), comprising:
a silicon layer (105) having an electrically insulated backside (BOX layer of SOI substrate, ¶ [0013]) and ((a thickness in a range of 10 µm to 200 µm between a frontside of the silicon layer and the electrically insulated backside));
a high voltage region (110, ¶ [0048]) and a low voltage region (210) formed in the silicon layer (105) and laterally spaced apart from one another; and
a first field plate structure (142, 134) extending from the frontside into the silicon layer (105), the first field plate structure (142, 134) comprising a field plate (142) laterally separated from the silicon layer (105/112) by a dielectric material (134) and/or a pn junction”.
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But Dong‘601 is silent upon the provision of wherein a thickness in a range of 10 µm to 200 µm between a frontside of the silicon layer and the electrically insulated backside.
However, Izumi‘996 teaches a semiconductor device using SOI substrate (2, fig. 1), wherein the thickness of the silicon layer is 30 µm (¶ [0037]), which meets the limitataion a thickness in a range of 10 µm to 200 µm between a frontside of the silicon layer (5) and the electrically insulated backside (BOX layer 4).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Dong‘601 and Izumi‘996 to form the silicon layer of claimed dimension according to the teachings of Izumi‘996 as this thickness helps to achieve target withstand voltage of the instant device (transistor). See Izumi‘996, ¶ [0003] - ¶ [0010].
Regarding claim 2, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the first field plate structure (142, 134, fig. 2b, Dong‘601) adjoins the high voltage region (110), and wherein the field plate (142, 134) is electrically connected to a same potential as the high voltage region (110)”.
Regarding claim 4, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, further comprising: a second field plate structure (142, 142, fig. 1b, Dong‘601) extending into the silicon layer from the frontside, the second field plate structure comprising a field plate laterally separated from the silicon layer by a dielectric material (134) and/or a pn junction, wherein the first field plate structure adjoins the high voltage region and the field plate of the first field plate structure is electrically connected to a same potential as the high voltage region, wherein the second field plate structure adjoins the low voltage region and the field plate of the second field plate structure is electrically connected to a same potential as the low voltage region ”. Applying potentials to the field plates is an operational language describing a way to configure the claimed device to operate in a way. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02.
Regarding claim 5, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the first field plate structure (142, fig. 1b, Dong‘601) electrically isolates first and second circuit areas (140, 150 and 144, 160) from one another within the silicon layer”.
Regarding claim 6, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 5, wherein the field plate is electrically connected to a doped region of one of the first and second circuit areas” (field plates are conventionally connected to source during operation).
Regarding claim 7, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 6, further comprising: a second field plate structure (142, fig. 1b, Dong‘601) extending into the silicon layer from the frontside, the second field plate structure comprising a field plate laterally separated from the silicon layer by a dielectric material (134) and/or a pn junction, wherein the second field plate structure electrically isolates the second circuit area from a third circuit area(140, 150 and 144, 160), wherein the field plate of the first field plate structure is electrically connected to a doped region of the first circuit area, wherein the field plate of the second field plate structure is electrically connected to a doped region of the second or the third circuit area”.
Regarding claim 8, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 6, further comprising: a second field plate structure (142, fig. 1b, Dong‘601) extending into the silicon layer from the frontside, the second field plate structure comprising a field plate laterally separated from the silicon layer by a dielectric material (134) and/or a pn junction, wherein the second field plate structure electrically isolates the second circuit area from a third circuit area(140, 150 and 144, 160), wherein the field plate of the first field plate structure is electrically connected to a doped region of the first circuit area, wherein the field plate of the second field plate structure is electrically connected to a doped region of the second or the second circuit area”.
Regarding claim 12, “The semiconductor device of claim 1, wherein the field plate is electrically connected to an electric potential such that a depletion region, accumulation region, or conductive channel forms along a sidewall of the first field plate structure when the electric potential is applied”, Dong‘601 modified with Izumi‘996 teaches all the elements including the field plate (fig. 2b) described in claim 1 and 12. The rest limitations in the instant claim 12 describes an intended manner in which the claimed device to be employed. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). See MPEP § 2144.02.
Regarding claim 13, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the field plate (142, 134, fig. 2b, Dong‘601) is electrically floating”.
Regarding claim 24, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the first field plate structure is segmented into a plurality of trench sections (fig. 1b, Dong‘601, two trenches are shown) that are laterally spaced apart from one another by a region of the silicon layer (105/112)”.
Regarding claim 25, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the first field plate structure (142, 134, fig. 2b, Dong‘601) terminates at a depth in the silicon layer (105) before reaching the electrically insulated backside (BOX layer of SOI substrate, ¶ [0013])”.
Regarding claim 26, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the field plate (142, fig. 1b) comprises a mesa of the silicon layer (105/112) that is surrounded by the dielectric material (132) and/or pn junction”.
Regarding claim 27, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the field plate (142, 134, fig. 2b, Dong‘601) comprises polysilicon (¶ [0029]) surrounded by the dielectric material (134) and/or pn junction of the first field plate structure”.
Regarding claim 28, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the first field plate structure (142, 134, fig. 2b, Dong‘601) comprises a trench that extends from the frontside into the silicon layer (105), and wherein the dielectric material (134) lines a sidewall and a bottom of the trench”.
Claims 1, 3, 9-11, 14-21 are rejected under 35 U.S.C. 103 as being unpatentable over Mehrotra et al. (US 20210159323 A1, hereinafter Mehrotra‘323) in view of Izumi et al. (US 20090078996 A1, hereinafter Izumi‘996).
Regarding independent claim 1, Mehrotra‘323 teaches, “A semiconductor device (fig. 1-15; ¶ [0014] - ¶ [0061]), comprising:
a silicon layer (105/103, fig. 9, 1) having an electrically insulated backside (103 is a SOI substrate, ¶ [0015]) and ((a thickness in a range of 10 µm to 200 µm between a frontside of the silicon layer and the electrically insulated backside));
a high voltage region (905) and a low voltage region (903) formed in the silicon layer (105) and laterally spaced apart from one another; and
a first field plate structure (701) extending from the frontside into the silicon layer (105), the first field plate structure (701) comprising a field plate laterally separated from the silicon layer (1055) by a dielectric material (301, 601) and/or a pn junction”.
But Mehrotra‘323 is silent upon the provision of wherein a thickness in a range of 10 µm to 200 µm between a frontside of the silicon layer and the electrically insulated backside.
However, Izumi‘996 teaches a semiconductor device using SOI substrate (2, fig. 1), wherein the thickness of the silicon layer is 30 µm (¶ [0037]), which meets the limitataion a thickness in a range of 10 µm to 200 µm between a frontside of the silicon layer (5) and the electrically insulated backside (BOX layer 4).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Mehrotra‘323 and Izumi‘996 to form the silicon layer of claimed dimension according to the teachings of Izumi‘996 as this thickness helps to achieve target withstand voltage of the instant device (transistor). See Izumi‘996, ¶ [0003] - ¶ [0010].
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Regarding claim 3, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the first field plate structure (701, fig. 9, Mehrotra‘323) adjoins the low voltage region (903), and wherein the field plate (701) is electrically connected to a same potential as the low voltage region (fig. 10)”.
Regarding claim 9, Mehrotra‘323 modified with Izumi‘996 further teaches, “ The semiconductor device of claim 1, wherein the field plate (701, fig. 9, Mehrotra‘323) is electrically connected to a doped region (903, ¶ [0043]) of the semiconductor layer, the doped region (903) having a higher doping concentration than a background doping concentration of the silicon layer (105)”.
Regarding claim 10, Mehrotra‘323 modified with Izumi‘996 further teaches, “ The semiconductor device of claim 9, wherein the doped region (903) has a same conductivity type as the semiconductor layer (105)”.
Regarding claim 11, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 9, wherein the doped region (903) has an opposite conductivity type as the semiconductor layer (107)”.
Regarding claim 14, Dong‘601 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the high voltage region (905) is a cathode region of a power diode, wherein the low voltage region (903) is an anode region of the power diode, and wherein the first field plate structure (701) extends through an n-type region (105) of the power diode that extends from the cathode region in a direction of the anode region”.
Regarding claim 15, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the high voltage region (905, fig. 9, Mehrotra‘323) is a drain region of a power transistor, wherein the low voltage region (903) is a source region of the power transistor, and wherein the first field plate structure (701) extends through an extension region of the power transistor that connects a body region of the power transistor to the drain region (905)”.
Regarding claim 16, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 15, wherein the first field plate structure (701) comprises a needle-shaped trench that extends through the extension region”.
Regarding claim 17, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 15, wherein the field plate (701, fig. 11, Mehrotra‘323) is electrically connected to an additional field plate (1105) overlaying the frontside of the silicon layer (105)”.
Regarding claim 18, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 15, wherein the field plate (701, ¶ [0043]) is electrically connected to a doped region (903) at the frontside of the silicon layer (105), and wherein the doped region (903) has a higher doping concentration than a background doping concentration of the silicon layer (105)”.
Regarding claim 19, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 15, further comprising: a plurality of additional field plate structures (1226, fig. 12, Mehrotra‘323) extending the frontside of the silicon layer (1207) through the extension region of the power transistor, each additional field plate structure (1226) comprising a field plate laterally separated from the silicon layer by a dielectric material (1229) and/or a pn junction, wherein the additional field plate structures (1229) are needle-shaped and laterally spaced apart from one another”.
Regarding claim 20, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 1, wherein the high voltage region (905, fig. 9, Mehrotra‘323) is a drain region of a power transistor, wherein the low voltage region is a source region (903) of the power transistor, wherein the first field plate structure (701) extends at least partly along a body region (107) interposed between the source region and the drain region, and wherein the field plate is biased such that an inversion region, accumulation region, or depletion region formed along a sidewall of the first field plate structure defines a side gate at least partly along the body region (this feature is a property of similar devices)”.
Regarding claim 21, Mehrotra‘323 modified with Izumi‘996 further teaches, “The semiconductor device of claim 20, wherein the first field plate structure (701, Mehrotra‘323, fig. 9) laterally surrounds (partially) a device cell that includes the source region, the drain region, and the body region”.
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Mehrotra‘323 modified with Izumi‘996 as applied to claim 1 above, and further in view of Dong‘601.
Regarding claim 22, Mehrotra‘323 modified with Izumi‘996 teaches all the limitations described in claim 21.
Mehrotra‘323 modified with Izumi‘996 further teaches, a second field plate structure (1226, fig. 12, Mehrotra‘323) extending from the frontside of the silicon layer into the body region (1215, 1217), the second field plate structure comprising a field plate (1226) laterally separated from the silicon layer by a dielectric material (1229) and/or a pn junction,
wherein the field plate of the second field plate structure is biased such that an inversion region, accumulation region, or depletion region formed along a sidewall of the second field plate structure defines a side gate along a side of the body region segment opposite the first field plate structure (this feature is a property of similar devices).
But Mehrotra‘323 modified with Izumi‘996 is silent upon the provision of wherein
wherein the second field plate structure is spaced inward from the first field plate structure such that a segment of the body region is interposed between the first field plate structure and the second field plate structure.
However, Dong‘601 teaches a similar device (fig. 1b), wherein the second field plate structure (142) is spaced inward from the first field plate structure (142) such that a segment of the body region (114) is interposed between the first field plate structure and the second field plate structure.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Mehrotra‘323 modified with Izumi‘996 and Dong‘601 to arrange the field plate structures according to the teachings of Dong‘601 to achieve target switching speed and high breakdown voltage. See Dong‘601, ¶ [0001] – ¶ [0005].
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Dong‘601 modified with Izumi‘996 as applied to claim 1 above, and further in view of Kitagawa (US 20080315343 A1, hereinafter Kitagawa‘343).
Regarding claim 30, Dong‘601 modified with Izumi‘996 teaches all the limitations described in claim 1.
But Dong‘601 modified with Izumi‘996 is silent upon the provision of wherein the first field plate structure comprises a trench that extends from the frontside into the silicon layer and terminates at the electrically insulated backside, wherein the dielectric material lines a sidewall of the trench, and wherein the field plate terminates at the electrically insulated backside at a bottom of the trench.
However, Kitagawa‘343 teaches all the limitations of claim 1 (fig. 4A-4B, silicon layer 43, high voltage region 49 side, low voltage region 48 side, field plate 45B, dielectric material 17, insulated backside layer 12). Kitagawa‘343 further teaches, wherein the first field plate structure comprises a trench (T) that extends from the frontside into the silicon layer (43) and terminates at the electrically insulated backside, wherein the dielectric material (17) lines a sidewall of the trench (T), and wherein the field plate (45B) terminates at the electrically insulated backside at a bottom of the trench (T).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Dong‘601 modified with Izumi‘996 and Kitagawa‘343 to terminate the field plate trench at the insulated backside according to the teachings of Kitagawa‘343 with a motivation of achieving low leakage current as mentioned by Kitagawa‘343, ¶ [0224].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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