DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant's election without traverse of Species III directed to Fig. 4A (Claims 1-20) in the reply filed on September 8th, 2025 is acknowledged.
Claim Objections
Claims 11 and 18 are objected to because of the following informalities:
Claim 11 recites “the fin-type active areas” in line 17 referring back to “a plurality of fin-type active areas” in line 2 and should be amended to “the plurality of fin-type active areas” for avoiding confusion. Appropriate correction is required.
Claim 18 recites “the pair of first nanosheet stacks” and “the pair of second nanosheet stacks in lines 12 and 16 then claim 18 recites “a pair of first nanosheet stacks” and “a pair of second nanosheet stacks” later in lines 20-21 and 22-23 for creating confusion on antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 7-11, 13 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over HA et al. (Pub. No.: US 2021/0217860 A1), hereinafter as Ha in view of Wang et al. (Pub. No.: US 2022/0336614), hereinafter as Wang.
Regarding claim 1, Ha discloses an integrated circuit device in Figs. 1-5 comprising: a plurality of fin-type active areas (plurality of first active patterns AP1 with protruding shape) extending in a first horizontal direction (direction D1) on a substrate (substrate 100) (see Fig. 1 and [0022-0024]); a plurality of channel regions (channel patterns CH1 includes semiconductor patterns CP1, CP2 and CP3) respectively on the plurality of fin-type active areas (see Fig. 2 and [0025]); a plurality of gate lines (plurality of gate electrodes GE) surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction (direction D2) that crosses the first horizontal direction (see Figs. 1-2, 4 and [0028-0030]); and a plurality of source/drain regions (source/drain patterns SD1) each arranged at positions adjacent to at least one of the plurality of gate lines on a respective one of the plurality of fin-type active areas and in contact with at least one of the plurality of channel regions (see Figs. 1-2 and [0025-0027]), wherein each of the plurality of source/drain regions has a bottom surface (bottom surface of layer SL1 of each source/drain patterns SD1) in contact with the respective one of the plurality of fin-type active areas (first patterns AP1), wherein the plurality of source/drain regions respectively include a plurality of semiconductor layers (layers SL1, SL2, SL3 and SL4), and wherein the plurality of semiconductor layers include: a first semiconductor layer (buffer layer SL1) including a part in contact with the at least one of the plurality of channel regions (CP1, CP3 and CP3) and a part in contact with the respective one of the plurality of fin-type active areas (first patterns AP1) (see Figs. 2, 5 and [0046], [0050], [0054]); a second semiconductor layer (intermediate layer SL2) on the first semiconductor layer (see Figs. 2, 5 and [0053-0054]); and a third semiconductor layer (main layer SL3) on the second semiconductor layer (see Figs. 2, 5 and [0053-0054]).
Ha fails to disclose the plurality of source/drain regions respectively includes at least one air gap located therein.
Wang discloses an integrated circuit device in Figs. 2D-2H comprising: a plurality of source/drain regions (first epitaxial layers 220 and second epitaxial layers 230) in contact with a plurality of channel regions (semiconductor layers 208’) (see Figs. 2E-2F and [0022-0023], [0031-0033]), wherein the plurality of source/drain regions respectively includes at least one air gap (voids portions 226B’ and 226C’) located therein (see Fig. 2H and [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the plurality source/drain regions of Ha to have at least one air gap therein as same as the plurality source/drain regions of Wang because the modified device would improve the electrical characteristic by reducing parasitic capacitances when at least one void/air gap present in the source/drain features (see Wang and [0040]).
Regarding claim 2, the combination of Ha and Wang discloses the integrated circuit device of claim 1, wherein the at least one air gap is located inside the plurality of semiconductor layers and includes an air gap (one of voids 226B’ and 226C’) spaced apart from the plurality of fin-type active areas with some portion of the plurality of semiconductor layers therebetween (see Ha, Fig. 2 and Wang, Fig. 2H).
Regarding claim 3, the combination of Ha and Wang discloses the integrated circuit device of claim 1, wherein the at least one air gap includes an air gap (void 226B’/226C’) located between boundary surfaces of two different semiconductor layers among the plurality of semiconductor layers (between left outer surface of first epitaxial layer 220 and right outer surface of second epitaxial layer 230) (see Wang, Fig. 2F-2H and [0026-0027]).
Regarding claim 4, the combination of Ha and Wang discloses the integrated circuit device of claim 1, but fails to disclose wherein a pitch of the plurality of source/drain regions in the first horizontal direction is about 40 nm to about 60 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have the integrated circuit device comprising wherein a pitch of the plurality of source/drain regions in the first horizontal direction is about 40 nm to about 60 nm because the pitch can be controlled by method of etching based on manufacturing desire for producing gate all around transistors. Since it has been held that wherein the general conditions of a claim are disclosed in the prior art, discovering optimum or workable ranges involve only routine skill in the art. In re Aller, 105 USPQ 233
Regarding claim 7, the combination of Ha and Wang discloses the integrated circuit device of claim 1, wherein: each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer (each of layers SL1, SL2 and SL3 include SiGe having different concentration of Ge with range of at %) includes a SiXGex layer (where, x ≠ 0) doped with a p-type dopant (boron doping), and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer have different Ge content ratios (see Ha, Fig. 5 and [0053-0054]).
Regarding claim 8, the combination of Ha and Wang discloses the integrated circuit device of claim 1, wherein: each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer (each of layers SL1, SL2 and SL3 include SiGe having different concentration of Ge with range of at %) includes a SiXGeX layer (where, x≠0) doped with a p-type dopant (boron doping), a Ge content ratio of the first semiconductor layer is smaller than a Ge content ratio of the second semiconductor layer (concentration of Ge of layer SL1 is less than concentration of Ge of layer SL2), and the Ge content ratio of the second semiconductor layer is smaller than a Ge content ratio of the third semiconductor layer (concentration of Ge of layer SL2 is less than concentration of Ge of layer SL3) (see Ha, Fig. 5 and [0053-0054]).
Regarding claim 9, the combination of Ha and Wang discloses the integrated circuit device of claim 1, Ha further disclose wherein: the plurality of channel regions (semiconductor patterns CP1, CP2 and CP3) include a plurality of semiconductor sheets respectively facing fin top surfaces of the plurality of fin-type active areas (top surfaces of first active patterns AP1) at positions spaced apart from the fin top surfaces and having different vertical distances from the fin top surfaces (semiconductor patterns CP1, CP2 and CP3 are stacked vertically at different height from the top surfaces of first active patterns AP1), and the plurality of source/drain regions are respectively in contact with the plurality of semiconductor sheets (see Figs. 2, 5 and [0025]).
Ha fails to disclose the plurality of channel regions include a plurality of nanosheets.
Wang discloses a plurality of channel regions (channel layers 208’) includes a plurality of nanosheets (see Fig. 2F-2H and [0031]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the plurality of channel regions of Ha to include a plurality of nanosheets as same as the plurality of channel regions of Wang because the modified device would improve speed and more power efficiency with nano size channels.
Regarding claim 10, the combination of Ha and Wang discloses the integrated circuit device of claim 1, wherein an air gap is absent from between the plurality of fin-type active areas and bottom surfaces of the plurality of source/drain regions (see Ha, Fig. 2 and Wang, Fig. 2H).
Regarding claim 11, Ha discloses an integrated circuit device in Figs. 1-5 comprising: a plurality of fin-type active areas (plurality of first active patterns AP1 with protruding shape) extending in a first horizontal direction (direction D1) on a substrate (substrate 100) (see Fig. 1 and [0022-0024]); a plurality of channel regions (channel patterns CH1 includes semiconductor patterns CP1, CP2 and CP3) respectively on the plurality of fin-type active areas, each of the plurality of channel regions spaced apart from the fin top surfaces at different distances in a vertical direction (direction D3) (see Fig. 2 and [0025]); a plurality of gate lines (plurality of gate electrodes GE) surrounding the plurality of channel regions on the plurality of fin-type active areas and extending in a second horizontal direction (direction D2) that crosses the first horizontal direction (see Figs. 1-2, 4 and [0028-0030]); and a plurality of source/drain regions (source/drain patterns SD1) having side surfaces (side surfaces of layer SL1) that face the plurality of channel regions in the first horizontal direction (direction D1), (see Figs. 1-2 and [0025-0027]), wherein each of the plurality of source/drain regions has a bottom surface (bottom surface of layer SL1 of each source/drain patterns SD1) in contact with the respective one of the plurality of fin-type active areas (first patterns AP1), wherein the plurality of source/drain regions respectively include a plurality of semiconductor layers (layers SL1, SL2, SL3 and SL4), and wherein each respective the plurality of semiconductor layers includes: a first semiconductor layer (buffer layer SL1) in contact with some of the plurality of channel regions (CP1, CP3 and CP3) in contact with at least one of the plurality of fin-type active areas (first patterns AP1) (see Figs. 2, 5 and [0046], [0050], [0054]); a second semiconductor layer (intermediate layer SL2) on the first semiconductor layer (see Figs. 2, 5 and [0053-0054]); and a third semiconductor layer (main layer SL3) on the second semiconductor layer (see Figs. 2, 5 and [0053-0054]).
Ha fails to disclose the plurality of channel regions include a plurality of nanosheets and each of the plurality of source/drain regions respectively includes at least one air gap located therein.
Wang discloses an integrated circuit device in Figs. 2D-2H comprising: a plurality of channel regions (channel layers 208’) includes a plurality of nanosheets (see Fig. 2F-2H and [0031]), a plurality of source/drain regions (first epitaxial layers 220 and second epitaxial layers 230) in contact with the plurality of nanosheets (semiconductor layers 208’) (see Figs. 2E-2F and [0022-0023], [0031-0033]), wherein each of the plurality of source/drain regions respectively includes at least one air gap (voids portions 226B’ and 226C’) located therein (see Fig. 2H and [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the plurality of channel regions of Ha to include a plurality of nanosheets as same as the plurality of channel regions of Wang because the modified device would improve speed and more power efficiency with nano size channels.
Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the plurality source/drain regions of Ha to have at least one air gap therein as same as the plurality source/drain regions of Wang because the modified device would improve the electrical characteristic by reducing parasitic capacitances when at least one void/air gap present in the source/drain features (see Wang and [0040]).
Regarding claim 13, the combination of Ha and Wang discloses the integrated circuit device of claim 11, wherein the at least one air gap includes an air gap (void 226B’/226C’) located between boundary surfaces of two different semiconductor layers among the plurality of semiconductor layers (between left outer surface of first epitaxial layer 220 and right outer surface of second epitaxial layer 230) (see Wang, Fig. 2F-2H and [0026-0027]).
Regarding claim 15, the combination of Ha and Wang discloses the integrated circuit device of claim 11, wherein: each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer (each of layers SL1, SL2 and SL3 include SiGe having different concentration of Ge with range of at %) includes a SiXGex layer (where, x ≠ 0) doped with a p-type dopant (boron doping), and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer have different Ge content ratios (see Ha, Fig. 5 and [0053-0054]).
Regarding claim 16, the combination of Ha and Wang discloses the integrated circuit device of claim 11, wherein: each of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer (each of layers SL1, SL2 and SL3 include SiGe having different concentration of Ge with range of at %) includes a SiXGeX layer (where, x≠0) doped with a p-type dopant (boron doping), a Ge content ratio of the first semiconductor layer is smaller than a Ge content ratio of the second semiconductor layer (concentration of Ge of layer SL1 is less than concentration of Ge of layer SL2), and the Ge content ratio of the second semiconductor layer is smaller than a Ge content ratio of the third semiconductor layer (concentration of Ge of layer SL2 is less than concentration of Ge of layer SL3) (see Ha, Fig. 5 and [0053-0054]).
Regarding claim 17, the combination of Ha and Wang discloses the integrated circuit device of claim 11, wherein the plurality of source/drain regions (SD1 of Ha) are respectively in contact with the plurality of nanosheets (CP1, CP2 and CP3 of Ha being modified into nanosheets) (see Ha, Fig. 2 and [0025-0027], and Wang, Fig. 2H and [0031]).
Allowable Subject Matter
Claims 5-6, 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner's statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claimed invention having:
Wherein the plurality of fin-type active areas include a first fin-type active area in a first region of the substrate and a second fin-type active area in a second region of the substrate, the plurality of gate lines include a pair of first gate lines on the first fin-type active area in the first region and spaced apart from each other in the first horizontal direction with a first distance therebetween, and a pair of second gate lines on the second fin-type active area in the second region and spaced apart from each other in the first horizontal direction with a second distance that is greater than the first distance therebetween, wherein the plurality of source/drain regions include first source/drain regions between the pair of first gate lines in the first region, and second source/drain regions between the pair of second gate lines in the second region, wherein the first source/drain regions have a top surface at a higher vertical level than a vertical level of an uppermost surface of the plurality of channel regions, and wherein the second source/drain regions have a top surface at a lower vertical level than a vertical level of the top surface of the first source/drain regions, and do not include an air gap therein as recited in claim 5.
Wherein the at least one air gap includes an air gap located inside each of the plurality of semiconductor layers as recited in claim 12.
And wherein: the plurality of fin-type active areas include a first fin-type active area in a first region of the substrate and a second fin-type active area in a second region of the substrate, the plurality of nanosheets include a plurality of first nanosheets spaced apart from a first fin top surface of the first fin-type active area in the vertical direction, and a plurality of second nanosheets spaced apart from a second fin top surface of the second fin-type active area in the vertical direction, the plurality of gate lines include a pair of first gate lines on the first fin-type active area in the first region and spaced apart from each other in the first horizontal direction with a first distance therebetween, and a pair of second gate lines on the second fin-type active area in the second region and spaced apart from each other in the first horizontal direction with a second distance that is greater than the first distance therebetween, the plurality of source/drain regions include a first source/drain region between the pair of first gate lines in the first region, and a second source/drain region between the pair of second gate lines in the second region, the first source/drain region has a top surface at a higher vertical level than a vertical level of a top surface of a nanosheet having a greatest vertical distance from the fin top surface among the plurality of first nanosheets, the second source/drain region has a top surface at a lower vertical level than a vertical level of the top surface of the first source/drain region, and the second source/drain region does not include an air gap therein as recited in claim 14.
Claim 6 depends on claim 5, and therefore also include said claimed limitation.
Claims 18-20 would be allowed over prior art of record if amended or written to overcome the objection of claim 18 as set forth in the office action above.
The following is an examiner' s statement of reason for allowance: the prior art made of record does not teach or fairly suggest the following: wherein the first source/drain region has a top surface at a higher vertical level than a vertical level of a top surface of a nanosheet having a greatest vertical distance from the first fin top surface among the plurality of first nanosheets, and wherein the second source/drain region has a top surface at a lower vertical level than a vertical level of the top surface of the first source/drain region, and wherein the second source/drain region does not include an air gap therein as recited in claim 18. Claims 19-20 depend on claim 18, and therefore also include said claimed limitation.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CUONG B NGUYEN whose telephone number is (571)270-1509 (Email: CuongB.Nguyen@uspto.gov). The examiner can normally be reached Monday-Friday, 8:30 AM-5:00 PM Eastern Standard Time.
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/CUONG B NGUYEN/Primary Examiner, Art Unit 2818