Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 03/30/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
While the previous action indicated that claim language was allowable, however, upon further consideration, it has become apparent that there is some clarity in the claim language that needs to be addressed.
Claims 6 and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Currently claims 5 and 16 discloses the limitation of “a passivation layer disposed on the encapsulant and covering the second redistribution layer”. Claim 6 and 17 which depends on claims 5 or 16 discloses that the same passivation layer “includes a plurality of openings exposing portions of the second redistribution layer”. Examiner believes that it is unclear how the passivation layer can both be covering the second encapsulation layer and have holes in the passivation layer that are specifically made to expose the second redistribution layer. Examiner believes that it would add further clarity if instead the limitation in claims 5 and 16 was instead that “a passivation layer disposed on the encapsulant and at least partially covering the second redistribution layer”. Examiner believes that this language makes clear that it is possible for the passivation layer to not fully cover the second redistribution wiring such as where there are holes in the passivation layer to expose the second distribution wiring. As independent claims 1 and 8 from which claims 5 and 16 depend are indicated to contain allowable subject matter, Examiner believes that this clarity does not hinder searching, however, the claims do still need to have appropriate action taken.
Pertinent Prior art made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
United States Patent Application Publication by Hsu et al. (US 20200251414 A1; Hsu)
United States Patent by Yu et al. (US 9768145 B2; Yu)
Allowable Subject Matter
Claims 1-5, 7-16, 18-20 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding the independent claims 1, 8, and 19, the prior fails to anticipate or in an obvious combination the limitations of the independent claims in the instant application.
Currently, Hsu discloses a semiconductor package (S20), comprising:
a connection structure (RDL1 - DI) having first and second surfaces opposing each other (Fig. 4, First surface is the lower surface and the second surface is the upper surface in the figure) and including an insulating layer (DI – Para. 11, the dielectric layer inside RDL1 where the rest of the connection structure is ‘on’ the dielectric layer) and a first redistribution layer (RDL1) on the insulating layer (Fig. 4, Where RDL1 is “on” the dielectric layer in DI);
a semiconductor chip (106) disposed on the first surface of the connection structure and including connection pads (106a-2) connected to the first redistribution layer (Fig. 4, where the chip is at the first surface [bottom] of the connection layer and pads 106a-2 are present);
an encapsulant disposed (108’) on the first surface of the connection structure and encapsulating the semiconductor chip (Fig. 4);
a second redistribution layer (RDL2) disposed on the encapsulant (Para. 24);
a wiring structure (104) connecting the first and second redistribution layers to each other and extending in a stacking direction (Fig. 4); and
a heat dissipation element (102) disposed on at least a portion of the second surface of the connection structure (Para. 29, “Subsequently, the conductive carrier 102 is patterned to form a heat dissipation element 102′ comprising a conductive base CB and a plurality of antenna patterns AP”).
Regarding specifically Claim 1, the prior art of record fails to show or collectively teach wherein the second surface of the connection structure includes a first region overlapping the semiconductor chip in the stacking direction and a second region, and the heat dissipation element is disposed on the first region to expose the second region of the connection structure.
Regarding specifically Claims 8, the prior art of record fails to show or collectively teach wherein at least one surface-mount component disposed on the second region of the connection structure and connected to the first redistribution layer as well as a separate adhesive layer attaching the heat dissipation element to the insulating layer of the connection structure.
Regarding specifically Claim 19, Hsu discloses a semiconductor package (S20), comprising:
a connection structure (RDL1 - DI) having first and second surfaces opposing each other (Fig. 4, First surface is the lower surface and the second surface is the upper surface in the figure) and including an insulating layer (DI – Para. 11, the dielectric layer inside RDL1 where the rest of the connection structure is ‘on’ the dielectric layer) and a first redistribution layer (RDL1) on the insulating layer (Fig. 4, Where RDL1 is “on” the dielectric layer in DI);
a semiconductor chip (106) disposed on the connection structure and having an active surface facing the first surface of the connection structure (Para. 40, “In other words, the active surface AS of the semiconductor die 106 is facing the first redistribution layer RDL1”), and connection pads (106a-2) arranged on the active surface, the connection pads connected to the first redistribution layer (Fig. 4, where the chip is at the first surface [bottom] of the connection layer and pads 106a-2 are present); an encapsulant disposed (108’) on the first surface of the connection structure and encapsulating the semiconductor chip (Fig. 4); a second redistribution layer (RDL2) disposed on the encapsulant (Para. 24); a wiring structure (104) connecting the first and second redistribution layers to each other and extending in a stacking direction (Fig. 4); an; and a plurality of underbump metal layers (112) connected to the second redistribution layer (Fig. 4). The prior art of record fails to show or collectively teach a separate adhesive layer attaching the heat dissipation element to the insulating layer of the connection structure as well as wherein a heat dissipation element disposed on an entire area of the second surface of the connection structure and furthermore, a passivation layer disposed on the encapsulant and covering the second redistribution layer.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 8am-5pm EST.
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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