Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/20/2026 has been entered.
Response to Arguments/Remarks made in Amendment
Applicant's arguments on pages 5-7 of “Applicant Arguments/Remarks Made in an Amendment” filed 05/05/2026 regarding the 35 U.S.C. 103 rejections of claims 1-4 have been fully considered but they are not persuasive. Applicant reiterates that the instant invention uses a single step of dispensing the device encapsulate and pressing the device encapsulate into the opening, and that the cited art of Tuominen teaches separate steps of dispensing the device encapsulate and pressing the device encapsulate into the opening. The previous office action agreed with this position just that the step of depositing the second encapsulate also does some pressing onto the device encapsulate. Applicant has amended the claim in an attempt to further clarify the separation of these steps and to overcome Tuominen by adding the limitation “after disposing the semiconductor device in the opening, dispensing a device encapsulant onto the semiconductor device” (underlined portion). This limitation appears to introduce a timing element, where the semiconductor device must be disposed in the opening before the disposing of the device encapsulate. Applicant argues that in Tuominen’s process, the device encapsulate (74) is dispensed before first encapsulation (68) and core layer (62) are disposed. Examiner argues that, this new limitation is still taught by Tuominen, as the new limitation is directed on if the device is disposed in the opening before the device encapsulate and if the device is disposed in the opening. It is clear that the semiconductor device is disposed before the device encapsulate, See Figs. 17A-17B. And further, the semiconductor device is still disposed where the opening is. Therefore, Examiner believes that this new limitation is still disclosed by Tuominen.
Applicant also amends claim 1 to include the limitation, “applying a second encapsulant layer onto the device encapsulant and simultaneously laminating together the first and second encapsulant layers so that the device encapsulant is pressed into the opening (underlined portion), and argues that this makes it clear that pressing of the device encapsulate in the opening is part of a combined, single step laminating and compression molding that is not taught by Tuominen. Examiner disagrees, as the language of the new limitation is just that the first and second encapsulate layers are simultaneously laminated with each other. As when laminating one thing with another, it doesn’t really make sense for there to be an instance where the two things are not simultaneously laminated, as long as the two things are laminated, it will be simultaneous with each other. In Tuominen, the first encapsulation layer (68) and the second encapsulation layer (69) are at least laminated with each other (See Fig. 17D, Para. 140), which means they are also laminated simultaneously with each other. Examiner believes that Tuominen still discloses this limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Tuominen in view of United States Patent Application Publication by Gavagnin et al. (US 20180213647 A1; Gavagnin).
Regarding claim 1, Tuominen discloses a method for fabricating a semiconductor device module, the method comprising:
providing a first encapsulant layer (68) and a core layer (62) disposed on the first encapsulant layer, wherein the core layer comprises an opening (66) (Para. 140, and Fig. 17D, where core layer 62 is disposed on first encapsulate layer 68, and there are holes ‘opening’ in core layer 66);
disposing a semiconductor device (6) in the opening (Fig. 17D, where semiconductor device is in opening 66),
after disposing the semiconductor device in the opening dispensing a device encapsulant (74) onto the semiconductor device (Figs. 17A-D, Where the semiconductor device 6 is disposed before the device encapsulation 74, and the semiconductor device is disposed where the opening is);
applying a second encapsulant layer (69) onto the device encapsulant (Fig. 17D, where second encapsulate layer is applied onto encapsulate 74) and simultaneously laminating together the first and second encapsulant layers (See Fig. 17D, Para. 140, Where the first encapsulation layer (68) and the second encapsulation layer (69) are at least laminated with each other, which would also mean they are laminated simultaneously with each other) so that the device encapsulant is pressed into the opening (Fig. 13B and Para. 108); and
laminating together the first and second encapsulant layers and the device encapsulant (Fig. 17E, Para 140, “On top of the unified insulation material sheet 69 the second conductive layer 9 will be laminated to the electronic module 160).
Tuominen discloses where the semiconductor device is a die, but fails to disclose where the semiconductor device is explicitly recited as a device comprising a die carrier and a semiconductor die disposed on the die carrier.
It is well known in the art to use a carrier for a semiconductor die in an opening of a module when the semiconductor dies calls for the need of a carrier and one of ordinary skill in the art would have recognized this. In a similar field of endeavor, Gavagnin discloses depositing a semiconductor die (102) on a die carrier (104) in an opening (110) (Figs. 17-21).
In view of the disclosure of Gavagnin and common knowledge of one of ordinary skill in the art, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Gavagnin to Tuominen at the time the instant application was filed to incorporate a die carrier with the semiconductor device including a die. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand that choosing a semiconductor die that requires a die carrier would necessitate the need to include such.
Regarding claim 2, the combination of Tuominen and Gavagnin disclose the method of claim 1, and further Tuominen additionally discloses wherein one or both of the first encapsulant layer and the second encapsulant layer comprises a polymer layer or a prepreg layer, respectively (Tuominen: Para. 94, “The core sheet 62 can be manufactured from one, two or several prepreg layers with aid of heat and pressure”).
Regarding claim 3, the combination of Tuominen and Gavagnin disclose the method of claim 1, and further Tuominen additionally discloses wherein the core layer comprises one of an FR1, FR2, FR3, or an FR4 material, a BT-epoxy, a polyimide, a cyanate ester, an organic material, an inorganic material, an electrically insulating material, or an electrically conductive material (Tuominen: Para. 94, lines 5-8).
Regarding claim 4, the combination of Tuominen and Gavagnin discloses the method of claim 1, and further Tuominen additionally discloses wherein the device encapsulant comprises a material which is one or more of:
one out of the group of adhesives, including a duromer, an elastomer and a thermoplastic,
a liquid mold compound,
a resin, an organic resin, an epoxy resin, an inorganic resin, a granulate, a polyimide, a silicone, a cyanate ester, or mixtures of the above components (Tuominen: Fig. 16C, where filler material 74 is a liquid mold compound)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Tuominen and Gavagnin, and further in view of United States Patent Application Publication by Woychik et al. (US 20080314867 A1; Woychik).
Regarding claim 17, the combination of Tuominen and Gavagnin disclose the method of claim 4, however, the combination of Tuominen and Gavagnin fails to disclose wherein the device encapsulant further comprises filler particles comprising metal oxide and/or metal nitride.
In [0100], however, Woychik discloses an encapsulant including filler particles comprising metal oxide and/or metal nitride.
Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known filler particle for a encapsulate such as metal oxide and/or metal nitride, as shown by Woychik [0100], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose filler particles comprising metal oxide and/or metal nitride over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer.
Allowable Subject Matter
Claims 19-20 allowed.
Claim 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 18-20, the prior art from at least Tuominen and Gavagnin discloses at least a method of fabricating a semiconductor module where the method includes the steps recited in claim 1, as shown above in the claim 1 rejection. However, Tuominen and Gavagnin, nor other prior art either anticipates or as in an obvious combination the step of “wherein when applying the second encapsulant layer onto the device encapsulant so that the device encapsulant is pressed into the opening, the device encapsulant completely fills the opening and partially flows out of the opening to form exit areas located outside of the opening in intermediate spaces between the core layer and the first and/or second encapsulant layers”. It is for at least this reason that claims 18-20 contain allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights