Prosecution Insights
Last updated: April 19, 2026
Application No. 18/140,976

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE MODULE WITH INCREASED RELIABILITY AND A SEMICONDUCTOR DEVICE MODULE

Final Rejection §103
Filed
Apr 28, 2023
Examiner
HIBBERT, DANIEL JOHNATHAN
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies Austria AG
OA Round
2 (Final)
83%
Grant Probability
Favorable
3-4
OA Rounds
3y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
10 granted / 12 resolved
+15.3% vs TC avg
Strong +33% interview lift
Without
With
+33.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
29 currently pending
Career history
41
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
37.3%
-2.7% vs TC avg
§102
32.6%
-7.4% vs TC avg
§112
28.0%
-12.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 12 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments/Remarks made in Amendment Applicant's arguments filed regarding the 35 U.S.C. 103 rejections of claims 1-4 on Pages 6-8 of “Applicant Arguments/Remarks Made in an Amendment” on 12/17/2025 have been fully considered but they are not persuasive. Applicant argues that the rejection is improper for at least claim 1 because the prior art of Tuominen corresponds to two separate steps for the deposition and pressing related to the encapsulate layer. One step of applying the second encapsulate layer on the device layer and a different step pressing the second encapsulate layer so the device encapsulate is pressed into the opening. While the instant application is only a single step based on the line from claim 1, “applying a second encapsulant layer onto the device encapsulant so that the device encapsulant is pressed into the opening”. Examiner agrees that there are two different steps of depositing and further pressing of the encapsulate in Tuominen. However, that doesn't mean there is no pressing action being done while applying the second encapsulate on top of the device encapsulate. As the second encapsulate has a weight to it, by depositing the a second encapsulate on top of the device encapsulate, there is at least some pressing of the device encapsulate into the opening, even if the entirety of the pressing isn't done to the degree where a satisfactory amount of the device encapsulate is in the opening, which results in the need for another pressing step afterward. While there is an additional step in Tuominen of pressing alone without application of the second encapsulate, that doesn't mean there is no pressing in the application step, and convention would argue that putting something with mass on top of something else with mass under gravity, there is some pressing that the upper mass would have on the lower mass, in this case the second encapsulate on the device encapsulate. Its for these reasons at least that examiner disagrees that no pressing is being done with the application step, and that Tuominen recites at least the limitations in the in the steps of claim 1 of the instant application, and that the 35 U.S.C. 103 rejections of claims 1-4 will not be withdrawn. Applicant’s arguments, see Page 5 of “Applicant Arguments/Remarks Made in an Amendment” filed 12/17/2025, with respect to the 35 U.S.C. 112 rejections of claims 1 and 4 have been fully considered and are persuasive. The addition of “device” to “encapsulate” removes all ambiguity of which encapsulate is which. The 35 U.S.C. 112 of Claims 1 and 4 has been withdrawn. The rejections of claims 5-16 have been withdrawn based on applicant’s cancelation of claims11-16. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Tuominen in view of United States Patent Application Publication by Gavagnin et al. (US 20180213647 A1; Gavagnin). Regarding claim 1, Tuominen discloses a method for fabricating a semiconductor device module, the method comprising: providing a first encapsulant layer (68) and a core layer (62) disposed on the first encapsulant layer, wherein the core layer comprises an opening (66) (Para. 140, and Fig. 17D, where core layer 62 is disposed on first encapsulate layer 68, and there are holes ‘opening’ in core layer 66); disposing a semiconductor device (6) in the opening (Fig. 17D, where semiconductor device is in opening 66), dispensing a device encapsulant (74) onto the semiconductor device (Fig. 17B); applying a second encapsulant layer (69) onto the device encapsulant (Fig. 17D, where second encapsulate layer is applied onto encapsulate 74) so that the device encapsulant is pressed into the opening (Fig. 13B and Para. 108); and laminating together the first and second encapsulant layers and the device encapsulant (Fig. 17E, Para 140, “On top of the unified insulation material sheet 69 the second conductive layer 9 will be laminated to the electronic module 160). Tuominen discloses where the semiconductor device is a die, but fails to disclose where the semiconductor device is explicitly recited as a device comprising a die carrier and a semiconductor die disposed on the die carrier. It is well known in the art to use a carrier for a semiconductor die in an opening of a module when the semiconductor dies calls for the need of a carrier and one of ordinary skill in the art would have recognized this. In a similar field of endeavor, Gavagnin discloses depositing a semiconductor die (102) on a die carrier (104) in an opening (110) (Figs. 17-21). In view of the disclosure of Gavagnin and common knowledge of one of ordinary skill in the art, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Gavagnin to Tuominen at the time the instant application was filed to incorporate a die carrier with the semiconductor device including a die. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand that choosing a semiconductor die that requires a die carrier would necessitate the need to include such. Regarding claim 2, the combination of Tuominen and Gavagnin disclose the method of claim 1, and further Tuominen additionally discloses wherein one or both of the first encapsulant layer and the second encapsulant layer comprises a polymer layer or a prepreg layer, respectively (Tuominen: Para. 94, “The core sheet 62 can be manufactured from one, two or several prepreg layers with aid of heat and pressure”). Regarding claim 3, the combination of Tuominen and Gavagnin disclose the method of claim 1, and further Tuominen additionally discloses wherein the core layer comprises one of an FR1, FR2, FR3, or an FR4 material, a BT-epoxy, a polyimide, a cyanate ester, an organic material, an inorganic material, an electrically insulating material, or an electrically conductive material (Tuominen: Para. 94, lines 5-8). Regarding claim 4, the combination of Tuominen and Gavagnin discloses the method of claim 1, and further Tuominen additionally discloses wherein the device encapsulant comprises a material which is one or more of: one out of the group of adhesives, including a duromer, an elastomer and a thermoplastic, a liquid mold compound, a resin, an organic resin, an epoxy resin, an inorganic resin, a granulate, a polyimide, a silicone, a cyanate ester, or mixtures of the above components (Tuominen: Fig. 16C, where filler material 74 is a liquid mold compound) Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Tuominen and Gavagnin, and further in view of United States Patent Application Publication by Woychik et al. (US 20080314867 A1; Woychik). Regarding claim 17, the combination of Tuominen and Gavagnin disclose the method of claim 4, however, the combination of Tuominen and Gavagnin fails to disclose wherein the device encapsulant further comprises filler particles comprising metal oxide and/or metal nitride. In [0100], however, Woychik discloses an encapsulant including filler particles comprising metal oxide and/or metal nitride. Accordingly, before the effective filling date of the invention, it would have been obvious to one having ordinary skill in the art to select a known filler particle for a encapsulate such as metal oxide and/or metal nitride, as shown by Woychik [0100], since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. See MPEP § 2144.07 (citing In re Leshin, 277 F.2d 197 (C.C.P.A. 1960)). One would be motivated to choose filler particles comprising metal oxide and/or metal nitride over other materials depending on manufacturing considerations such as cost of materials or time it takes to process the layer. Allowable Subject Matter Claim 19 allowed. Claim 18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 18 and 19, the prior art from at least Tuominen and Gavagnin discloses at least a method of fabricating a semiconductor module where the method includes the steps recited in claim 1, as shown above in the claim 1 rejection. However, Tuominen and Gavagnin, nor other prior art either anticipates or as in an obvious combination the step of “wherein when applying the second encapsulant layer onto the device encapsulant so that the device encapsulant is pressed into the opening, the device encapsulant completely fills the opening and partially flows out of the opening to form exit areas located outside of the opening in intermediate spaces between the core layer and the first and/or second encapsulant layers”. It is for at least this reason that claims 18 and 19 contain allowable subject matter. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL J HIBBERT whose telephone number is (703)756-1562. The examiner can normally be reached Monday - Friday 8am-5pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL J HIBBERT/Examiner, Art Unit 2899 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 28, 2023
Application Filed
Sep 24, 2025
Non-Final Rejection — §103
Dec 17, 2025
Response Filed
Mar 11, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12575447
QFN PACKAGING STRUCTURE AND QFN PACKAGING METHOD
2y 5m to grant Granted Mar 10, 2026
Patent 12543337
OXIDE FILM COATING SOLUTION AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME
2y 5m to grant Granted Feb 03, 2026
Patent 12506045
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Dec 23, 2025
Patent 12484411
METHOD OF MANUFACTURING DISPLAY DEVICE
2y 5m to grant Granted Nov 25, 2025
Patent 12444694
Semiconductor Device and Method of Forming Selective EMI Shielding with Slotted Substrate
2y 5m to grant Granted Oct 14, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+33.3%)
3y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 12 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month