DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (original claims 1-14 and new claims 21-22) and Species B (Fig. 3; claims 1-14 and 21-22) in the reply filed on 1.20.2026 is acknowledged. Claims 15-20 drawn to Invention II have been canceled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 7-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsuchiko (US 20130069154 A1).
Regarding claim 1, Tsuchiko discloses an integrated circuit (Figs. 2 and 14) comprising:
a first epitaxial layer (16) having a first conductivity type (P, [0017]) over a semiconductor substrate (14) having a top surface;
a second epitaxial layer (18) having (partly) the first conductivity type (P in 148, [0020]) over the first epitaxial layer;
a first doped region (136) having a different second conductivity type (N, [0020]) between and extending into the substrate (14) and the first epitaxial layer (16);
a second doped region (134) having the second conductivity type (N, [0020]) between and extending into the first epitaxial layer (16) and the second epitaxial layer (18. See Fig. 10: 134 extends into 18);
a well region (126/156) having the first conductivity type (P, [0020], [0033]) extending from a top surface of the second epitaxial layer (18) into the second epitaxial layer over the first doped region (136); and
an active device (LDMOS) formed over or in the well region over the first doped region (Figs. 2 and 14).
Regarding claim 7, Tsuchiko discloses the integrated circuit of claim 1, wherein the active device is a transistor (Fig. 14).
Regarding claim 8, Tsuchiko discloses the integrated circuit of claim 1, wherein the active device includes an LDMOS transistor (Fig. 14).
Regarding claim 9, Tsuchiko discloses the integrated circuit of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type ([0017], [0020], [0033]).
Allowable Subject Matter
Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 10-14 and 21-22 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the prior art of record fails to disclose or suggest wherein the second doped region has a higher average dopant concentration than does the first doped region.
Regarding claim 3, the prior art of record fails to disclose or suggest wherein a portion of the first epitaxial layer between the first and second doped regions has an unmodified dopant concentration.
Regarding claim 4, the prior art of record fails to disclose or suggest wherein the first doped region is spaced apart from the top surface of the second epitaxial layer by a first distance and merges with a third doped region having the second conductivity type that is laterally spaced apart from the first doped region and vertically spaced apart from the top surface by a lesser second distance; claims 5-6 depend from claim 4.
Regarding claim 10, the prior art of record fails to disclose or suggest a second P-type epitaxial layer extending between the first P-type epitaxial layer and a top surface of the second P-type epitaxial layer; an unmodified portion of the first P-type epitaxial layer between the first N-type buried layer and the P-type buried layer; a second N-type buried layer extending into the first P-type epitaxial layer and laterally spaced apart from and at a same height over the substrate as the P-type buried layer; and a third N-type buried layer in the first P-type epitaxial layer between the second N-type buried layer and the substrate as recited within the context of claim; claims 11-14 and 21-22 depend from claim 10.
With regards to independent claim 10, the closest prior art (Tsuchiko, US 20130069154 A1) discloses an integrated circuit (Figs. 1 and 16) comprising:
a first N-type buried layer (136) extending into a semiconductor substrate (14);
a first P-type epitaxial layer (16) extending from the first N-type buried layer away from the substrate;
a P-type buried layer (137) extending into the first P-type epitaxial layer over the first N-type buried layer;
a second
a P-type well (156) in the second
a second N-type buried layer (134) extending into the first P-type epitaxial layer
a transistor formed in or over the P-type well (156, Fig. 16).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818