Prosecution Insights
Last updated: May 29, 2026
Application No. 18/141,265

STRUCTURE AND METHOD FOR BONDED WAFER BARRIER

Non-Final OA §102
Filed
Apr 28, 2023
Priority
Feb 16, 2023 — provisional 63/485,300
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Non-Final)
85%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
709 granted / 838 resolved
+16.6% vs TC avg
Moderate +8% lift
Without
With
+8.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
14 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.2%
+9.2% vs TC avg
§102
46.9%
+6.9% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 838 resolved cases

Office Action

§102
DETAILED ACTION Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al. (Liu, US 2015/0266722 A1). Regarding claim 1, Liu shows an apparatus comprising: a semiconductor device (device 38 in FIG. 9 and [0015]) layer including a bond pad area (area 52 as shown in FIG. 5), a bond pad (pad 52 in Fig. 9) on the semiconductor device layer (element 36) in the bond pad area; a scribe seal (element 60) on the semiconductor device layer (element 36), the scribe seal (element 60) surrounding the bond pad area on at least three sides (see FIG. 9); and a swarf barrier ( cap layer 64 in FIG. 6) on the scribe seal (element 60), the swarf barrier including: a first portion ( portion of element 64 in The cavity as shown in FIG. 6) a first distance (see Fig. 6) from the semiconductor device layer; and a second portion ( element 64) a second distance (top to bottom portion) from the semiconductor device layer, the second distance being larger than the first distance (see FIG. 6). Regarding claim 2, Liu shows an apparatus comprising: a semiconductor device (device 38 in FIG. 9 and [0015]), wherein the second portion ( top to bottom portion of element 64) is structured to contact a second layer on top of the semiconductor device layer (element 36). Regarding claim 3, Liu shows an apparatus comprising: a semiconductor device (device 38 in FIG. 9 and [0015]), wherein the second portion of the swarf barrier (top to bottom portion of element 64) includes at least one of a curved portion, an angled portion, or a step-up portion (see FIG. 5). Regarding claim 4, Liu shows an apparatus comprising: a semiconductor device (device 38 in FIG. 9 and [0015]), wherein, further including a bond ring (element 36) on the semiconductor device layer, the swarf barrier connected to the bond ring (see FIG. 5-9). Regarding claim 13, Liu shows an apparatus comprising: a first layer ( layer 74); a bond pad ( layer 36) in a bond area on the first layer (layer 74); a second layer (layer 52); a bond ring (element 36) coupling the first layer and the second layer (see FIG. 9), a cavity (see FIG. 9) between the first layer and the second layer at least partially surrounded by the bond ring (element 36), the bond pad outside the cavity; a scribe seal ( element 60) on the first layer; and a swarf barrier (element 64) on the scribe seal, the swarf barrier surrounding the bond pad area on at least three sides ( see FIG. 5-9). Allowable Subject Matter Claims 5-12 are allowed. Claims 14-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Apr 28, 2023
Application Filed
Jul 15, 2025
Non-Final Rejection mailed — §102
Nov 17, 2025
Response Filed
Apr 10, 2026
Request for Continued Examination
Apr 20, 2026
Response after Non-Final Action
May 20, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+8.0%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 838 resolved cases by this examiner. Grant probability derived from career allowance rate.

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