Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al US 20230386915 A1 and further in view of Song et al US 20220093594 A1. Cheng et al and Song et al will be referenced to as Cheng and Song respectively henceforth.
Regarding Claim 1,
Cheng teaches:
“A semiconductor unit comprising (annotated FIG. 19 #1):
A semiconductor device (annotated FIG. 19 #1) on a substrate (substrate 100, [0010]), the semiconductor device having at least one terminal (source/drain features 116, [0013]) and at least 2 sides (annotated FIG. 19 #1: a first side and a second side.), the substrate being on a first side of the semiconductor device (annotated FIG. 19 #1);
A back-end-of-line (BEOL) region comprising a plurality of metal layers ([0027]: metal wire layers 128, top metal layer 128A, and top metal layer 24 are a plurality of metal layers. See FIG. 2 for labeling of 128.), and disposed on the opposite side of the semiconductor device from the substrate (annotated FIG. 19 #1); and
A backside contact in the substrate (contact plug 144, liner 134, silicide layer 138, [0017], [0019], [0029]) and in contact with a first surface of a terminal of the at least one terminal of the semiconductor device (annotated FIG. 19 #1),
Wherein the backside contact has a side contacting the terminal (annotated FIG. 19 #1), a side contacting a backside power rail (first metal wire layer 148A, [0024] annotated FIG. 19 #1), and sidewalls extending from the terminal to the backside power rail (annotated FIG. 19 #1); and
Wherein the sidewalls of the backside contact have a positive slope (annotated FIG. 19 #1: Applicant describes a positive slope as,
“"positive slope" indicates that the sidewalls of backside contact 335 lean outwards in such a way that the-14- width W of the backside contact 335, where it contacts the source-drain 310b, is less than the width W' of the backside contact 335 where it contacts the backside power rail 330.”
Given that first metal wire layer 148A of Cheng is a backside power rail, the backside contact of Cheng has sidewalls such that the width of the backside contact at 148A is thicker than the width of the backside contact at the source/drain region.) and are lined with a dielectric liner (liner 134, [0017]: the liner may include SiN, a dielectric material.).”
Cheng doesn’t substantially teach:
“the first surface of the terminal being in direct contact with the substrate and the backside contact;”
However, Song teaches:
“the first surface of the terminal being in direct contact with the substrate and the backside contact (Song: [0056], annotated FIG. 4A #1: The first surface of the terminal 416(1)S is in direct contact with both backside metal contact 432(1) and substrate 410.);”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Cheng is modifiable in view of Song.
This is because Cheng teaches a first surface of a source/drain region contacting a backside contact in a substrate wherein an isolation region separates the source/drain region from the substrate to prevent the disturbing of adjacent routing areas. Cheng doesn’t substantively teach a first surface of a source/drain region directly contacting a substrate and a backside contact. Song teaches a first surface of a source/drain region contacting a backside contact in a substrate. Song further teaches a first surface of a source/drain region directly contacting a substrate and a backside contact wherein the backside contact has a small enough diameter to prevent the disturbing of adjacent routing areas. Because both Cheng and Song have a first surface of a source/drain region contacting a backside contact in a substrate, one of ordinary skill in the art would have deemed it obvious to substitute the first surface of a source/drain region contacting a backside contact, wherein the backside contact is in a substrate, of Cheng for a first surface of a source/drain region which directly contacts a substrate and a backside contact within the substrate of Song for the predictable result of a backside contact in a substrate which does not disturb adjacent routing areas.
Further, Song shows FIG. 5A, as an alternative to FIG. 4A, wherein an isolation layer (Song: BOX layer 412, [0064]) separates a source/drain region from a substrate. One of ordinary skill in the art would recognize that FIG.5’s geometry is analogous to the geometry of Cheng. Therefore, one of ordinary skill in the art would determine that the inclusion of an isolation layer separating a source/drain from a substrate is optional as this is shown in the contrasting of Song’s FIG. 4A with respect to Song’s FIG. 5A.
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Regarding Claim 2,
Cheng/Song teaches:
“The semiconductor unit of claim 1, wherein the dielectric liner comprises at least one material from among (Cheng: [0017]: the liner may include SiN, a dielectric material.)”
Regarding Claim 3,
Cheng/Song teaches:
“The semiconductor unit of claim 1, additionally comprising a middle-of-line (MOL) region between the semiconductor device and the BEOL region (Cheng: annotated FIG. 19 #1), wherein the MOL region (Cheng: gate contact via 124, annotated FIG. 19 #1: see FIG. 2 for labeling of 124), connecting the semiconductor device to the BEOL metal layers (Cheng: annotated FIG. 19 #1: 124 connects to 128).”
Regarding Claim 4,
Cheng/Song teaches:
“The semiconductor unit of claim 1, wherein the BEOL metal layers comprise signal routing layers (Cheng: top metal layers 24, [0028], FIG. 19: 24 is the only connection to passive components 26. 26 may be a memory device. Therefore, the signal inputs from the transistors into 26 must come from 24. Therefore 24 is a signal routing line.).”
Regarding Claim 5,
Cheng/Song teaches:
“The semiconductor unit of claim 1, wherein the backside contact comprises at least one material from among (Cheng: metal contact layer 143, [0023], FIG. 13: 144 is formed from 143. 143 comprises tungsten (W).).”
Regarding Claim 6,
Cheng/Song teaches:
“The semiconductor unit of claim 1, wherein the backside power rail comprises at least one material from among ([0024]: 148 may comprise Ru, Cu, Mo, and Al.).”
Regarding Claim 7,
Cheng/Song teaches:
“The semiconductor unit of claim 1, wherein the sidewalls of the backside contact are substantially straight (annotated FIG. 19 #1).”
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ju et al and further in view of Song. Ju et al will be referenced to as Ju henceforth.
Regarding Claim 8,
Ju teaches:
“A method for forming a semiconductor unit, comprising:
Forming a semiconductor device (the semiconductor device described in FIG. 7-27B) on a substrate (substrate 140, [0037], FIG. 7-20: Notice 140), the semiconductor device having at least one terminal (source/drain epitaxial structure 106, [0025], FIG. 17A) and at least 2 sides (annotated FIG. 20 #1), the substrate being on a first side of the semiconductor device (annotated FIG. 20 #1);
Forming a back-end-of-line (BEOL) region (annotated FIG. 27B #1) comprising a plurality of metal layers (front side metal layers 116, [0026], [0060], FIG. 3, FIG. 20, FIG. 22B: 116 is formed in FIG. 20 though not visible. 116 is labeled in FIG. 3.), disposed on the opposite side of the semiconductor device from the substrate (FIG. 22B: substrate layer 146 is on the opposite side of the semiconductor device region from 116.); and
Forming a backside contact in the substrate (source/drain contact 120, [0063], [0066], FIG. 23B – 26B. sacrificial source/drain contact 236 becomes 120.) and in contact with a first surface of a terminal of the at least one terminal of the semiconductor device (FIG. 26B: 120 contacts 106.), ;
Wherein the backside contact has a first side contacting the terminal ([0028], annotated FIG. 27B #1, 120 contacts 106b, a portion of 106.), a second, opposite side contacting a backside power rail (back-side power rail 122, [0027], annotated FIG. 27B #1), and sidewalls extending from the terminal to the backside power rail (annotated FIG. 27B #1); and
Wherein the sidewalls of the backside contact have a positive slope and are lined with a dielectric liner (annotated FIG. 27B #1: Applicant describes a positive slope as,
“"positive slope" indicates that the sidewalls of backside contact 335 lean outwards in such a way that the-14- width W of the backside contact 335, where it contacts the source-drain 310b, is less than the width W' of the backside contact 335 where it contacts the backside power rail 330.”
Given that the width of 120 at 106b is thinner than the width of 120 at 122, 120 meets the limitation.) and are lined with a dielectric liner (dielectric sidewall spacer 118, [0027], FIG. 27B).”
Ju doesn’t substantially teach:
“the first surface of the terminal being in direct contact with the substrate and the backside contact”
However, Song teaches:
“the first surface of the terminal being in direct contact with the substrate and the backside contact (Song: [0056], annotated FIG. 4A #1: The first surface of the terminal 416(1)S is in direct contact with both backside metal contact 432(1) and substrate 410.)”
It would have been obvious to one with ordinary skill in the art before the effective filing
date of the invention to recognize that the device of Ju is modifiable in view of Song.
This is because Song teaches that a sufficiently small diameter of a backside contact provides the benefit of reducing the disturbing of adjacent routing areas. One of ordinary skill in the art would recognize that a, “sufficiently small diameter” would be as shown in FIG. 4A of Song wherein the backside contact has a smaller diameter than the source region.
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Regarding Claim 9,
Ju/Song teaches:
“The method of claim 8, wherein forming the backside contact comprises:
Forming, on a preliminary substrate (Ju: substrate layer 146, [0037], FIG. 23B), a pillar structure having sloped sidewalls (Ju: second sacrificial source/drain contact 236, [0063], FIG. 23B), the pillar sloped so that the widest end is in contact with the preliminary substrate (Ju: FIG. 23B, the widest end at the top of 236 contacts 146 on its sides.). ”
Regarding Claim 10,
Ju teaches:
“The method of claim 9, wherein forming the backside contact additionally comprises: Forming, on the sidewalls of the pillar structure, the sidewall dielectric liner (Ju: [0027], FIG. 26B: 118 is disposed on 120.).”
Allowable Subject Matter
Claims 11-15 are allowed to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 11,
Ju fails to explicitly teach :
“forming, around the pillar sidewalls, additional preliminary substrate, such that the preliminary substrate is level with the top of the pillar structure.” In view of the rest of the limitations of claim 11.
Ju fails to explicitly teach the above limitation because it is not obvious to combine the invention of Ju with other art which teaches the above limitation. Namely, one of ordinary skill in the art would not see it as obvious to have one step in which they add some additional preliminary substrate and another where they add enough additional preliminary substrate such that the preliminary substrate is level with the top of the pillar structure. The Examiner found similar art which may meet the limitations added in claim 11, but such limitations are not met in view of claim 10 upon which claim 11 depends. Such art includes US 20220270924 A1.
The Examiner did not find prior art which one of ordinary skill in the art would use alone or would find obvious to combine with the invention of Ju to reach all of the limitations of the claim.
Regarding Claims 12-15, these claims depend on claim 11 and are objected to for the same reasons.
Response to Arguments
Applicant’s amendments to the Claims have overcome the Examiner’s 102(a)(1) and 102(a)(2) rejections.
Applicant’s arguments, with respect to the rejection(s) of claim(s) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Song.
In the interest of compact prosecution, if the Applicant were to amend an independent claim with the following limitation:
“wherein the MOL region comprises at least one of a front-side contact or a via, wherein a front-side contact or a via is in direct contact with a second terminal and an ILD layer”
It would overcome the current rejections for claim 1. The Examiner is available for interview at Applicant’s convenience for discussion of claim amendments.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDRE XAVIER RAMIREZ whose telephone number is (571)272-2715. The examiner can normally be reached Monday - Friday 8:30 AM to 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDRE X RAMIREZ/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812