DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed October 1, 2025 have been fully considered but they are not persuasive.
Applicant argues it is unclear how the contacts 133, 134, and 135 in Lin are considered separate, distinct contacts to correspond to the claimed further conductive layer that covers both the conductive layer 208 and the contact 122.
In response, each of the three portions 133, 134, and 135 that make up the further conductive layer correspond to each of the three portions 12 that make of the further conductive layer in the figures of the instant application. For example, in Lin portion 135 of the further conductive layer covers both the first conductive layer 208 and the electrical connector 122.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-9, 12, 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2012/0134115 (Schulz-Harder), cited by Applicant in view of U.S. Patent Application Publication No. 2020/0098727 (Mallik) and U.S. Patent Application Publication No. 2019/0252329 (Lin).
Schulz-Harder discloses (Fig. 1)
1. (Currently Amended) A semiconductor package, comprising
a ceramic plate 3;
a first conductive layer 4 disposed on the plate 3, the first conductive layer 4 comprising a first portion 4.2 and a second portion 4.1;
a semiconductor transistor die 7 disposed above the first portion 4.2 of the first conductive layer 4; and
a semiconductor die 6 disposed on the second portion 4.1 of the first conductive layer 4.
Schulz-Harder fails to disclose
an electrical connector disposed between the semiconductor transistor die and the first portion of the first conductive layer;
a semiconductor logic die;
a further conductive layer covering at least in part the first conductive layer and the electrical connector; and
an encapsulant 59 covering at least in part the plate 3, the first conductive layer 31 / 33 / 35 and/or the further conductive layer, the semiconductor transistor die 9 and the semiconductor (logic) die 7.
Mallik teaches (Fig. 1D)
A semiconductor package, comprising
a first conductive layer disposed on the plate 110;
an electrical connector 114 disposed between the semiconductor transistor die 20 and the first portion 116 (right side) of the first conductive layer 116;
a semiconductor logic die 10 disposed on the second portion 116 (left) of the first conductive layer 116; and
an encapsulant 126 covering at least in part the plate 110, the first conductive layer 116, the semiconductor transistor die 20 and the semiconductor logic die 10.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an electrical connector, a logic die, and an encapsulant in Schulz-Harder. The motivation would be to a matter of routine engineering design considerations since electrical connectors and an encapsulant are well-known in the semiconductor package art, and a logic die could be used such as pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like as taught by Mallik [0085]. See MPEP 2144.03, 2144.07.
Lin teaches
A semiconductor package, comprising
a further conductive layer 133 / 134 / 135 covering the first conductive layer 208 and the electrical connector 122.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a further conductive layer in Schulz-Harder. The motivation would be to provide adhesion and protection from warpage as discussed in Lin ([0036]).
Schulz-Harder discloses ([0016])
2. The semiconductor package according to claim 1, wherein the ceramic plate 3 comprises one of Al2O3, AlN, Si3N4, or zirconia toughened alumina, BeO, SiC, or any other ceramic according to DIN V ENV 12212.
Schulz-Harder discloses ([0016])
3. The semiconductor package according to claim 1, wherein the ceramic plate 3 comprises a thickness greater than 500 µm or greater than 600 µm or greater than 635 µm.
Schulz-Harder discloses ([0017])
4. The semiconductor package according to claim 1, wherein the first conductive layer 4 comprises an electrical conductivity of >30% according to the International Annealed Copper Standard.
Schulz-Harder discloses ([0017])
5. The semiconductor package according to claim 4, wherein the first conductive layer 4 comprises a copper basis with a share of >50%.
Schulz-Harder discloses ([0024])
6. The semiconductor package according to claim 1, wherein a thickness of the first conductive layer 4 is in a range from 5 to 150 µm, or from 20 to 125 µm, or from 30 to 100 µm.
Mallik teaches ([0022])
7. The semiconductor package according to claim 1, wherein the electrical connector 114 comprises an electrical conductivity of >70% according to the International Annealed Copper Standard.
Mallik teaches ([0022]), selecting the optimum material would only have involved routine skill in the art. See MPEP 2144.07.
8. The semiconductor package according to claim 1, wherein the electrical connector 114 comprises one of OF-Copper or tough pitch copper.
Mallik teaches ([0022]), selecting the optimum thickness would only have involved routine skill in the art. See MPEP 2144.07.
9. The semiconductor package according to claim 1, wherein the electrical connector 114 comprises a thickness greater than 125 µm or greater than 300 µm.
Schulz-Harder discloses
12. The semiconductor package according to claim 1, wherein the ceramic plate 3 is disposed on a metallic substrate 5.
Lin teaches ([0017])
15. (Currently Amended) The semiconductor package according to claim 1, wherein the further conductive layer 133 / 134 / 135 is a plated layer.
Lin teaches ([0023])
16. The semiconductor package according to claim 15, wherein the plated layer is an electroless plating (product-by-process language, see MPEP 2113) of copper, nickel, gold, silver or any layer stack thereof.
Schulz-Harder discloses ([0018])
17. The semiconductor package according to claim 1, wherein the semiconductor transistor die 7 is a power semiconductor transistor die.
Schulz-Harder discloses ([0017]), Lin teaches [0022]
18. (New) The semiconductor package according to claim 1,
wherein the first conductive layer comprises a copper basis with a share of > 50%, and
wherein the further conductive layer is an electroless plated layer of copper, nickel, gold, silver or any layer stack thereof.
Claim(s) 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schulz-Harder in view of Mallik as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2016/0329312 (O'Mullan).
The combination of references fails to teach
10. The semiconductor package according to claim 1, further comprising a plurality of pins, wherein first pins of the plurality of pins are connected with the semiconductor transistor die, and second pins of the plurality of pins are connected with the semiconductor logic die.
O’Mullan teaches ([0021], [0025])
A semiconductor package, comprising
a plurality of pins, wherein first pins of the plurality of pins are connected with the semiconductor transistor die 20, and second pins of the plurality of pins are connected with the semiconductor logic die 25.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include pins in Schulz-Harder. The motivation would be a matter of routine engineering design considerations since pins are well-known in the semiconductor package art as taught by O’Mullan. See MPEP 2144.03, 2144.07.
O’Mullan teaches ([0021])
11. (Currently Amended) The semiconductor package according to claim 10, wherein the first conductive layer 50, 55, 60 comprises a plurality of third portions disposed on the ceramic plate, each one of the third portions connected with one of the second pins.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schulz-Harder in view of Mallik as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2015/0085454 (Hong), cited by Applicant.
The combination of references fails to teach
13. The semiconductor package according to claim 12, wherein a second conductive layer is disposed between the ceramic plate and the metallic substrate.
Hong teaches (Figs. 11, 12, 14)
A semiconductor package, comprising
wherein a second conductive layer 320 is disposed between the ceramic plate 210 and the metallic substrate 740.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a second conductive layer in the modified device of Schulz-Harder. The motivation would be so as to reduce electromagnetic noise and prevent moist infiltration and to dissipate heat as taught by Hong ([0042], [0050]).
Claim(s) 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Schulz-Harder, cited by Applicant in view of Mallik and U.S. Patent No. 11,437,354 (Ishimatsu).
Schulz-Harder discloses (Fig. 1)
19. (New) A semiconductor package, comprising
a ceramic plate 3;
a first conductive layer 4 disposed on the ceramic plate 3, the first conductive layer 4 comprising a first portion 4.2 and a second portion 4.1;
a semiconductor transistor die 7 disposed above the first portion 4.2 of the first conductive layer 4;
a semiconductor die 6 disposed on the second portion 4.1 of the first conductive layer 4;
Schulz-Harder fails to disclose
an electrical connector disposed between the semiconductor transistor die and the first portion of the first conductive layer;
a semiconductor logic die;
an encapsulant 59 covering at least in part the ceramic plate 3, the first conductive layer 31 / 33 / 35, the semiconductor transistor die 9 and the semiconductor (logic) die 7; and
a plurality of external pins,
wherein first external pins of the plurality of external pins are connected with the semiconductor transistor die, and second external pins of the plurality of external pins are connected with the semiconductor logic die.
Mallik teaches (Fig. 1D)
A semiconductor package, comprising
a first conductive layer disposed on the plate 110;
an electrical connector 114 disposed between the semiconductor transistor die 20 and the first portion 116 (right side) of the first conductive layer 116;
a semiconductor logic die 10 disposed on the second portion 116 (left) of the first conductive layer 116; and
an encapsulant 126 covering at least in part the plate 110, the first conductive layer 116, the semiconductor transistor die 20 and the semiconductor logic die 10.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an electrical connector, a logic die, and an encapsulant in Schulz-Harder. The motivation would be to a matter of routine engineering design considerations since electrical connectors and an encapsulant are well-known in the semiconductor package art, and a logic die could be used such as pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like as taught by Mallik [0085]. See MPEP 2144.03, 2144.07.
Ishimatsu teaches (at least Fig. 5)
A semiconductor package, comprising
a plurality of external pins 1, 2 wherein first pins of the plurality of pins are connected with the semiconductor transistor die 4B, and second pins of the plurality of pins are connected with the semiconductor logic die 4G.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include pins in Schulz-Harder. The motivation would be a matter of routine engineering design considerations since pins are well-known in the semiconductor package art as taught by Ishimatsu. See MPEP 2144.03, 2144.07.
Ishimatsu teaches
21. (New) The semiconductor package according to claim 19, wherein an end of each of the external pins 1, 2 protrudes from an outer surface of the encapsulant 7.
Wolf teaches
20. (New) The semiconductor package according to claim 19, wherein the first conductive layer 6 comprises a plurality of third portions disposed on the ceramic plate 3, each one of the third portions connected with one of the second pins 2.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication No. 2005/0006758 (Wolf) teaches a power semiconductor package.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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