DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1a and 2a in the reply filed on November 17, 2025 is acknowledged. The traversal is on the ground(s) that “the variations identified by the Examiner represent alternative embodiments of the same general architecture and do not necessitate materially different classifications, references, or search fields”. This is not found persuasive because the species require different arrangements of the fixed layer, sub-information storage layer, the cell transistor and the memcitor and search strategies and terms used to find art pertinent to one species is not likely to find art pertinent to another. For example, search terms and strategies used to find art disclosing a device with a fixed layer contacting each of a plurality of sub-information storage layers (species 1a) are not likely to result in finding art pertinent to a device where the fixed layer does not contact at least one of a plurality of sub-information storage layers (species 1b).
The requirement is still deemed proper and is therefore made FINAL.
Claims 6, 9, and 17 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on November 17, 2025.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "191" and "197" in Figs. 8A and 8B have both been used to designate the lower electrodes.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 7-8, 12, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nan et al. (CN 101834271 A) herein after “Nan”.
Regarding claim 1, Figs. 4a-4b of Nan disclose a semiconductor device comprising a plurality of memory cells (Figs. 4a-4b, magneto-electric random memory card unit 1, transistor 10, ¶ [0043]) each including a cell transistor (Figs. 4a-4b, transistor 10, ¶ [0043]) and a memcitor (Figs. 4a-4b, magneto-electric random memory card unit 1, ¶ [0043]) connected to the cell transistor (10), wherein:
the memcitor (1) includes an information storage layer (Fig. 4a, ferroelectric oxide layer 4, ¶ [0043]) including a ferroelectric material, a first electrode (Fig. 4a, second electrode 3, ¶ [0045]) and a second electrode (Fig. 4a, first electrode 2, ¶ [0043]) connected to both ends of the information storage layer (4), a fixed layer (Fig. 4a, sandwich structure 8, antiferromagnetic pinning layer 9, ¶ [0044] and [0049]) stacked on the information storage layer (4) and including a paraelectric material or an antiferroelectric material (“the antiferromagnetic pinning layer 9 is preferably but not limited to iron-manganese alloy (FeMn), nickel manganese alloy (NiMn), platinum-manganese alloy (PtMn) or other alloy material containing Mn is formed”, ¶ [0052]), and a third electrode (Fig. 4a, second bit line 18, ¶ [0043]) connected to the fixed layer (8, 9) without contacting the information storage layer (4).
Regarding claim 3, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 1 as applied above, and further disclose wherein the first electrode (3) and the second electrode (2) are arranged on a top surface (left side in Fig. 4a) and a bottom surface (right side in Fig. 4a) of the information storage layer (4), respectively, wherein the fixed layer (8, 9) is arranged on a side (top in Fig. 4a) of the information storage layer (4), and
wherein the third electrode (18) is arranged on a side of the fixed layer (8, 9), which is opposite to a side on which the information storage layer (4) is arranged.
Regarding claim 7, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 1 as applied above, and further disclose comprising:
a plurality of word lines (Figs. 4a-4b, word line 14, ¶ [0043]) extending in a first direction and apart from one another in a second direction perpendicular to the first direction; and
a plurality of bit lines (Figs. 4a-4b, first bit line 17, ¶ [0043]) extending in the second direction and apart from one another in the first direction, wherein a gate (Fig. 4b, gate 13, ¶ [0055]), a source (Fig. 4b, source 11, ¶ [0055]), and a drain (Fig. 4b, drain 12, ¶ [0055]) of a cell transistor (10) of each of the plurality of memory cells (1, 10) is connected to one of the plurality of word lines (14), one of the plurality of bit lines (17), and the second electrode (2).
Regarding claim 8, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 7 as applied above, and further disclose wherein the first direction and the second direction are horizontal directions that are orthogonal to each other (shown in Fig. 3).
Regarding claim 12, Figs. 4a-4b of Nan disclose a semiconductor device comprising:
a substrate (Fig. 4b, substrate of transistor 10);
a plurality of word lines (14) extending on the substrate (substrate of 10) in a first direction and apart from one another in a second direction perpendicular to the first direction;
a plurality of bit lines (17) extending on the substrate (substrate of 10) in the second direction and apart from one another in the first direction; and
a plurality of memory cells (1, 10) arranged between the plurality of word lines (14) and the plurality of bit lines (17) and each including a cell transistor (10) and a memcitor (1) connected to the cell transistor (10),
wherein the memcitor (1) includes:
an information storage layer (4) including a ferroelectric material;
a first electrode (3) and a second electrode (2) connected to both ends of the information storage layer (4);
a fixed layer (8, 9) that does not contact the first electrode (3) and the second electrode (2), that is stacked on the information storage layer (4), and that includes a paraelectric material or an antiferroelectric material; and
a third electrode (18) connected to the fixed layer (8, 9) without contacting the information storage layer (4).
Regarding claim 14, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 12 as applied above, and Figs. 5a-5b further disclose wherein a direction of polarization occurring in the information storage layer (4) is different from that of polarization occurring in the fixed layer (8, 9) (shown in Figs. 5a-5b).
Regarding claim 15, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 12 as applied above, and further disclose wherein the cell transistor (10) and the memcitor (1) are arranged in a vertical direction (shown in Figs. 4a-4b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Nan (CN 101834271 A) in view of Okuno (WO 2022176549 A1).
Regarding claim 2, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 1 as applied above, but fail to explicitly disclose wherein the information storage layer has an orthorhombic phase, and
wherein the fixed layer has a tetragonal phase.
In the similar field of endeavor of semiconductor storage devices, Okuno discloses wherein the information storage layer has an orthorhombic phase (“the abundance ratio of orthorhombic crystals contained in the ferroelectric layer 222 is higher”, ¶ [0043]), and
wherein the fixed layer has a tetragonal phase (“the paraelectric layer 122 may include… tetragonal crystals”, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the layers of Nan with the crystal phases as disclosed by Okuno, to obtain the desired ferroelectric properties (see Okuno, ¶ [0043]).
Regarding claim 13, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 12 as applied above, but fail to explicitly disclose wherein the information storage layer comprises a ferroelectric material having an orthorhombic phase dominant thickness, and
wherein the fixed layer comprises a paraelectric material or an antiferroelectric material having a tetragonal phase dominant thickness.
In the similar field of endeavor of semiconductor storage devices, Okuno discloses wherein the information storage layer comprises a ferroelectric material having an orthorhombic phase dominant thickness (“the abundance ratio of orthorhombic crystals contained in the ferroelectric layer 222 is higher”, ¶ [0043]), and
wherein the fixed layer comprises a paraelectric material or an antiferroelectric material having a tetragonal phase dominant thickness (“the paraelectric layer 122 may include… tetragonal crystals”, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the layers of Nan with the crystal phases as disclosed by Okuno, to obtain the desired ferroelectric properties (see Okuno, ¶ [0043]).
Regarding claim 18, Figs. 4a-4b of Nan disclose a semiconductor device comprising:
a substrate (substrate of 10);
a plurality of word lines (14) extending on the substrate (substrate of 10) in a first direction and apart from one another in a second direction perpendicular to the first direction;
a plurality of bit lines (17) extending on the substrate (substrate of 10) in the second direction and apart from one another in the first direction; and
a plurality of memory cells (1, 10) arranged between the plurality of word lines (14) and the plurality of bit lines (17) and each including a cell transistor (10) and a memcitor (1) connected to the cell transistor (10), wherein the memcitor (1) includes:
an information storage layer (4) including a ferroelectric material;
a fixed layer (8, 9) that does not contact the first electrode (3) and the second electrode (2), that is stacked on the information storage layer (4), and that includes a paraelectric material or an antiferroelectric material; and
a third electrode (18) connected to the fixed layer (8, 9) without contacting the information storage layer (4), and
wherein a gate, a source, and a drain of a cell transistor (10) of each of the plurality of memory cells (1, 10) is connected to one of the plurality of word lines (14), one of the plurality of bit lines (17), and the second electrode (2) of the memcitor (1).
Nan fails to explicitly disclose the information storage layer including a ferroelectric material with an orthorhombic phase;
the fixed layer includes a paraelectric material or an antiferroelectric material with an orthorhombic phase.
In the similar field of endeavor of semiconductor storage devices, Okuno discloses the information storage layer including a ferroelectric material with an orthorhombic phase (“the abundance ratio of orthorhombic crystals contained in the ferroelectric layer 222 is higher”, ¶ [0043]);
the fixed layer includes a paraelectric material or an antiferroelectric material with an orthorhombic phase (“the paraelectric layer 122 may include… orthorhombic crystals”, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the layers of Nan with the crystal phases as disclosed by Okuno, to obtain the desired ferroelectric properties (see Okuno, ¶ [0043]).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nan (CN 101834271 A) in view of Lim et al. (US 20200286985 A1) herein after “Lim”.
Regarding claim 4, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 1 as applied above, but fail to disclose wherein the information storage layer has a stacked structure including a plurality of sub-information storage layers sequentially arranged between the first electrode and the second electrode.
In the similar field of endeavor of semiconductor memory devices, Fig. 6 of Lim discloses the information storage layer (Fig. 6, third ferroelectric film 212, ¶ [0100]) has a stacked structure including a plurality of sub-information storage layers (Fig. 6, first sub-dielectric film 212a, a second sub-dielectric film 212b, ¶ [0101]) sequentially arranged between the first electrode (Fig. 6, first electrode 100, ¶ [0038]) and the second electrode (Fig. 6, second electrode 110, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the information storage layer of Nan with the sub-layers as disclosed by Lim, to improve the capacitance properties (see Lim, ¶ [0006]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Nan (CN 101834271 A) in view of Hua et al. (US 20240172411 A1) herein after “Hua”.
Regarding claim 16, Figs. 4a-4b of Nan disclose the semiconductor device as claimed in claim 15 as applied above, but fail to disclose wherein a channel layer of the cell transistor has a channel length extending in the vertical direction.
In the similar field of endeavor of semiconductor devices, Fig. 7A of Hua discloses wherein a channel layer (Fig. 7A, channel region 211, ¶ [0088]) of the cell transistor has a channel length extending in the vertical direction (“the columnar transistor 210 provided in the embodiment of the disclosure has a vertical channel (that is, the channel region 211)”, ¶ [0088]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the channel layer of Nan with the vertical channel length as disclosed by Hua, to reduce the area and increase storage density (see Hua, ¶ [0234]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Nan (CN 101834271 A) and Okuno (WO 2022176549 A1) in view of Suh et al. (US 20240081082 A1) herein after “Suh”.
Regarding claim 20, Nan and Okuno together disclose the semiconductor device as claimed in claim 18 as applied above, but the combination fails to disclose wherein a thickness of the information storage layer is about 10 Å to about 100 Å in a direction between the first electrode and the second electrode, and
wherein a thickness of the fixed layer is about 5 Å to about 50 Å in a direction perpendicular to a surface of the information storage layer, which contacts the fixed layer.
In the similar field of endeavor of semiconductor devices, Fig. 7 of Suh discloses wherein a thickness of the information storage layer (Fig. 7, ferroelectric layer 120, ¶ [0094]) is about 10 Å to about 100 Å (“The ferroelectric layer 120 may have a thickness of 1 nm to 5 nm”, ¶ [0094]) in a direction between the first electrode (Fig. 7, first electrode 110, ¶ [0088]) and the second electrode (Fig. 7, second electrode 150, ¶ [0088]), and
wherein a thickness of the fixed layer (Fig. 7, dielectric layer 130, ¶ [0095]) is about 5 Å to about 50 Å (“The dielectric layer 130 may have a thickness of 1 nm to 5 nm”, ¶ [0095]) in a direction perpendicular to a surface of the information storage layer (120), which contacts the fixed layer (130).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the layers of Nan with the thicknesses as disclosed by Suh, to obtain the desired device characteristics (see Suh, ¶ [0004]).
Allowable Subject Matter
Claims 5, 10-11,and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art of record alone or in combination fails to disclose or fairly suggest “wherein the fixed layer contacts each of the plurality of sub-information storage layers” in combination with the other limitations of claim 5.
Regarding claim 10, the prior art of record alone or in combination fails to disclose or fairly suggest “wherein a magnitude of a voltage applied between the first electrode and the second electrode to generate fixed polarization in the information storage layer is inversely proportional to that of a voltage applied to the third electrode” in combination with the other limitations of claim 10.
Claim 11 is indicated as allowable based on its dependence on claim 10.
Regarding claim 19, the prior art of record alone or in combination fails to disclose or fairly suggest “wherein at least some of the plurality of sub-information storage layers have polarization directions different from those of remaining sub-information storage layers” in combination with the other limitations of claim 19.
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893