DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang et al. (20120056315) in view of Yang et al. (20100267217)
Regarding Claim 1, in Figs. 1 and 7, Chang et al. discloses an interposer (see paragraph 0012), comprising: a substrate 10 with a first surface and a second surface opposite from the first surface; a via 20/20A/20b through the substrate, wherein a portion of the via extends past the second surface (see Fig. 3) a first layer 24/24A/24B/28 over the substrate, wherein the first layer is an electrically insulating material; and a second layer 24/24A/24B/28 over the first layer and over the portion of the via that extends past the second surface. Chang et al. fails to disclose the newly added limitation with respect to a liner surrounding the via, wherein a portion of the liner extends past the second surface. However, Yang et al. discloses a semiconductor device where in Fig. 10, elements 126/117 and 110, the required liner structure is disclosed. (Here TSV is 126, liner is 117 and “recessed” substrate is 110)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required liner structure in Chang et al. as taught by Yang et al. in order to protect the TSV and the layers around it.
Regarding Claim 2, in Figs 3 of Chang et al, a step height of the portion of the via 20/20A/20B that extends past the second surface is approximately 0.1 micrometer or greater.
Regarding Claim 3, in Chang et al., the second layer 24/24A/24B/28 comprises:a third layer 24/24A/24B/28 comprising titanium; and a fourth layer 24/24A/24B/28 comprising copper.
Regarding Claim 4, in Chang et al, the third layer 24/24A/24B/28 comprises a barrier layer, and wherein the fourth layer comprises a seed layer.
Regarding Claim 5, in Chang et al, the first layer 24/24A/24B/28 comprises silicon and nitrogen.
Regarding Claim 6, in Chang et al, the substrate 10 comprises silicon.
Regarding Claim 8, in Chang et al, an electrically conductive bump 30 over the second layer.
Regarding Claim 9, in Chang et al, a width of the electrically conductive bump 30 is substantially equal to a width of the second layer.
Regarding Claim 10, in Chang et al, the first layer is wider than the second layer.
Regarding Claim 11, in Chang et al, the via is a through silicon via (TSV) that passes through an entire thickness of the substrate (see Fig.3).
Regarding Claim 12, in Chang et al, it is disclosed a multi-die module, comprising :an interposer (paragraph 0012), comprising: a substrate 10 with a first surface and a second surface opposite from the first surface; a via 20/20a/20b through the substrate, wherein an end of the via extends up past the second surface of the substrate (Fig. 3); and a layer 24/24A/24B/28 comprising copper around the end of the via; a first die coupled to the interposer; and a second die coupled to the interposer (see paragraph 0012, interposer is inherently for a multi-die). Chang et al. fails to disclose the newly added limitation with respect to a liner surrounding the via, wherein a portion of the liner extends past the second surface. However, Yang et al. discloses a semiconductor device where in Fig. 10, elements 126/117 and 110, the required liner structure is disclosed. (Here TSV is 126, liner is 117 and “recessed” substrate is 110)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required liner structure in Chang et al. as taught by Yang et al. in order to protect the TSV and the layers around it.
Regarding Claim 13, in paragraph 0012 of Chang et al, the first die is communicatively coupled to the second die through the interposer.
Regarding Claim 14, in Fig. 7 of Chang et al, the first die is coupled to the interposer through a bump 30 or through a bumpless die-to-die interconnect.
Regarding Claim 15, in Chang et al, the layer 24/24A/24B/28 comprising copper is over a layer comprising titanium.
Regarding Claim 16, in Chang et al, the layer c24/24A/24B/28 comprising copper has a horizontal portion over a top of the via, and vertical portions along sidewalls of the via.
Regarding Claim 17, in Chang et al, a layer 24/24A/24B/28 comprising silicon and nitrogen is provided over the second surface of the substrate.
Regarding Claim 18, in Chang et al, an electronic system, comprising: a board; a package substrate coupled to the board; and a multi-die module coupled to the package substrate (see paragraph 0012), wherein the multi-die module comprises: an interposer (see paragraph 0012) with a via 20/20A/20B with an end that extends past a top surface of the interposer (Fig. 3); a laye r24/24A/24B/28 comprising copper over and around the end of the via; a first die coupled to the interposer through the bump; and a second die coupled to the interposer (see paragraph 0012). Chang et al. fails to disclose the newly added limitation with respect to a liner surrounding the via, wherein a portion of the liner extends past the second surface. However, Yang et al. discloses a semiconductor device where in Fig. 10, elements 126/117 and 110, the required liner structure is disclosed. (Here TSV is 126, liner is 117 and “recessed” substrate is 110)
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required liner structure in Chang et al. as taught by Yang et al. in order to protect the TSV and the layers around it.
Regarding Claim 19, in Chang et al, the via 20/20A/20B has a step height above the top surface of the interposer that is approximately 0.1pm or greater.
Regarding Claim 20, in Chang et al, in paragraph 0012, the electronic system is part of a personal computer, a server, a mobile device, a tablet, or an automobile.
Examiner is including Chiang et al, 20150348871 (Fig. 2, paragraph 0018) as pertinent prior art reference that is not applied on this rejection but that discloses a recessed substrate, a TSV and a liner protruding above the recessed substrate).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 9/28/2026
