CTNF 18/141,887 CTNF 79135 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chang et al. (20120056315) . Regarding Claim 1, in Figs. 1 and 7, Chang et al. discloses an interposer (see paragraph 0012), comprising: a substrate 10 with a first surface and a second surface opposite from the first surface; a via 20/20A/20b through the substrate, wherein a portion of the via extends past the second surface (see Fig. 3) a first layer 24/24A/24B/28 over the substrate, wherein the first layer is an electrically insulating material; and a second layer 24/24A/24B/28 over the first layer and over the portion of the via that extends past the second surface. Regarding Claim 2, in Figs 3 a step height of the portion of the via 20/20A/20B that extends past the second surface is approximately 0.1 micrometer or greater. Regarding Claim 3, the second layer 24/24A/24B/28 comprises:a third layer 24/24A/24B/28 comprising titanium; and a fourth layer 24/24A/24B/28 comprising copper. Regarding Claim 4, the third layer 24/24A/24B/28 comprises a barrier layer, and wherein the fourth layer comprises a seed layer. Regarding Claim 5, the first layer 24/24A/24B/28 comprises silicon and nitrogen. Regarding Claim 6, the substrate 10 comprises silicon. Regarding Claim 7, a liner 24/24A/24B/28 surrounds the via. Regarding Claim 8, an electrically conductive bump 30 over the second layer. Regarding Claim 9, a width of the electrically conductive bump 30 is substantially equal to a width of the second layer. Regarding Claim 10, the first layer is wider than the second layer. Regarding Claim 11, the via is a through silicon via (TSV) that passes through an entire thickness of the substrate (see Fig.3). Regarding Claim 12, a multi-die module, comprising :an interposer (paragraph 0012), comprising: a substrate 10 with a first surface and a second surface opposite from the first surface; a via 20/20a/20b through the substrate, wherein an end of the via extends up past the second surface of the substrate (Fig. 3); and a layer 24/24A/24B/28 comprising copper around the end of the via; a first die coupled to the interposer; and a second die coupled to the interposer (see paragraph 0012, interposer is inherently for a multi-die). Regarding Claim 13, in paragraph 0012, the first die is communicatively coupled to the second die through the interposer. Regarding Claim 14, in Fig. 7, the first die is coupled to the interposer through a bump 30 or through a bumpless die-to-die interconnect. Regarding Claim 15, the layer 24/24A/24B/28 comprising copper is over a layer comprising titanium. Regarding Claim 16, the layer c24/24A/24B/28 comprising copper has a horizontal portion over a top of the via, and vertical portions along sidewalls of the via. Regarding Claim 17, a layer 24/24A/24B/28 comprising silicon and nitrogen is provided over the second surface of the substrate. Regarding Claim 18, in Chang et al, an electronic system, comprising: a board; a package substrate coupled to the board; and a multi-die module coupled to the package substrate (see paragraph 0012), wherein the multi-die module comprises: an interposer (see paragraph 0012) with a via 20/20A/20B with an end that extends past a top surface of the interposer (Fig. 3); a laye r24/24A/24B/28 comprising copper over and around the end of the via; a first die coupled to the interposer through the bump; and a second die coupled to the interposer (see paragraph 0012). Regarding Claim 19, the via 20/20A/20B has a step height above the top surface of the interposer that is approximately 0.1pm or greater. Regarding Claim 20, in paragraph 0012, the electronic system is part of a personal computer, a server, a mobile device, a tablet, or an automobile. = Examiner is including Wirz 2015033014, Hu (20180096889), Yang (20150127392) and Liang et al. (20140077369) as pertinent prior art references that are not relied upon but that discloses through vias/TSV aligned with the bumps in a package structure. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FAZLI ERDEM/Primary Examiner, Art Unit 2812 5/17/2026 Application/Control Number: 18/141,887 Page 2 Art Unit: 2812 Application/Control Number: 18/141,887 Page 3 Art Unit: 2812 Application/Control Number: 18/141,887 Page 4 Art Unit: 2812 Application/Control Number: 18/141,887 Page 5 Art Unit: 2812
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