DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 11/20/2025, with respect to the drawing objections, and claim rejections under 35 USC 112 and 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made incorporating US 7189617 B2 Slesazeck.
Applicant's arguments filed 11/20/2025 have been fully considered but they are not persuasive regarding the 35 USC 103 rejection of claim 4. The applicants’ arguments only address base reference Togo and do not address the combination of Togo in view of Slesazeck.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
However, as the 35 USC 103 rejection of claim 4 was made in view of claim 1, the rejection has been withdrawn a new ground(s) of rejection is made incorporating US 7189617 B2 Slesazeck into claim 1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, and 10-25 are rejected under 35 U.S.C. 103 as being obvious over US 20230079098 A1 Togo et al. and in further view of US 7189617 B2 Slesazeck et al hearafter “Slesazeck”
Claim 1 Togo teaches a transistor structure (60A the embodiment as represented in figs. 23) comprising: a body (8 comprising 10, 36A, 31A, 32A, 38A, 39A, illustrated in figs. 23) with a single convex structure (36A, 31A and 39A illustrated in figs. 23, meets the limitation under broadest reasonable interpretation and MPEP 2112.01 as it structurally matches the body with the single convex structure 202 as illustrated in fig. 21 of the instant application) , wherein the convex structure is made of a first semiconductor material [Paragraph 0192 “the first channel region 36A can have a doping of a first conductivity type” this meets the limitation under broadest reasonable interpretation], and a trench [best illustrated fig. 23A] is formed in the single convex structure;
a gate structure (comprising 52A and 50A figs. 23) with a gate conductive layer (52A figs. 23) and a gate dielectric layer (50A figs. 23), wherein the gate conductive layer is across over the single convex structure, and a portion (52F figs. 23) of the gate conductive layer is filled in the trench, and a source region (32A figs. 23, best illustrated fig. 23C) contacting with a first end (left end fig. 23C) of the single convex structure.
Togo does not teach the gate structure covers two most outer sidewalls of the single convex structure.
Slesazeck teaches a gate comprising (30’ fig. 7A-7B) covers two most outer sidewalls a convex structure [see annotation below].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the transistor structure of Togo and change the shape and/or relative proportions such that “the gate structure… covers two most outer sidewalls of the single convex structure” as Slesazeck teaches to improve the control of the gate over the channel region [column 3 lines 40-50 Slesazeck] and/or changes in shape and/or relative proportions is prima facie type obviousness [See MPEP 2144.04 IV. A. and/or B.]
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Annotated figs. 7 Slesazeck: highlighting the Single convex structure and two most outer sidewalls
Claim 2 Togo in view of Slesazeck as shown above teaches the transistor structure in claim 1, wherein a bottom surface (the bottom surface of the trench, best illustrated fig. 23A) and sidewalls (the sidewalls of the trench, best illustrated fig. 23A) of the trench are covered by the gate dielectric layer.
Claim 3 Togo in view of Slesazeck as shown above teaches the transistor structure in claim 1, wherein the convex structure comprises a first outer sidewall [see annotation below] and a second outer sidewall [see annotation below] covered by the gate conductive layer (best illustrated fig. 23A, met under broadest reasonable interpretation wherein the tops of the first outer sidewall and the second outer sidewall is covered by the gate conductive layer covers), the convex structure further comprises a first inner sidewall [see annotation below] and a second inner sidewall [see annotation below] in the trench (best illustrated fig. 23A ); wherein a length of the first inner sidewall or the second inner sidewall (the height of the first or second inner sidewall) is shorter than a length of the first outer sidewall or the second outer sidewall (the height of the first or second outer sidewall)[best illustrated in fig. 23A, see annotation below].
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Annotated fig. 23A
Claim 4 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 1,teaches a STI region (20 figs. 23 Togo)
Togo does not teach a bottom of the gate structure above a STI region surrounding the body is lower than a bottom of the source region.
Slesazeck teaches a bottom of the gate structure (5a fig. 7A-7B) above a STI region (IT fig. 7B-7A) surrounding the body is lower than a bottom of the source region (the bottom of 4’). [this limitation is met under broadest reasonable interpretation as the bottom of the gate structure is above at least a portion of the STI region, See annotation below. In addition, the bottom of the gate structure is depicted as lower than surface U fig. 7A-7B, which is clearly indicated at lower than 4’ fig. 7A].
As shown in claim 1 it would have been obvious to modify Togo in view Slesazeck such that “a bottom of the gate structure above a STI region surrounding the body is lower than a bottom of the source region” for the same reasons as presented in claim 1.
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Annotated figs. 7 Slesazeck: highlighting a portion of the STI region that the gate region is above.
Claim 5 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 1, wherein the single convex structure comprises two vertical thin bodies (31A and 39A), and the gate dielectric layer is disposed between the gate conductive layer and the two vertical thin bodies [best illustrated fig. 23C].
Claim 6 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 5, further comprising:;
a drain region (38A figs. 23 best illustrated fig. 23C) contacting with a second end (the right end fig. 23C) of the single convex structure;
a first concave [see annotation below] accommodating the source region; and
a second concave [see annotation below] accommodating the drain region;
wherein sidewalls of the first concave and sidewalls of the second concave are surrounded by a STI region (20 figs. 23).
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Annotated fig. 23C
Claim 7 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 6, wherein an edge (right edge fig. 23C) of the source region contacts with the two vertical thin bodies, and an edge (left edge fig. 23C) of the drain region contacts with the two vertical thin bodies.
Claim 8 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 7, wherein the source region comprises: an LDD region [31A sufficiently disclosed paragraph 0140 with a dopant concentration between
1.0
*
10
17
/
c
m
3
to
1.0
*
10
20
/
c
m
3
] that forms the two vertical thin bodies;
a heavily doped region [32A sufficiently disclosed paragraph 0142 with a dopant concentration between
5.0
*
10
18
/
c
m
3
to
2.0
*
10
21
/
c
m
3
] laterally extending from the LDD region [illustrated fig. 23C];
and a metal region (82A sufficiently disclosed in paragraph 0195 “contact via structure” comprising “one conductive material”) being in the first concave (met under broadest reasonable interpretation, 82A is illustrated as being in the opening of the first concave fig. 23C) and contacting with a sidewall (the top vertical side wall of 32A fig. 23C, met under broadest reasonable interpretation of “sidewall”) of the heavily doped region.
Togo does not teach an LDD region contacting with the two vertical thin bodies;
Slesazeck teaches an LDD region contact (4 figs. 7) with two vertical thin bodies [see annotation below, “thin” relative to the semiconductor body 1 figs. 7].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to change the size and/or shape of LDD region and channel region taught by Togo such that there is “an LDD region contacting with the two vertical thin bodies” instead of --an LDD region that forms the two vertical thin bodies-- for the benefit of “excellent scaling characteristics” and/or to be “assured that the source/drain regions are suitably connected to the channel region along the trench periphery” [Slesazeck Column 4 lines 30-35] and/or changes in size and/or relative shape is prima facie type obviousness [See MPEP 2144.04 IV. A. and/or B.]
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Annotated fig. 7A Slesazeck: highlighting the two vertical thin sidewalls
Claim 10 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 5, wherein the width of one vertical thin body [see annotation below] is less then 5nm to 100nm. [disclosed in Paragraph 0172 “the thickness of the horizontally-extending portions of the first source/drain extension regions (31A, 39A) that underlie the bottom surface of each line trench 49 may be in a range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although lesser and greater vertical distances may also be employed” wherein fig. 23C sufficiently illustrates a width of one vertical thin body is less than the horizontally-extending portions [see annotation below].
Togo does not explicitly teach a width of one vertical thin body is not greater than 3nm.
It would have been obvious to one of or ordinary skill in the art before the effective filing date of the claimed invention to take the device of Togo and modify it such that “a width of one vertical thin body is not greater than 3nm” as where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists [See MPEP 2144.05 I.].
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Annotated fig. 23C: highlighting the width of one vertical thin body and a width of a horizontally-extending portion.
Claim 11 Togo teaches as shown above a transistor (60A of figs. 23) structure comprising: a body (8 figs. 23) with a convex structure (comprising 36A, 31A, and 39A figs. 23) which has an original surface [the top most surface of 36A, the surfaces of the convex structures are original under broadest reasonable interpretation of “original” and/or MPEP 2112.01 as it is structurally the same as disclosed],
wherein the body is made of a semiconductor material [Paragraph 0192 “the first channel region 36A can have a doping of a first conductivity type” this meets the limitation under broadest reasonable interpretation], and the convex structure has multiple conductive channels [36A sufficiently illustrated fig 23A and/or met under MPEP 2112.01 fig 23A matches required structure of the conductive channel structure 202 as illustrated in fig. 21 of the instant application, not the instant applicant is disclosed as having two channels [paragraph 0021] and illustrated fig. 21 of the instant application, Togo appears to have five channels figs. 23];
a source region (32A figs. 23, best illustrated fig. 23C) contacting with a first end of the convex structure (left end fig. 23C);
a drain region (38A figs. 23, best illustrated fig. 23C) contacting with a second end of the convex structure (right end fig. 23C); and
a gate region (comprising 50A and 52A figs. 23) with a gate conductive layer (comprising 50A figs. 23), wherein the gate conductive layer is across over the convex structure [best illustrated fig. 23A], a first portion (52F figs. 23) of the gate conductive layer is in the convex structure and under the original surface [best illustrated fig. 23A], and a second portion (52P figs. 23) of the gate conductive layer is above the original surface [best illustrated fig. 23A];
wherein a length [left most side to right most side fig. 23A, see annotation below] of the second portion of the gate conductive layer is longer than a length [left most side to right most side fig. 23A see annotation below] of the first portion of the gate conductive layer [sufficiently illustrated fig. 23A].
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Annotated fig. 23A
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Annotated figs. 7 Slesazeck: highlighting the Single convex structure and two most outer sidewalls
Claim 12 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 11, wherein a trench (sufficiently illustrated fig. 23A) formed in the convex structure and between the first end and the second end [illustrated figs. 23], and the first portion of the gate conductive layer is filled in the trench [illustrated figs. 23, best illustrated 23A].
Claim 13 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 12, wherein the convex structure comprises two thin bodies extending upward (31A and 38A figs. 23, “thin body” best illustrated fig. 23C), and each thin body comprises two conductive channels along sidewalls of the thin body [best illustrated fig. 23E for 31A wherein the cross section of 23E is directly adjacent to the cross section of 23A, as illustrated in the top down view of Fig. 23B, 38A corresponds with 31A however is drain side instead of source side.].
Claim 14 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 13, wherein the trench filled with the first portion of the gate conductive layer is between the two thin bodies (best illustrated fig. 23C).
Claim 15 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 14, further comprising a gate dielectric layer (50A figs. 23) being across over the convex structure, wherein the first portion of the gate conductive layer is surrounded by the gate dielectric layer in the trench [best illustrated fig. 23A].
Claim 16 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 15, wherein the gate conductive layer is surrounded by the gate dielectric layer along four sidewalls [the side walls of the 52F in the trench, fig. 23A illustrates at least 8 sidewalls surrounding] and a bottom of the trench [illustrated fig. 23A].
Claims 17 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 16, wherein right under the bottom of the trench is the semiconductor material of the body [best illustrated fig. 23A], and the gate dielectric layer along the bottom of the trench directly contacts with the semiconductor material of the body [best illustrated fig. 23A].
Claims 18 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 11, further comprising an isolation wall (56 fig. 23A) clamping sidewalls of the convex structure [illustrated fig. 23A, met under broadest reasonable interpretation, appears to claim a small top portion of the sidewalls of the convex structure], and a STI layer (20 fig. 23A) surrounding the isolation wall [illustrated fig. 23A, met under broadest reasonable interpretation surrounds a recessed portion of the isolation wall].
Claim 19 Togo teaches a transistor structure [illustrated figs. 23] comprising: a semiconductor body with a single convex structure (8 comprising 10, 36A, 31A, 32A, 38A, 39A, illustrated in figs. 23), wherein the single convex structure comprises at least 4 upward extending conductor-oxide-semiconductor interfaces (fig. 23A illustrates at least 8 comprising gate electrode 52A [wherein an electrode qualifies as a conductor] - gate dielectric 50A [“thermal silicon oxide” Paragraph 151] – channel region 36A [sufficiently disclosed “Each channel region may have a dopant concentration of the first conductivity type” paragraph 0143 in view of the semiconductor material layer 10 “single crystal silicon” paragraph 0105]);
wherein the at least 4 upward extended conductor-oxide-semiconductor interfaces are horizontally shifted with each other [illustrated fig. 23A]
Togo does not teach two upward extending interfaces conductor-oxide-semiconductor interfaces of the at least 4 upward extending conductor-oxide-semiconductor interfaces are positioned at two most outer sidewalls of the single convex structure.
Slesazeck teaches two upward extending interfaces gate interfaces [sufficiently illustrated fig. 7A-7B wherein the gate comprises 30’] are positioned at two most outer sidewalls of a single convex structure [sufficiently illustrated fig. 7A-7B see annotation below].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the transistor structure of Togo and change the shape and/or relative proportions such that “two upward extending interfaces conductor-oxide-semiconductor interfaces of the at least 4 upward extending conductor-oxide-semiconductor interfaces are positioned at two most outer sidewalls of the single convex structure” as Slesazeck teaches to improve the control of the gate over the channel region [column 3 lines 40-50 Slesazeck] and/or changes in shape and/or relative proportions is prima facie type obviousness [See MPEP 2144.04 IV. A. and/or B.]
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Annotated figs. 7 Slesazeck: highlighting the Single convex structure and two most outer sidewalls
Claim 20 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 19, wherein the single convex structure comprises two upward extending thin bodies (31A and 39A, best illustrated Fig. 23C), and each upward extending thin body comprises two upward extending conductor-oxide-semiconductor interfaces ( 52A [as shown in claim 19] – 50A [as shown in claim 19] – 31A/39A [sufficiently disclosed Paragraph 0140, “Electrical dopants can be implanted into unmasked portions of the semiconductor material layer 10 that are not masked by a respective combination of an implantation mask layer and the gate stacks to form various source/drain extension regions (31A, 39A, 31B, 39B, 31C, 39C, 31D, 39D)” wherein of the semiconductor material layer 10 “single crystal silicon” paragraph 0105].
Claim 21 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 20, wherein a trench (see annotation below) is formed in the single convex structure to separate the two upward extending thin bodies [illustrated fig. 23C].
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Annotated Fig. 23C: highlighting the trench
Claim 22 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 19, further comprising:
a single source region (32A, best illustrated fig. 23C) selectively grown from a first end (left end in fig. 23C) of the single convex structure; and
a single drain region (38A, best illustrated fig. 23C) selectively grown from a second end (right end in fig. 23C) of the single convex structure.
[The limitation for “selectively grown” is sufficiently met under MPEP 2113 as “the product in the product-by-process claim is the same as or obvious from a product of the prior art” wherein “selectively grown” may broadly imply an epitaxial structure and/or poly/single crystal material. Paragraph 0105 sufficiently discloses “the semiconductor material layer 10 may comprise an epitaxial semiconductor (e.g., single crystal silicon) layer” in view of paragraph 0142 “Electrical dopants can be implanted into unmasked portions of the semiconductor material layer 10 that are not masked by a respective combination of an implantation mask layer, the gate stacks, and the dielectric gate spacers 56 to form various deep source/drain regions (32A, 38A, 32B, 38B, 32C, 38C, 32D, 38D)”].
Claim 23 Togo teaches a transistor structure (figs. 23C) comprising:
a semiconductor body (8 comprising 10, 36A, 31A, 32A, 38A, 39A, illustrated in figs. 23) with a convex structure ()36A, 31A and 39A illustrated in figs. 23, meets the limitation under broadest reasonable interpretation and MPEP 2112.01 as it structurally matches the body with the single convex structure 202 as illustrated in fig. 21 of the instant application) which comprises at least two upward extending bodies (31A and 39A, best illustrated fig. 23), wherein the semiconductor body is made of a first semiconductor material [sufficiently disclosed as doped single crystal silicon in Paragraph 0105 “the semiconductor material layer 10 may comprise an epitaxial semiconductor (e.g., single crystal silicon) layer” and “Electrical dopants can be implanted into unmasked portions of the semiconductor material layer 10 that are not masked by a respective combination of an implantation mask layer, the gate stacks, and the dielectric gate spacers 56 to form various deep source/drain regions (32A, 38A, 32B, 38B, 32C, 38C, 32D, 38D)” Paragraph 0142];
a trench [see annotation below] formed in the single convex structure to separate the at least two upward extending bodies; and
a gate region (comprising 52A and 50A fig. 23C) across over the convex structure,
wherein no STI region is between the two upward extending bodies [sufficiently illustrated fig. 23C];
Togo does not teach the gate region covering two most outer sidewalls of the convex structure.
Slesazeck teaches a gate comprising (30’ fig. 7A-7B) covers two most outer sidewalls a convex structure [see annotation below].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take the transistor structure of Togo and change the shape and/or relative proportions such that “the gate structure… covers two most outer sidewalls of the single convex structure” as Slesazeck teaches to improve the control of the gate over the channel region [column 3 lines 40-50 Slesazeck] and/or changes in shape and/or relative proportions is prima facie type obviousness [See MPEP 2144.04 IV. A. and/or B.]
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Annotated Fig. 23C: highlighting the trench
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Annotated figs. 7 Slesazeck: highlighting the Single convex structure and two most outer sidewalls
Claim 24 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 23, further comprising:
a source region (32A, best illustrated fig. 23C) contacting with a first end (left end in fig. 23C) of the convex structure; and
a drain region (38A fig. 23C) contacting with a second end (right end in fig. 23C) of the convex structure;
wherein the gate region (comprising 52A and 50A fig. 23C) has a gate conductive layer (52A fig. 23C), wherein the gate conductive layer is across over the convex structure [sufficiently illustrated fig. 23C and 23A].
Claim 25 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 23, wherein a bottom (the bottom of the trench) of the trench directly contacts with the first semiconductor material [sufficiently illustrated fig. 23C].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over obvious as applied to the claims above, US 7575964 B2 Oh et al hereafter “Oh”.
Claim 9 Togo in view of Slesazeck teaches as shown above the transistor structure in claim 6
Togo does not teach an oxide layer positioned in the first concave, wherein the oxide layer comprises a vertical portion and a lateral portion covering a bottom of the first concave; wherein a top surface of the vertical portion is higher than a top surface of the lateral portion; and
a nitride layer above the oxide layer.
Oh teaches Columns 4 line 62 to column 5 line 19 “a buried insulating layer 37 is interposed between the drain region 47d and the lower semiconductor substrate. The buried insulating layer 37 may be a silicon oxide layer (SiO.sub.2), and may be stacked layers of the silicon oxide layer and a silicon nitride layer (SiN)” and “The buried insulating layer 37 may have an extension portion which is partially interposed between the channel region 47c and the lower semiconductor substrate 21”.
It would have been obvious to one of ordinary skill in the art to combine the device as taught by Togo with the device as taught by Oh such that there is “an oxide layer positioned in the first concave, wherein the oxide layer comprises a vertical portion and a lateral portion covering a bottom of the first concave” and “a nitride layer above the oxide layer” to reduce an intensity of the electric field generated, and/or to prevent leakage current, and/or to prevent the generation of floating body effects [Oh Columns 4 line 62 to column 5 line 19 “].
In view of the modification above the limitation “a top surface of the vertical portion is higher than that of the lateral portion” would necessarily be met as the vertical sides of the concave extend higher than the lateral bottom of the concave.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/WCT/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893