Prosecution Insights
Last updated: August 17, 2026
Application No. 18/142,421

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Final Rejection §103§112
Filed
May 02, 2023
Priority
Jun 21, 2022 — RE 10-2022-0075651
Examiner
MALSAWMA, LALRINFAMKIM HMAR
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
LG Display Co., Ltd.
OA Round
2 (Final)
90%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
997 granted / 1102 resolved
+22.5% vs TC avg
Moderate +9% lift
Without
With
+8.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
26 currently pending
Career history
1131
Total Applications
across all art units

Statute-Specific Performance

§101
1.0%
-39.0% vs TC avg
§103
43.0%
+3.0% vs TC avg
§102
35.8%
-4.2% vs TC avg
§112
10.2%
-29.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1102 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Applicant is advised that should claim 1 be found allowable, claim 11 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 23-26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Each of claims 23-26 recites a specific range (5%, 3%, 2%, 1%, respectively) in addition to the range of about 10% from independent claim 1; therefore, claims 1 and 23-26 are indefinite because it is not clear whether the claims require a range of about 10% or the specific range of 5%, 3%, 2%, 1%, respectively, i.e., a range of 1%, 2%, 3%, or 5% is clearly not a range of about 10%. For the purpose of examination, claim 1 will be interpreted as requiring “a range of about 10% or less” in order to properly examine claims 23-26 along with all other pending claims. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-3, 5-7, 12, 23-26, 28 and 29 (as interpreted) is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2019/0206973 A1; hereinafter, “Kim”, of record) in view of Lee et al. (US 2008/0023694 A1; hereinafter, “Lee”). Regarding claims 1 and 11 (as interpreted), Kim discloses a display device comprising: a buffer layer 120 (Fig. 4 and [0065]) located on a substrate 100 [0065]; an active layer 210 (Fig. 4 and [0062]) located on the buffer layer 120, and including a channel region (e.g., portion of “210” that is underneath “220” in Fig. 4), a first region (underneath “261” in Fig. 4) located on a first side (left side) of the channel region, and a second region (portion of “210” that is underneath “266” in Fig. 4) located on a second side (right side) of the channel region; a first conductor 261 (Fig. 4 and [0078]) located on the first region of the active layer; and a second conductor 266 (Fig. 4 and [0078]) located on the second region of the active layer, wherein in the buffer layer 120, a portion of an upper surface overlapping the active layer 210 has a first surface roughness (inherent), and a portion of the upper surface not overlapping the active layer 210 has a second surface roughness (inherent), and Kim does not explicitly disclose a range for a difference in the surface roughness of the first and second surfaces; accordingly, Kim does not disclose the lined-through limitations. Lee teaches (in Fig. 3 and [0008]), in a similar device, a buffer layer 141 has a surface roughness 150 that is larger in a portion of the buffer layer that is farther away from an active layer 124. Lee shows (in Fig. 3) the surface roughness at a boundary with an edge of the active layer 124 is similar to that of a surface roughness of the buffer layer 141 located beneath the active layer 124. Lee discloses that reducing the surface roughness of the buffer layer is important to prevent a short-circuit [0008]. It would have been obvious to one of ordinary skill in the art to modify Kim to ensure the first surface roughness has a difference of about 10% or less from the second surface roughness because Lee discloses large surface roughness produces short-circuit; accordingly, ensuring a surface roughness difference of about 10% or less would significantly assist in preventing a short-circuit. Regarding claims 2, 3, 5-7, 12, 23-26, 28 and 29 (as interpreted): re claim 2, Kim discloses: a gate insulating layer 220 (Fig. 4 and [0069]) located on the channel region; a first electrode 262/263 (Fig. 4 and [0078]) electrically connected to the first conductor 261; a second electrode 267/268 (Fig. 4 and [0078]) electrically connected to the second conductor 266; and a third electrode 231/232 (Fig. 4 and [0069]) located on the gate insulating layer 220 and overlapping the channel region, wherein the first conductor 261 is a first auxiliary electrode for an electrical connection between the first region and the first electrode 262/263, and the second conductor 266 is a second auxiliary electrode for an electrical connection between the second region and the second electrode 267/268; re claim 3, Kim discloses, wherein a conductive material included in the first conductor 261 and the second conductor 266 comprises either a metal (e.g., Ti, Mo, [0080]) included in the third electrode 231/232 (e.g., Ti, Mo, [0073]) or a transparent conductive oxide. re claim 5, Kim discloses, wherein the first electrode 262/263 (Fig. 4) comprises a first lower electrode 262 and a first upper electrode 263 electrically connected to each other, wherein the second electrode 267/268 comprises a second lower electrode 267 and a second upper electrode 268 electrically connected to each other, wherein the third electrode 230/231 comprises a third lower electrode 230 and a third upper electrode 231 electrically connected to each other, and wherein the first lower electrode 262 (Cu, [0081]), the second lower electrode 267 (Cu, [0081]), and the third lower electrode 231 (Ti, Mo [0073]) commonly comprise a first metal, and the first upper electrode 263 (ITO [0083]), the second upper electrode 268 (ITO [0083]), and the third upper electrode 232 (Cu, Al [0074]) commonly comprise a second metal different from the first metal (i.e., the lower electrodes are not required to comprise the same first metal, also, the upper electrodes are not required to comprise the same second metal); re claim 6, Kim discloses, further comprising a light shield 110 (Fig. 4) located between the substrate 100 and the buffer layer 120 and overlapping the channel region (e.g., the central portion of “210”), wherein the light shield 110 comprises a lower light shield 111 [0063] and an upper light shield 112 [0064] located on the lower light shield 110, wherein the lower light shield 111 comprises the first metal (e.g., Ti or Mo [0063]) included in the first lower electrode, the second lower electrode, and the third lower electrode 231; and wherein the upper light shield 112 comprises the second metal (Cu or Al [0064]) included in the first upper electrode, the second upper electrode, and the third upper electrode 232; re claim 7, Kim discloses, wherein the first lower electrode or the second lower electrode 267 (Fig. 4) is connected to the upper light shield 111 through through-holes of the buffer layer 120 and the gate insulating layer 220; re claim 12, Kim discloses, wherein at a boundary with an edge of the active layer, a difference in height (see “difference in height” in Fig. 4 below) between a portion of an upper surface of the buffer layer 120 overlapping the active layer 210 and a portion of the upper surface of the buffer layer 120 not overlapping the active layer 210; re claims 23-26, Kim (in view of Lee) renders obvious a surface roughness difference in a range of 10% or less; accordingly, it would have been obvious to one of ordinary skill in the art to further ensure a difference in surface roughness of 5%, 3%, 2%, or 1% because such smaller differences would ensure no short-circuits occurs; and re claims 28 and 29, Initially, with respect to the current claims, claim 1 will be reinterpreted with the following changes: an active layer 210 (Fig. 4 and [0062]) located on the buffer layer 120, and including a channel region (e.g., portion of “210” that is underneath “220” in Fig. 4), a first region (portion of “210” underneath “266” in Fig. 4) located on a first side (right side) of the channel region, and a second region (portion of “210” that is underneath “261” in Fig. 4) located on a second side (left side) of the channel region; a first conductor 266 (Fig. 4 and [0078]) located on the first region of the active layer; and a second conductor 261 (Fig. 4 and [0078]) located on the second region of the active layer; accordingly, with regard to claim 28, Kim further discloses a first electrode 110 directly connected to the first conductor 266, wherein the first electrode 110 directly contacts the buffer layer 120 (Fig. 4 and [0062-0063], wherein “110” comprises metal material electrically connected to the drain electrode 265, i.e., “110” can be referred to as an electrode); and with regard to claim 29, Kim further discloses a multi-layered light shield 110 located between the substrate 100 and the buffer layer 120 and overlapping the channel region (within “210”); and a first electrode 240 (Fig. 4 and [0076]) electrically connecting the multi-layered light shield 110 and the first conductor 266, wherein the first electrode 240 directly contacts the buffer layer 120 (i.e., the first electrode 240 is electrically connected to “266” and “210” at least when the pixel “P” in in Fig. 4 is on). Therefore, claims 2, 3, 5-7, 12, 23-26, 28 and 29 are rendered obvious by Kim in view of Lee. Claim(s) 27 (as interpreted) is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (in view of Lee) as applied to claim 1 above, and further in view of Lee et al. (US 2006/0008931 A1; hereinafter, “Lee-II”). Regarding claim 27: Kim (in view of Lee) does not disclose the buffer layer includes a first buffer layer and a second buffer layer; accordingly, Kim (in view of Lee) does not disclose the limitations in the current claim. Lee-II teaches, in a similar device, a buffer layer comprising a first buffer layer 132 (Fig. 1 and [0003]) disposed on a substrate 130 [0003] and a second buffer layer 134 [0003], wherein the first buffer layer includes a material different from a material of the second buffer layer, wherein the second buffer layer 134 includes silicon oxide, wherein a portion of an upper surface of the second buffer layer 134 overlapping an active layer P+/Poly/P+ (Fig. 1) has a first surface roughness, and a portion of the upper surface of the second buffer layer 134 not overlapping the active layer has a second surface roughness, wherein the first roughness and second roughness have a similar profile as that shown/disclosed by Lee. It would have been obvious to one of ordinary skill in the art to modify Kim (in view of Lee) by incorporating a buffer layer comprising two layers first and second buffer layers made of different materials, as taught by Lee-II, because the modification would provide etch selectively and etching control when forming subsequent pixel regions. Allowable Subject Matter Claims 4 and 8-10 (as interpreted) are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claims 4 and 8-10 are allowable for reasons stated in the prior Office action. Remarks The objections to the title and claims are withdrawn in view of the amendments. Applicant’s remarks have been carefully reviewed and considered, but they are moot in view of the new grounds of rejections. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to LEX H MALSAWMA whose telephone number is (571)272-1903. The examiner can normally be reached M-F (4-12 Hours, between 5:30AM-10PM). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /LEX H MALSAWMA/Primary Examiner, Art Unit 2892
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Prosecution Timeline

May 02, 2023
Application Filed
Dec 13, 2025
Non-Final Rejection (signed) — §103, §112
Jan 27, 2026
Non-Final Rejection mailed — §103, §112
Apr 23, 2026
Applicant Interview (Telephonic)
Apr 23, 2026
Examiner Interview Summary
Apr 27, 2026
Response Filed
Jul 28, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+8.8%)
2y 1m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1102 resolved cases by this examiner. Grant probability derived from career allowance rate.

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