DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed 06/16/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5 and 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US PGpub: 2020/0203498 A1), herein after Jo, in view of known arts like Zhu et al. (US 2021/0249539 A1), , herein after Zhu, in the same field of endeavor.
Regarding claim 1, Jo teaches a junction structure element comprising:
a semiconductor channel layer (217, FIG. 12) which includes a material having ferroelectric (dielectric film 400 may be provided between the ferroelectric film 110 and the substrate 200. The dielectric film 400 may be spaced apart from the first polarization enhancement film 120 by the ferroelectric film 110. For example, the dielectric film 400 may include at least one of Si oxides, Al oxides, Hf oxides, Zr oxides, and 2D insulators (such as a hexagonal boron nitride (h-BN))) and semiconductor properties (217 may include Si, Ge, SiGe, a Group III-V semiconductor, an organic semiconductor, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a 2D material, a quantum dot, or a combination thereof);
a source electrode and a drain electrode (source electrode 215 and the drain electrode 216 in FIG. 12) which are each in contact with the semiconductor channel layer (130, 400 and 217 constitutes channel layer) and are spaced apart from each other (as in FIG 12);
a ferroelectric layer (110) which is formed on the semiconductor channel layer (217) and includes a material having ferroelectric properties (Paragraph [0052]);
a gate electrode (300) disposed on the ferroelectric layer (110).; and
an insulating layer (400, FIG. 12) which is disposed between the semiconductor channel layer (217) and the ferroelectric layer (110) and includes a material having insulating properties (For example, the dielectric film 400 may include at least one of Si oxides, Al oxides, Hf oxides, Zr oxides, and 2D insulators (such as a hexagonal boron nitride (h-BN))).
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Jo does not explicitly teach wherein the semiconductor channel layer is configured to adjust a degree of polarization thereof in response to a voltage applied between the source electrode and the drain electrode.
However, Zhu teaches semiconductor channel layer is configured to adjust a degree of polarization thereof in response to a voltage applied between the source electrode and the drain electrode. It is mentioned in Paragraph [0066], [0067], [0071], [0079]. Let’s explain. The polarization layer 120 and 130 helps adjusting the degree and direction of polarization in order to improve the reliability of the device as in Jo. It is also mentioned in Zhu in ABSTRACT, Paragraph [0005], [0016], [0028]- [0041]), how voltage will be applied in source, drain and gate electrode and how polarization or conductivity of the transistor will be programmed. The polarity of the transistor 400 was switched from p-type to n-type when voltage applied on the embedded gates is changed from −3V to 3V. These results demonstrate that polarity of a black phosphorus transistor can be switched between pFET and nFET using the local program gates in the source/drain regions, as stated in Paragraph [0040] in Zhu.
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Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Jo’s junction structure element with other teaching from Jo or Zhu in order in order to improve the reliability of the device.
Regarding claim 4, Jo teaches the junction structure element of claim 2, wherein the insulating layer includes h-BN (For example, the dielectric film 400 may include at least one of Si oxides, Al oxides, Hf oxides, Zr oxides, and 2D insulators (such as a hexagonal boron nitride (h-BN)) in Paragraph [0074]).
Regarding claim 5, Jo teaches the junction structure element of claim 1, wherein the semiconductor channel layer and the ferroelectric layer include at least one material each independently differently selected from the group consisting of graphanol, hydroxyl-functionalized graphene, halogen- decorated phosphorene, g-C6N8H, Bi-CH2OH and two-dimensional perovskite including arsenic (As), antimony (Sb), bismuth (Bi), tellurium (Te), d1T-MoS2, t-MoS2, WS2, WSe2, WTe2, BiN, SbN, BiP, α-In₂Se₃, GaN, GaSe, SiC, BN, AIN, ZnO, GeS, GeSe, SnS, SnSe, SiTE, GeTe, SnTE, PbTe, CrN, CrB₂, CrBr₃, Crl₃, GaTeCI, AgBiP₂Se₆, CuCrP₂S₆, CuCrP₂Se₆, CuVP₂S₆, CuVP₂Se₆, CulnP₂Se₆, CulnP₂S₆ (CIPS), Sc₂CO₂, Bi₂O₂Se, Bi₂O₂Te, Bi₂O₂S, Ba₂PbCl₄ (Paragraph [0111], [0078]).
Regarding claim 7, Jo teaches the junction structure element of claim 1, wherein: a voltage applied between the source electrode and the drain electrode adjusts a degree of polarization in the horizontal direction of the semiconductor channel layer; and a voltage applied to the gate electrode adjusts a degree of polarization in the vertical direction of the ferroelectric layer (The direction of polarization is the intrinsic characteristics of the device. It is somewhat mentioned in Paragraph [0066], [0067], [0071], [0079]. The polarization layer 120 and 130 helps adjusting the degree and direction of polarization in order to improve the reliability of the device. It is also mentioned in Zhu et al. (US 2021/0249539 A1) in ABSTRACT, Paragraph [0005], [0016], [0028]- [0041]), how voltage will be applied in source, drain and gate electrode and how polarization or conductivity of the transistor will be programmed. “The polarity of the transistor 400 was switched from p-type to n-type when voltage applied on the embedded gates is changed from −3V to 3V. These results demonstrate that polarity of a black phosphorus transistor can be switched between pFET and nFET using the local program gates in the source/drain regions.” As stated in Paragraph [0040] in Zhu et al.).
Regarding claim 8, Jo teaches, in view of known arts, the junction structure element of claim 7, wherein an increasing or decreasing state of a current conducted in the semiconductor channel layer is determined according to an increasing or decreasing state of a current applied between the source electrode and the drain electrode and an increasing or decreasing state of a current applied to the gate electrode (The direction of polarization is the intrinsic characteristics of the device. It is somewhat mentioned in Paragraph [0066], [0067], [0071], [0079]. The polarization layer 120 and 130 helps adjusting the degree and direction of polarization in order to improve the reliability of the device. It is also mentioned in Zhu et al. (US 2021/0249539 A1) in ABSTRACT, Paragraph [0005], [0016], [0028]- [0041]), how voltage will be applied in source, drain and gate electrode and how polarization or conductivity of the transistor will be programmed. “The polarity of the transistor 400 was switched from p-type to n-type when voltage applied on the embedded gates is changed from −3V to 3V. These results demonstrate that polarity of a black phosphorus transistor can be switched between pFET and nFET using the local program gates in the source/drain regions.” As stated in Paragraph [0040] in Zhu et al.).
Regarding claim 9, Jo teaches, in view of known arts, the junction structure element of claim 7, wherein current conductivity of the semiconductor channel layer is determined according to a pulse of the voltage applied between the source electrode and the drain electrode and a pulse of the voltage applied to the gate electrode (he polarity of the transistor 400 was switched from p-type to n-type when voltage applied on the embedded gates is changed from −3V to 3V. These results demonstrate that polarity of a black phosphorus transistor can be switched between pFET and nFET using the local program gates in the source/drain regions.” As stated in Paragraph [0040] in Zhu et al.).
Regarding claim 10, Jo teaches, in view of known arts, the junction structure element of claim 1, wherein: the semiconductor channel layer has a thickness of 40 nm to 60 nm; and the ferroelectric layer has a thickness of 60 nm 100 nm (Channel thickness mentioned in Zhu et al. (US 2021/0249539 A1) in Paragraph [0038] or in RABKIN et al. (US: 2021/0264959 A1) in Paragraph [0097], the channel thickness can be adjusted based on device need to meet the current limitations to meet device functionality).
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Regarding claim 11, Jo teaches the junction structure element of claim 1, wherein the source electrode, the drain, and the gate electrode each include at least one material selected from the group consisting of titanium (Ti) and gold (Au) (Paragraph [0029]).
Claims 3, 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jo et al. (US PGpub: 2020/0203498 A1), herein after Jo, in view of Zhu and in further view of known arts like RABKIN et al. (US: 2021/0264959 A1), herein after RABKIN, in the same field of endeavor.
Regarding claim 3, Jo teaches, in view of RABKIN, the junction structure element of claim 2, wherein the insulating layer has a thickness of 5 nm to 10 nm (see paragraph [0156]-[0007], [0275] in RABKIN among other in order to control memory capacity of device so that device functionality can be achieved.).
Regarding claim 6, Jo teaches, in view of RABKIN, the junction structure element of claim 5, wherein: the semiconductor channel layer includes α-In2Se3 or SnS; and the ferroelectric layer includes CIPS (see paragraph [0006]-[0007], [0275] in RABKIN et al. (US: 2021/0264959 A1) among other in order to control memory capacity of device).
Regarding claim 15, Jo does not explicitly teach, in view of known arts like RABKIN et al. US PGpub: 2021/0264959, the junction structure element of claim 3, wherein the gate electrode is disposed directly on the ferroelectric layer.
However, it is known arts like RABKIN et al. wherein the gate electrode (51, FIG. 9) is disposed directly on the ferroelectric layer (21, FIG. 9) in order to meet the current limitations to meet device functionality.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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